drivers/net/ixgbe/ixgbe_pf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <stdlib.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12
  13 #include <rte_interrupts.h>
  14 #include <rte_log.h>
  15 #include <rte_debug.h>
  16 #include <rte_eal.h>
  17 #include <rte_ether.h>
  18 #include <rte_ethdev_driver.h>
  19 #include <rte_memcpy.h>
  20 #include <rte_malloc.h>
  21 #include <rte_random.h>
  22
  23 #include "base/ixgbe_common.h"
  24 #include "ixgbe_ethdev.h"
  25 #include "rte_pmd_ixgbe.h"
  26
  27 #define IXGBE_MAX_VFTA     (128)
  28 #define IXGBE_VF_MSG_SIZE_DEFAULT 1
  29 #define IXGBE_VF_GET_QUEUE_MSG_SIZE 5
  30 #define IXGBE_ETHERTYPE_FLOW_CTRL 0x8808
  31
  32 static inline uint16_t
  33 dev_num_vf(struct rte_eth_dev *eth_dev)
  34 {
  35         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
  36
  37         return pci_dev->max_vfs;
  38 }
  39
  40 static inline
  41 int ixgbe_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num)
  42 {
  43         unsigned char vf_mac_addr[RTE_ETHER_ADDR_LEN];
  44         struct ixgbe_vf_info *vfinfo =
  45                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
  46         uint16_t vfn;
  47
  48         for (vfn = 0; vfn < vf_num; vfn++) {
  49                 rte_eth_random_addr(vf_mac_addr);
  50                 /* keep the random address as default */
  51                 memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr,
  52                            RTE_ETHER_ADDR_LEN);
  53         }
  54
  55         return 0;
  56 }
  57
  58 static inline int
  59 ixgbe_mb_intr_setup(struct rte_eth_dev *dev)
  60 {
  61         struct ixgbe_interrupt *intr =
  62                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
  63
  64         intr->mask |= IXGBE_EICR_MAILBOX;
  65
  66         return 0;
  67 }
  68
  69 int ixgbe_pf_host_init(struct rte_eth_dev *eth_dev)
  70 {
  71         struct ixgbe_vf_info **vfinfo =
  72                 IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
  73         struct ixgbe_mirror_info *mirror_info =
  74         IXGBE_DEV_PRIVATE_TO_PFDATA(eth_dev->data->dev_private);
  75         struct ixgbe_uta_info *uta_info =
  76         IXGBE_DEV_PRIVATE_TO_UTA(eth_dev->data->dev_private);
  77         struct ixgbe_hw *hw =
  78                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
  79         uint16_t vf_num;
  80         uint8_t nb_queue;
  81         int ret = 0;
  82
  83         PMD_INIT_FUNC_TRACE();
  84
  85         RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
  86         vf_num = dev_num_vf(eth_dev);
  87         if (vf_num == 0)
  88                 return ret;
  89
  90         *vfinfo = rte_zmalloc("vf_info", sizeof(struct ixgbe_vf_info) * vf_num, 0);
  91         if (*vfinfo == NULL) {
  92                 PMD_INIT_LOG(ERR,
  93                         "Cannot allocate memory for private VF data");
  94                 return -ENOMEM;
  95         }
  96
  97         ret = rte_eth_switch_domain_alloc(&(*vfinfo)->switch_domain_id);
  98         if (ret) {
  99                 PMD_INIT_LOG(ERR,
 100                         "failed to allocate switch domain for device %d", ret);
 101                 rte_free(*vfinfo);
 102                 *vfinfo = NULL;
 103                 return ret;
 104         }
 105
 106         memset(mirror_info, 0, sizeof(struct ixgbe_mirror_info));
 107         memset(uta_info, 0, sizeof(struct ixgbe_uta_info));
 108         hw->mac.mc_filter_type = 0;
 109
 110         if (vf_num >= ETH_32_POOLS) {
 111                 nb_queue = 2;
 112                 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_64_POOLS;
 113         } else if (vf_num >= ETH_16_POOLS) {
 114                 nb_queue = 4;
 115                 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_32_POOLS;
 116         } else {
 117                 nb_queue = 8;
 118                 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_16_POOLS;
 119         }
 120
 121         RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue;
 122         RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num;
 123         RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue);
 124
 125         ixgbe_vf_perm_addr_gen(eth_dev, vf_num);
 126
 127         /* init_mailbox_params */
 128         hw->mbx.ops.init_params(hw);
 129
 130         /* set mb interrupt mask */
 131         ixgbe_mb_intr_setup(eth_dev);
 132
 133         return ret;
 134 }
 135
 136 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev)
 137 {
 138         struct ixgbe_vf_info **vfinfo;
 139         uint16_t vf_num;
 140         int ret;
 141
 142         PMD_INIT_FUNC_TRACE();
 143
 144         RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
 145         RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = 0;
 146         RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = 0;
 147         RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = 0;
 148
 149         vf_num = dev_num_vf(eth_dev);
 150         if (vf_num == 0)
 151                 return;
 152
 153         vfinfo = IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
 154         if (*vfinfo == NULL)
 155                 return;
 156
 157         ret = rte_eth_switch_domain_free((*vfinfo)->switch_domain_id);
 158         if (ret)
 159                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
 160
 161         rte_free(*vfinfo);
 162         *vfinfo = NULL;
 163 }
 164
 165 static void
 166 ixgbe_add_tx_flow_control_drop_filter(struct rte_eth_dev *eth_dev)
 167 {
 168         struct ixgbe_hw *hw =
 169                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 170         struct ixgbe_filter_info *filter_info =
 171                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 172         uint16_t vf_num;
 173         int i;
 174         struct ixgbe_ethertype_filter ethertype_filter;
 175
 176         if (!hw->mac.ops.set_ethertype_anti_spoofing) {
 177                 PMD_DRV_LOG(INFO, "ether type anti-spoofing is not supported.\n");
 178                 return;
 179         }
 180
 181         i = ixgbe_ethertype_filter_lookup(filter_info,
 182                                           IXGBE_ETHERTYPE_FLOW_CTRL);
 183         if (i >= 0) {
 184                 PMD_DRV_LOG(ERR, "A ether type filter entity for flow control already exists!\n");
 185                 return;
 186         }
 187
 188         ethertype_filter.ethertype = IXGBE_ETHERTYPE_FLOW_CTRL;
 189         ethertype_filter.etqf = IXGBE_ETQF_FILTER_EN |
 190                                 IXGBE_ETQF_TX_ANTISPOOF |
 191                                 IXGBE_ETHERTYPE_FLOW_CTRL;
 192         ethertype_filter.etqs = 0;
 193         ethertype_filter.conf = TRUE;
 194         i = ixgbe_ethertype_filter_insert(filter_info,
 195                                           &ethertype_filter);
 196         if (i < 0) {
 197                 PMD_DRV_LOG(ERR, "Cannot find an unused ether type filter entity for flow control.\n");
 198                 return;
 199         }
 200
 201         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
 202                         (IXGBE_ETQF_FILTER_EN |
 203                         IXGBE_ETQF_TX_ANTISPOOF |
 204                         IXGBE_ETHERTYPE_FLOW_CTRL));
 205
 206         vf_num = dev_num_vf(eth_dev);
 207         for (i = 0; i < vf_num; i++)
 208                 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
 209 }
 210
 211 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev)
 212 {
 213         uint32_t vtctl, fcrth;
 214         uint32_t vfre_slot, vfre_offset;
 215         uint16_t vf_num;
 216         const uint8_t VFRE_SHIFT = 5;  /* VFRE 32 bits per slot */
 217         const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
 218         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 219         uint32_t gpie, gcr_ext;
 220         uint32_t vlanctrl;
 221         int i;
 222
 223         vf_num = dev_num_vf(eth_dev);
 224         if (vf_num == 0)
 225                 return -1;
 226
 227         /* enable VMDq and set the default pool for PF */
 228         vtctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 229         vtctl |= IXGBE_VMD_CTL_VMDQ_EN;
 230         vtctl &= ~IXGBE_VT_CTL_POOL_MASK;
 231         vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx
 232                 << IXGBE_VT_CTL_POOL_SHIFT;
 233         vtctl |= IXGBE_VT_CTL_REPLEN;
 234         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl);
 235
 236         vfre_offset = vf_num & VFRE_MASK;
 237         vfre_slot = (vf_num >> VFRE_SHIFT) > 0 ? 1 : 0;
 238
 239         /* Enable pools reserved to PF only */
 240         IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot), (~0U) << vfre_offset);
 241         IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot ^ 1), vfre_slot - 1);
 242         IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot), (~0U) << vfre_offset);
 243         IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot ^ 1), vfre_slot - 1);
 244
 245         /* PFDMA Tx General Switch Control Enables VMDQ loopback */
 246         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
 247
 248         /* clear VMDq map to perment rar 0 */
 249         hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
 250
 251         /* clear VMDq map to scan rar 127 */
 252         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(hw->mac.num_rar_entries), 0);
 253         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(hw->mac.num_rar_entries), 0);
 254
 255         /* set VMDq map to default PF pool */
 256         hw->mac.ops.set_vmdq(hw, 0, RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx);
 257
 258         /*
 259          * SW msut set GCR_EXT.VT_Mode the same as GPIE.VT_Mode
 260          */
 261         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 262         gcr_ext &= ~IXGBE_GCR_EXT_VT_MODE_MASK;
 263
 264         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 265         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 266         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT;
 267
 268         switch (RTE_ETH_DEV_SRIOV(eth_dev).active) {
 269         case ETH_64_POOLS:
 270                 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
 271                 gpie |= IXGBE_GPIE_VTMODE_64;
 272                 break;
 273         case ETH_32_POOLS:
 274                 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_32;
 275                 gpie |= IXGBE_GPIE_VTMODE_32;
 276                 break;
 277         case ETH_16_POOLS:
 278                 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_16;
 279                 gpie |= IXGBE_GPIE_VTMODE_16;
 280                 break;
 281         }
 282
 283         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
 284         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 285
 286         /*
 287          * enable vlan filtering and allow all vlan tags through
 288          */
 289         vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
 290         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
 291         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
 292
 293         /* VFTA - enable all vlan filters */
 294         for (i = 0; i < IXGBE_MAX_VFTA; i++)
 295                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
 296
 297         /* Enable MAC Anti-Spoofing */
 298         hw->mac.ops.set_mac_anti_spoofing(hw, FALSE, vf_num);
 299
 300         /* set flow control threshold to max to avoid tx switch hang */
 301         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 302                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
 303                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
 304                 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
 305         }
 306
 307         ixgbe_add_tx_flow_control_drop_filter(eth_dev);
 308
 309         return 0;
 310 }
 311
 312 static void
 313 set_rx_mode(struct rte_eth_dev *dev)
 314 {
 315         struct rte_eth_dev_data *dev_data = dev->data;
 316         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 317         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
 318         uint16_t vfn = dev_num_vf(dev);
 319
 320         /* Check for Promiscuous and All Multicast modes */
 321         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
 322
 323         /* set all bits that we expect to always be set */
 324         fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
 325         fctrl |= IXGBE_FCTRL_BAM;
 326
 327         /* clear the bits we are changing the status of */
 328         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
 329
 330         if (dev_data->promiscuous) {
 331                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
 332                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
 333         } else {
 334                 if (dev_data->all_multicast) {
 335                         fctrl |= IXGBE_FCTRL_MPE;
 336                         vmolr |= IXGBE_VMOLR_MPE;
 337                 } else {
 338                         vmolr |= IXGBE_VMOLR_ROMPE;
 339                 }
 340         }
 341
 342         if (hw->mac.type != ixgbe_mac_82598EB) {
 343                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(vfn)) &
 344                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
 345                            IXGBE_VMOLR_ROPE);
 346                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vfn), vmolr);
 347         }
 348
 349         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
 350
 351         ixgbe_vlan_hw_strip_config(dev);
 352 }
 353
 354 static inline void
 355 ixgbe_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)
 356 {
 357         struct ixgbe_hw *hw =
 358                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 359         struct ixgbe_vf_info *vfinfo =
 360                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
 361         int rar_entry = hw->mac.num_rar_entries - (vf + 1);
 362         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
 363
 364         vmolr |= (IXGBE_VMOLR_ROPE |
 365                         IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
 366         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
 367
 368         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), 0);
 369
 370         /* reset multicast table array for vf */
 371         vfinfo[vf].num_vf_mc_hashes = 0;
 372
 373         /* reset rx mode */
 374         set_rx_mode(dev);
 375
 376         hw->mac.ops.clear_rar(hw, rar_entry);
 377 }
 378
 379 static inline void
 380 ixgbe_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf)
 381 {
 382         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 383         uint32_t reg;
 384         uint32_t reg_offset, vf_shift;
 385         const uint8_t VFRE_SHIFT = 5;  /* VFRE 32 bits per slot */
 386         const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
 387         uint8_t  nb_q_per_pool;
 388         int i;
 389
 390         vf_shift = vf & VFRE_MASK;
 391         reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0;
 392
 393         /* enable transmit for vf */
 394         reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset));
 395         reg |= (reg | (1 << vf_shift));
 396         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg);
 397
 398         /* enable all queue drop for IOV */
 399         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
 400         for (i = vf * nb_q_per_pool; i < (vf + 1) * nb_q_per_pool; i++) {
 401                 IXGBE_WRITE_FLUSH(hw);
 402                 reg = IXGBE_QDE_ENABLE | IXGBE_QDE_WRITE;
 403                 reg |= i << IXGBE_QDE_IDX_SHIFT;
 404                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg);
 405         }
 406
 407         /* enable receive for vf */
 408         reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));
 409         reg |= (reg | (1 << vf_shift));
 410         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg);
 411
 412         /* Enable counting of spoofed packets in the SSVPC register */
 413         reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset));
 414         reg |= (1 << vf_shift);
 415         IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg);
 416
 417         ixgbe_vf_reset_event(dev, vf);
 418 }
 419
 420 static int
 421 ixgbe_disable_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf)
 422 {
 423         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 424         uint32_t vmolr;
 425
 426         vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
 427
 428         PMD_DRV_LOG(INFO, "VF %u: disabling multicast promiscuous\n", vf);
 429
 430         vmolr &= ~IXGBE_VMOLR_MPE;
 431
 432         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
 433
 434         return 0;
 435 }
 436
 437 static int
 438 ixgbe_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf)
 439 {
 440         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 441         struct ixgbe_vf_info *vfinfo =
 442                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
 443         unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses;
 444         int rar_entry = hw->mac.num_rar_entries - (vf + 1);
 445         uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
 446
 447         ixgbe_vf_reset_msg(dev, vf);
 448
 449         hw->mac.ops.set_rar(hw, rar_entry, vf_mac, vf, IXGBE_RAH_AV);
 450
 451         /* Disable multicast promiscuous at reset */
 452         ixgbe_disable_vf_mc_promisc(dev, vf);
 453
 454         /* reply to reset with ack and vf mac address */
 455         msgbuf[0] = IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK;
 456         rte_memcpy(new_mac, vf_mac, RTE_ETHER_ADDR_LEN);
 457         /*
 458          * Piggyback the multicast filter type so VF can compute the
 459          * correct vectors
 460          */
 461         msgbuf[3] = hw->mac.mc_filter_type;
 462         ixgbe_write_mbx(hw, msgbuf, IXGBE_VF_PERMADDR_MSG_LEN, vf);
 463
 464         return 0;
 465 }
 466
 467 static int
 468 ixgbe_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
 469 {
 470         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 471         struct ixgbe_vf_info *vfinfo =
 472                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
 473         int rar_entry = hw->mac.num_rar_entries - (vf + 1);
 474         uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
 475
 476         if (rte_is_valid_assigned_ether_addr(
 477                         (struct rte_ether_addr *)new_mac)) {
 478                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6);
 479                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf, IXGBE_RAH_AV);
 480         }
 481         return -1;
 482 }
 483
 484 static int
 485 ixgbe_vf_set_multicast(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
 486 {
 487         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 488         struct ixgbe_vf_info *vfinfo =
 489                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
 490         int nb_entries = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >>
 491                 IXGBE_VT_MSGINFO_SHIFT;
 492         uint16_t *hash_list = (uint16_t *)&msgbuf[1];
 493         uint32_t mta_idx;
 494         uint32_t mta_shift;
 495         const uint32_t IXGBE_MTA_INDEX_MASK = 0x7F;
 496         const uint32_t IXGBE_MTA_BIT_SHIFT = 5;
 497         const uint32_t IXGBE_MTA_BIT_MASK = (0x1 << IXGBE_MTA_BIT_SHIFT) - 1;
 498         uint32_t reg_val;
 499         int i;
 500         u32 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
 501
 502         /* Disable multicast promiscuous first */
 503         ixgbe_disable_vf_mc_promisc(dev, vf);
 504
 505         /* only so many hash values supported */
 506         nb_entries = RTE_MIN(nb_entries, IXGBE_MAX_VF_MC_ENTRIES);
 507
 508         /* store the mc entries  */
 509         vfinfo->num_vf_mc_hashes = (uint16_t)nb_entries;
 510         for (i = 0; i < nb_entries; i++) {
 511                 vfinfo->vf_mc_hashes[i] = hash_list[i];
 512         }
 513
 514         if (nb_entries == 0) {
 515                 vmolr &= ~IXGBE_VMOLR_ROMPE;
 516                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
 517                 return 0;
 518         }
 519
 520         for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
 521                 mta_idx = (vfinfo->vf_mc_hashes[i] >> IXGBE_MTA_BIT_SHIFT)
 522                                 & IXGBE_MTA_INDEX_MASK;
 523                 mta_shift = vfinfo->vf_mc_hashes[i] & IXGBE_MTA_BIT_MASK;
 524                 reg_val = IXGBE_READ_REG(hw, IXGBE_MTA(mta_idx));
 525                 reg_val |= (1 << mta_shift);
 526                 IXGBE_WRITE_REG(hw, IXGBE_MTA(mta_idx), reg_val);
 527         }
 528
 529         vmolr |= IXGBE_VMOLR_ROMPE;
 530         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
 531
 532         return 0;
 533 }
 534
 535 static int
 536 ixgbe_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
 537 {
 538         int add, vid;
 539         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 540         struct ixgbe_vf_info *vfinfo =
 541                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
 542
 543         add = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK)
 544                 >> IXGBE_VT_MSGINFO_SHIFT;
 545         vid = (msgbuf[1] & IXGBE_VLVF_VLANID_MASK);
 546
 547         if (add)
 548                 vfinfo[vf].vlan_count++;
 549         else if (vfinfo[vf].vlan_count)
 550                 vfinfo[vf].vlan_count--;
 551         return hw->mac.ops.set_vfta(hw, vid, vf, (bool)add, false);
 552 }
 553
 554 static int
 555 ixgbe_set_vf_lpe(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
 556 {
 557         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 558         uint32_t new_mtu = msgbuf[1];
 559         uint32_t max_frs;
 560         uint32_t hlreg0;
 561         int max_frame = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
 562
 563         /* X540 and X550 support jumbo frames in IOV mode */
 564         if (hw->mac.type != ixgbe_mac_X540 &&
 565                 hw->mac.type != ixgbe_mac_X550 &&
 566                 hw->mac.type != ixgbe_mac_X550EM_x &&
 567                 hw->mac.type != ixgbe_mac_X550EM_a)
 568                 return -1;
 569
 570         if (max_frame < RTE_ETHER_MIN_LEN ||
 571                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
 572                 return -1;
 573
 574         max_frs = (IXGBE_READ_REG(hw, IXGBE_MAXFRS) &
 575                    IXGBE_MHADD_MFS_MASK) >> IXGBE_MHADD_MFS_SHIFT;
 576         if (max_frs < new_mtu) {
 577                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
 578                 if (new_mtu > RTE_ETHER_MAX_LEN) {
 579                         dev->data->dev_conf.rxmode.offloads |=
 580                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 581                         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
 582                 } else {
 583                         dev->data->dev_conf.rxmode.offloads &=
 584                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 585                         hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
 586                 }
 587                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
 588
 589                 max_frs = new_mtu << IXGBE_MHADD_MFS_SHIFT;
 590                 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, max_frs);
 591         }
 592
 593         return 0;
 594 }
 595
 596 static int
 597 ixgbe_negotiate_vf_api(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
 598 {
 599         uint32_t api_version = msgbuf[1];
 600         struct ixgbe_vf_info *vfinfo =
 601                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
 602
 603         switch (api_version) {
 604         case ixgbe_mbox_api_10:
 605         case ixgbe_mbox_api_11:
 606         case ixgbe_mbox_api_12:
 607         case ixgbe_mbox_api_13:
 608                 vfinfo[vf].api_version = (uint8_t)api_version;
 609                 return 0;
 610         default:
 611                 break;
 612         }
 613
 614         PMD_DRV_LOG(ERR, "Negotiate invalid api version %u from VF %d\n",
 615                 api_version, vf);
 616
 617         return -1;
 618 }
 619
 620 static int
 621 ixgbe_get_vf_queues(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
 622 {
 623         struct ixgbe_vf_info *vfinfo =
 624                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
 625         uint32_t default_q = vf * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
 626         struct rte_eth_conf *eth_conf;
 627         struct rte_eth_vmdq_dcb_tx_conf *vmdq_dcb_tx_conf;
 628         u8 num_tcs;
 629         struct ixgbe_hw *hw;
 630         u32 vmvir;
 631 #define IXGBE_VMVIR_VLANA_MASK          0xC0000000
 632 #define IXGBE_VMVIR_VLAN_VID_MASK       0x00000FFF
 633 #define IXGBE_VMVIR_VLAN_UP_MASK        0x0000E000
 634 #define VLAN_PRIO_SHIFT                 13
 635         u32 vlana;
 636         u32 vid;
 637         u32 user_priority;
 638
 639         /* Verify if the PF supports the mbox APIs version or not */
 640         switch (vfinfo[vf].api_version) {
 641         case ixgbe_mbox_api_20:
 642         case ixgbe_mbox_api_11:
 643         case ixgbe_mbox_api_12:
 644         case ixgbe_mbox_api_13:
 645                 break;
 646         default:
 647                 return -1;
 648         }
 649
 650         /* Notify VF of Rx and Tx queue number */
 651         msgbuf[IXGBE_VF_RX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
 652         msgbuf[IXGBE_VF_TX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
 653
 654         /* Notify VF of default queue */
 655         msgbuf[IXGBE_VF_DEF_QUEUE] = default_q;
 656
 657         /* Notify VF of number of DCB traffic classes */
 658         eth_conf = &dev->data->dev_conf;
 659         switch (eth_conf->txmode.mq_mode) {
 660         case ETH_MQ_TX_NONE:
 661         case ETH_MQ_TX_DCB:
 662                 PMD_DRV_LOG(ERR, "PF must work with virtualization for VF %u"
 663                         ", but its tx mode = %d\n", vf,
 664                         eth_conf->txmode.mq_mode);
 665                 return -1;
 666
 667         case ETH_MQ_TX_VMDQ_DCB:
 668                 vmdq_dcb_tx_conf = &eth_conf->tx_adv_conf.vmdq_dcb_tx_conf;
 669                 switch (vmdq_dcb_tx_conf->nb_queue_pools) {
 670                 case ETH_16_POOLS:
 671                         num_tcs = ETH_8_TCS;
 672                         break;
 673                 case ETH_32_POOLS:
 674                         num_tcs = ETH_4_TCS;
 675                         break;
 676                 default:
 677                         return -1;
 678                 }
 679                 break;
 680
 681         /* ETH_MQ_TX_VMDQ_ONLY,  DCB not enabled */
 682         case ETH_MQ_TX_VMDQ_ONLY:
 683                 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 684                 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
 685                 vlana = vmvir & IXGBE_VMVIR_VLANA_MASK;
 686                 vid = vmvir & IXGBE_VMVIR_VLAN_VID_MASK;
 687                 user_priority =
 688                         (vmvir & IXGBE_VMVIR_VLAN_UP_MASK) >> VLAN_PRIO_SHIFT;
 689                 if ((vlana == IXGBE_VMVIR_VLANA_DEFAULT) &&
 690                         ((vid !=  0) || (user_priority != 0)))
 691                         num_tcs = 1;
 692                 else
 693                         num_tcs = 0;
 694                 break;
 695
 696         default:
 697                 PMD_DRV_LOG(ERR, "PF work with invalid mode = %d\n",
 698                         eth_conf->txmode.mq_mode);
 699                 return -1;
 700         }
 701         msgbuf[IXGBE_VF_TRANS_VLAN] = num_tcs;
 702
 703         return 0;
 704 }
 705
 706 static int
 707 ixgbe_set_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
 708 {
 709         struct ixgbe_vf_info *vfinfo =
 710                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
 711         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 712         int xcast_mode = msgbuf[1];     /* msgbuf contains the flag to enable */
 713         u32 vmolr, fctrl, disable, enable;
 714
 715         switch (vfinfo[vf].api_version) {
 716         case ixgbe_mbox_api_12:
 717                 /* promisc introduced in 1.3 version */
 718                 if (xcast_mode == IXGBEVF_XCAST_MODE_PROMISC)
 719                         return -EOPNOTSUPP;
 720                 break;
 721                 /* Fall threw */
 722         case ixgbe_mbox_api_13:
 723                 break;
 724         default:
 725                 return -1;
 726         }
 727
 728         if (vfinfo[vf].xcast_mode == xcast_mode)
 729                 goto out;
 730
 731         switch (xcast_mode) {
 732         case IXGBEVF_XCAST_MODE_NONE:
 733                 disable = IXGBE_VMOLR_BAM | IXGBE_VMOLR_ROMPE |
 734                           IXGBE_VMOLR_MPE | IXGBE_VMOLR_UPE | IXGBE_VMOLR_VPE;
 735                 enable = 0;
 736                 break;
 737         case IXGBEVF_XCAST_MODE_MULTI:
 738                 disable = IXGBE_VMOLR_MPE | IXGBE_VMOLR_UPE | IXGBE_VMOLR_VPE;
 739                 enable = IXGBE_VMOLR_BAM | IXGBE_VMOLR_ROMPE;
 740                 break;
 741         case IXGBEVF_XCAST_MODE_ALLMULTI:
 742                 disable = IXGBE_VMOLR_UPE | IXGBE_VMOLR_VPE;
 743                 enable = IXGBE_VMOLR_BAM | IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_MPE;
 744                 break;
 745         case IXGBEVF_XCAST_MODE_PROMISC:
 746                 if (hw->mac.type <= ixgbe_mac_82599EB)
 747                         return -1;
 748
 749                 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
 750                 if (!(fctrl & IXGBE_FCTRL_UPE)) {
 751                         /* VF promisc requires PF in promisc */
 752                         PMD_DRV_LOG(ERR,
 753                                "Enabling VF promisc requires PF in promisc\n");
 754                         return -1;
 755                 }
 756
 757                 disable = 0;
 758                 enable = IXGBE_VMOLR_BAM | IXGBE_VMOLR_ROMPE |
 759                          IXGBE_VMOLR_MPE | IXGBE_VMOLR_UPE | IXGBE_VMOLR_VPE;
 760                 break;
 761         default:
 762                 return -1;
 763         }
 764
 765         vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
 766         vmolr &= ~disable;
 767         vmolr |= enable;
 768         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
 769         vfinfo[vf].xcast_mode = xcast_mode;
 770
 771 out:
 772         msgbuf[1] = xcast_mode;
 773
 774         return 0;
 775 }
 776
 777 static int
 778 ixgbe_set_vf_macvlan_msg(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
 779 {
 780         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 781         struct ixgbe_vf_info *vf_info =
 782                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
 783         uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
 784         int index = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >>
 785                     IXGBE_VT_MSGINFO_SHIFT;
 786
 787         if (index) {
 788                 if (!rte_is_valid_assigned_ether_addr(
 789                         (struct rte_ether_addr *)new_mac)) {
 790                         PMD_DRV_LOG(ERR, "set invalid mac vf:%d\n", vf);
 791                         return -1;
 792                 }
 793
 794                 vf_info[vf].mac_count++;
 795
 796                 hw->mac.ops.set_rar(hw, vf_info[vf].mac_count,
 797                                 new_mac, vf, IXGBE_RAH_AV);
 798         } else {
 799                 if (vf_info[vf].mac_count) {
 800                         hw->mac.ops.clear_rar(hw, vf_info[vf].mac_count);
 801                         vf_info[vf].mac_count = 0;
 802                 }
 803         }
 804         return 0;
 805 }
 806
 807 static int
 808 ixgbe_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf)
 809 {
 810         uint16_t mbx_size = IXGBE_VFMAILBOX_SIZE;
 811         uint16_t msg_size = IXGBE_VF_MSG_SIZE_DEFAULT;
 812         uint32_t msgbuf[IXGBE_VFMAILBOX_SIZE];
 813         int32_t retval;
 814         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 815         struct ixgbe_vf_info *vfinfo =
 816                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
 817         struct rte_pmd_ixgbe_mb_event_param ret_param;
 818
 819         retval = ixgbe_read_mbx(hw, msgbuf, mbx_size, vf);
 820         if (retval) {
 821                 PMD_DRV_LOG(ERR, "Error mbx recv msg from VF %d", vf);
 822                 return retval;
 823         }
 824
 825         /* do nothing with the message already been processed */
 826         if (msgbuf[0] & (IXGBE_VT_MSGTYPE_ACK | IXGBE_VT_MSGTYPE_NACK))
 827                 return retval;
 828
 829         /* flush the ack before we write any messages back */
 830         IXGBE_WRITE_FLUSH(hw);
 831
 832         /**
 833          * initialise structure to send to user application
 834          * will return response from user in retval field
 835          */
 836         ret_param.retval = RTE_PMD_IXGBE_MB_EVENT_PROCEED;
 837         ret_param.vfid = vf;
 838         ret_param.msg_type = msgbuf[0] & 0xFFFF;
 839         ret_param.msg = (void *)msgbuf;
 840
 841         /* perform VF reset */
 842         if (msgbuf[0] == IXGBE_VF_RESET) {
 843                 int ret = ixgbe_vf_reset(dev, vf, msgbuf);
 844
 845                 vfinfo[vf].clear_to_send = true;
 846
 847                 /* notify application about VF reset */
 848                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX,
 849                                               &ret_param);
 850                 return ret;
 851         }
 852
 853         /**
 854          * ask user application if we allowed to perform those functions
 855          * if we get ret_param.retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED
 856          * then business as usual,
 857          * if 0, do nothing and send ACK to VF
 858          * if ret_param.retval > 1, do nothing and send NAK to VF
 859          */
 860         rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX, &ret_param);
 861
 862         retval = ret_param.retval;
 863
 864         /* check & process VF to PF mailbox message */
 865         switch ((msgbuf[0] & 0xFFFF)) {
 866         case IXGBE_VF_SET_MAC_ADDR:
 867                 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
 868                         retval = ixgbe_vf_set_mac_addr(dev, vf, msgbuf);
 869                 break;
 870         case IXGBE_VF_SET_MULTICAST:
 871                 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
 872                         retval = ixgbe_vf_set_multicast(dev, vf, msgbuf);
 873                 break;
 874         case IXGBE_VF_SET_LPE:
 875                 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
 876                         retval = ixgbe_set_vf_lpe(dev, vf, msgbuf);
 877                 break;
 878         case IXGBE_VF_SET_VLAN:
 879                 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
 880                         retval = ixgbe_vf_set_vlan(dev, vf, msgbuf);
 881                 break;
 882         case IXGBE_VF_API_NEGOTIATE:
 883                 retval = ixgbe_negotiate_vf_api(dev, vf, msgbuf);
 884                 break;
 885         case IXGBE_VF_GET_QUEUES:
 886                 retval = ixgbe_get_vf_queues(dev, vf, msgbuf);
 887                 msg_size = IXGBE_VF_GET_QUEUE_MSG_SIZE;
 888                 break;
 889         case IXGBE_VF_UPDATE_XCAST_MODE:
 890                 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
 891                         retval = ixgbe_set_vf_mc_promisc(dev, vf, msgbuf);
 892                 break;
 893         case IXGBE_VF_SET_MACVLAN:
 894                 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
 895                         retval = ixgbe_set_vf_macvlan_msg(dev, vf, msgbuf);
 896                 break;
 897         default:
 898                 PMD_DRV_LOG(DEBUG, "Unhandled Msg %8.8x", (unsigned)msgbuf[0]);
 899                 retval = IXGBE_ERR_MBX;
 900                 break;
 901         }
 902
 903         /* response the VF according to the message process result */
 904         if (retval)
 905                 msgbuf[0] |= IXGBE_VT_MSGTYPE_NACK;
 906         else
 907                 msgbuf[0] |= IXGBE_VT_MSGTYPE_ACK;
 908
 909         msgbuf[0] |= IXGBE_VT_MSGTYPE_CTS;
 910
 911         ixgbe_write_mbx(hw, msgbuf, msg_size, vf);
 912
 913         return retval;
 914 }
 915
 916 static inline void
 917 ixgbe_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf)
 918 {
 919         uint32_t msg = IXGBE_VT_MSGTYPE_NACK;
 920         struct ixgbe_hw *hw =
 921                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 922         struct ixgbe_vf_info *vfinfo =
 923                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
 924
 925         if (!vfinfo[vf].clear_to_send)
 926                 ixgbe_write_mbx(hw, &msg, 1, vf);
 927 }
 928
 929 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev)
 930 {
 931         uint16_t vf;
 932         struct ixgbe_hw *hw =
 933                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 934
 935         for (vf = 0; vf < dev_num_vf(eth_dev); vf++) {
 936                 /* check & process vf function level reset */
 937                 if (!ixgbe_check_for_rst(hw, vf))
 938                         ixgbe_vf_reset_event(eth_dev, vf);
 939
 940                 /* check & process vf mailbox messages */
 941                 if (!ixgbe_check_for_msg(hw, vf))
 942                         ixgbe_rcv_msg_from_vf(eth_dev, vf);
 943
 944                 /* check & process acks from vf */
 945                 if (!ixgbe_check_for_ack(hw, vf))
 946                         ixgbe_rcv_ack_from_vf(eth_dev, vf);
 947         }
 948 }