4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5 * Copyright 2014 6WIND S.A.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
18 * * Neither the name of Intel Corporation nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/queue.h>
46 #include <rte_byteorder.h>
47 #include <rte_common.h>
48 #include <rte_cycles.h>
50 #include <rte_debug.h>
51 #include <rte_interrupts.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_launch.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
75 #include "ixgbe_logs.h"
76 #include "base/ixgbe_api.h"
77 #include "base/ixgbe_vf.h"
78 #include "ixgbe_ethdev.h"
79 #include "base/ixgbe_dcb.h"
80 #include "base/ixgbe_common.h"
81 #include "ixgbe_rxtx.h"
83 /* Bit Mask to indicate what bits required for building TX context */
84 #define IXGBE_TX_OFFLOAD_MASK ( \
90 static inline struct rte_mbuf *
91 rte_rxmbuf_alloc(struct rte_mempool *mp)
95 m = __rte_mbuf_raw_alloc(mp);
96 __rte_mbuf_sanity_check_raw(m, 0);
102 #define RTE_PMD_USE_PREFETCH
105 #ifdef RTE_PMD_USE_PREFETCH
107 * Prefetch a cache line into all cache levels.
109 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
111 #define rte_ixgbe_prefetch(p) do {} while(0)
114 /*********************************************************************
118 **********************************************************************/
121 * Check for descriptors with their DD bit set and free mbufs.
122 * Return the total number of buffers freed.
124 static inline int __attribute__((always_inline))
125 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
127 struct ixgbe_tx_entry *txep;
131 /* check DD bit on threshold descriptor */
132 status = txq->tx_ring[txq->tx_next_dd].wb.status;
133 if (!(status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD)))
137 * first buffer to free from S/W ring is at index
138 * tx_next_dd - (tx_rs_thresh-1)
140 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
142 /* free buffers one at a time */
143 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
144 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
145 txep->mbuf->next = NULL;
146 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
150 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
151 rte_pktmbuf_free_seg(txep->mbuf);
156 /* buffers were freed, update counters */
157 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
158 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
159 if (txq->tx_next_dd >= txq->nb_tx_desc)
160 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
162 return txq->tx_rs_thresh;
165 /* Populate 4 descriptors with data from 4 mbufs */
167 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
169 uint64_t buf_dma_addr;
173 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
174 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
175 pkt_len = (*pkts)->data_len;
177 /* write data to descriptor */
178 txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
180 txdp->read.cmd_type_len =
181 rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
183 txdp->read.olinfo_status =
184 rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
186 rte_prefetch0(&(*pkts)->pool);
190 /* Populate 1 descriptor with data from 1 mbuf */
192 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
194 uint64_t buf_dma_addr;
197 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
198 pkt_len = (*pkts)->data_len;
200 /* write data to descriptor */
201 txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
202 txdp->read.cmd_type_len =
203 rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
204 txdp->read.olinfo_status =
205 rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
206 rte_prefetch0(&(*pkts)->pool);
210 * Fill H/W descriptor ring with mbuf data.
211 * Copy mbuf pointers to the S/W ring.
214 ixgbe_tx_fill_hw_ring(struct ixgbe_tx_queue *txq, struct rte_mbuf **pkts,
217 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
218 struct ixgbe_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
219 const int N_PER_LOOP = 4;
220 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
221 int mainpart, leftover;
225 * Process most of the packets in chunks of N pkts. Any
226 * leftover packets will get processed one at a time.
228 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
229 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
230 for (i = 0; i < mainpart; i += N_PER_LOOP) {
231 /* Copy N mbuf pointers to the S/W ring */
232 for (j = 0; j < N_PER_LOOP; ++j) {
233 (txep + i + j)->mbuf = *(pkts + i + j);
235 tx4(txdp + i, pkts + i);
238 if (unlikely(leftover > 0)) {
239 for (i = 0; i < leftover; ++i) {
240 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
241 tx1(txdp + mainpart + i, pkts + mainpart + i);
246 static inline uint16_t
247 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
250 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
251 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
255 * Begin scanning the H/W ring for done descriptors when the
256 * number of available descriptors drops below tx_free_thresh. For
257 * each done descriptor, free the associated buffer.
259 if (txq->nb_tx_free < txq->tx_free_thresh)
260 ixgbe_tx_free_bufs(txq);
262 /* Only use descriptors that are available */
263 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
264 if (unlikely(nb_pkts == 0))
267 /* Use exactly nb_pkts descriptors */
268 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
271 * At this point, we know there are enough descriptors in the
272 * ring to transmit all the packets. This assumes that each
273 * mbuf contains a single segment, and that no new offloads
274 * are expected, which would require a new context descriptor.
278 * See if we're going to wrap-around. If so, handle the top
279 * of the descriptor ring first, then do the bottom. If not,
280 * the processing looks just like the "bottom" part anyway...
282 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
283 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
284 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
287 * We know that the last descriptor in the ring will need to
288 * have its RS bit set because tx_rs_thresh has to be
289 * a divisor of the ring size
291 tx_r[txq->tx_next_rs].read.cmd_type_len |=
292 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
293 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
298 /* Fill H/W descriptor ring with mbuf data */
299 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
300 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
303 * Determine if RS bit should be set
304 * This is what we actually want:
305 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
306 * but instead of subtracting 1 and doing >=, we can just do
307 * greater than without subtracting.
309 if (txq->tx_tail > txq->tx_next_rs) {
310 tx_r[txq->tx_next_rs].read.cmd_type_len |=
311 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
312 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
314 if (txq->tx_next_rs >= txq->nb_tx_desc)
315 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
319 * Check for wrap-around. This would only happen if we used
320 * up to the last descriptor in the ring, no more, no less.
322 if (txq->tx_tail >= txq->nb_tx_desc)
325 /* update tail pointer */
327 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
333 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
338 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
339 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
340 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
342 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
346 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
347 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
348 nb_tx = (uint16_t)(nb_tx + ret);
349 nb_pkts = (uint16_t)(nb_pkts - ret);
358 ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,
359 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
360 uint64_t ol_flags, union ixgbe_tx_offload tx_offload)
362 uint32_t type_tucmd_mlhl;
363 uint32_t mss_l4len_idx = 0;
365 uint32_t vlan_macip_lens;
366 union ixgbe_tx_offload tx_offload_mask;
368 ctx_idx = txq->ctx_curr;
369 tx_offload_mask.data = 0;
372 /* Specify which HW CTX to upload. */
373 mss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
375 if (ol_flags & PKT_TX_VLAN_PKT) {
376 tx_offload_mask.vlan_tci |= ~0;
379 /* check if TCP segmentation required for this packet */
380 if (ol_flags & PKT_TX_TCP_SEG) {
381 /* implies IP cksum in IPv4 */
382 if (ol_flags & PKT_TX_IP_CKSUM)
383 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |
384 IXGBE_ADVTXD_TUCMD_L4T_TCP |
385 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
387 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV6 |
388 IXGBE_ADVTXD_TUCMD_L4T_TCP |
389 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
391 tx_offload_mask.l2_len |= ~0;
392 tx_offload_mask.l3_len |= ~0;
393 tx_offload_mask.l4_len |= ~0;
394 tx_offload_mask.tso_segsz |= ~0;
395 mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
396 mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;
397 } else { /* no TSO, check if hardware checksum is needed */
398 if (ol_flags & PKT_TX_IP_CKSUM) {
399 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
400 tx_offload_mask.l2_len |= ~0;
401 tx_offload_mask.l3_len |= ~0;
404 switch (ol_flags & PKT_TX_L4_MASK) {
405 case PKT_TX_UDP_CKSUM:
406 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
407 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
408 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
409 tx_offload_mask.l2_len |= ~0;
410 tx_offload_mask.l3_len |= ~0;
412 case PKT_TX_TCP_CKSUM:
413 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
414 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
415 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
416 tx_offload_mask.l2_len |= ~0;
417 tx_offload_mask.l3_len |= ~0;
418 tx_offload_mask.l4_len |= ~0;
420 case PKT_TX_SCTP_CKSUM:
421 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
422 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
423 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
424 tx_offload_mask.l2_len |= ~0;
425 tx_offload_mask.l3_len |= ~0;
428 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
429 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
434 txq->ctx_cache[ctx_idx].flags = ol_flags;
435 txq->ctx_cache[ctx_idx].tx_offload.data =
436 tx_offload_mask.data & tx_offload.data;
437 txq->ctx_cache[ctx_idx].tx_offload_mask = tx_offload_mask;
439 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
440 vlan_macip_lens = tx_offload.l3_len;
441 vlan_macip_lens |= (tx_offload.l2_len << IXGBE_ADVTXD_MACLEN_SHIFT);
442 vlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);
443 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
444 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
445 ctx_txd->seqnum_seed = 0;
449 * Check which hardware context can be used. Use the existing match
450 * or create a new context descriptor.
452 static inline uint32_t
453 what_advctx_update(struct ixgbe_tx_queue *txq, uint64_t flags,
454 union ixgbe_tx_offload tx_offload)
456 /* If match with the current used context */
457 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
458 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
459 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
460 return txq->ctx_curr;
463 /* What if match with the next context */
465 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
466 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
467 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
468 return txq->ctx_curr;
471 /* Mismatch, use the previous context */
472 return (IXGBE_CTX_NUM);
475 static inline uint32_t
476 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
479 if ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM)
480 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
481 if (ol_flags & PKT_TX_IP_CKSUM)
482 tmp |= IXGBE_ADVTXD_POPTS_IXSM;
483 if (ol_flags & PKT_TX_TCP_SEG)
484 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
488 static inline uint32_t
489 tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)
491 uint32_t cmdtype = 0;
492 if (ol_flags & PKT_TX_VLAN_PKT)
493 cmdtype |= IXGBE_ADVTXD_DCMD_VLE;
494 if (ol_flags & PKT_TX_TCP_SEG)
495 cmdtype |= IXGBE_ADVTXD_DCMD_TSE;
499 /* Default RS bit threshold values */
500 #ifndef DEFAULT_TX_RS_THRESH
501 #define DEFAULT_TX_RS_THRESH 32
503 #ifndef DEFAULT_TX_FREE_THRESH
504 #define DEFAULT_TX_FREE_THRESH 32
507 /* Reset transmit descriptors after they have been used */
509 ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)
511 struct ixgbe_tx_entry *sw_ring = txq->sw_ring;
512 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
513 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
514 uint16_t nb_tx_desc = txq->nb_tx_desc;
515 uint16_t desc_to_clean_to;
516 uint16_t nb_tx_to_clean;
519 /* Determine the last descriptor needing to be cleaned */
520 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
521 if (desc_to_clean_to >= nb_tx_desc)
522 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
524 /* Check to make sure the last descriptor to clean is done */
525 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
526 status = txr[desc_to_clean_to].wb.status;
527 if (!(status & rte_cpu_to_le_32(IXGBE_TXD_STAT_DD)))
529 PMD_TX_FREE_LOG(DEBUG,
530 "TX descriptor %4u is not done"
531 "(port=%d queue=%d)",
533 txq->port_id, txq->queue_id);
534 /* Failed to clean any descriptors, better luck next time */
538 /* Figure out how many descriptors will be cleaned */
539 if (last_desc_cleaned > desc_to_clean_to)
540 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
543 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
546 PMD_TX_FREE_LOG(DEBUG,
547 "Cleaning %4u TX descriptors: %4u to %4u "
548 "(port=%d queue=%d)",
549 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
550 txq->port_id, txq->queue_id);
553 * The last descriptor to clean is done, so that means all the
554 * descriptors from the last descriptor that was cleaned
555 * up to the last descriptor with the RS bit set
556 * are done. Only reset the threshold descriptor.
558 txr[desc_to_clean_to].wb.status = 0;
560 /* Update the txq to reflect the last descriptor that was cleaned */
561 txq->last_desc_cleaned = desc_to_clean_to;
562 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
569 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
572 struct ixgbe_tx_queue *txq;
573 struct ixgbe_tx_entry *sw_ring;
574 struct ixgbe_tx_entry *txe, *txn;
575 volatile union ixgbe_adv_tx_desc *txr;
576 volatile union ixgbe_adv_tx_desc *txd;
577 struct rte_mbuf *tx_pkt;
578 struct rte_mbuf *m_seg;
579 uint64_t buf_dma_addr;
580 uint32_t olinfo_status;
581 uint32_t cmd_type_len;
592 union ixgbe_tx_offload tx_offload = {0};
595 sw_ring = txq->sw_ring;
597 tx_id = txq->tx_tail;
598 txe = &sw_ring[tx_id];
600 /* Determine if the descriptor ring needs to be cleaned. */
601 if (txq->nb_tx_free < txq->tx_free_thresh)
602 ixgbe_xmit_cleanup(txq);
604 rte_prefetch0(&txe->mbuf->pool);
607 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
610 pkt_len = tx_pkt->pkt_len;
613 * Determine how many (if any) context descriptors
614 * are needed for offload functionality.
616 ol_flags = tx_pkt->ol_flags;
618 /* If hardware offload required */
619 tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
621 tx_offload.l2_len = tx_pkt->l2_len;
622 tx_offload.l3_len = tx_pkt->l3_len;
623 tx_offload.l4_len = tx_pkt->l4_len;
624 tx_offload.vlan_tci = tx_pkt->vlan_tci;
625 tx_offload.tso_segsz = tx_pkt->tso_segsz;
627 /* If new context need be built or reuse the exist ctx. */
628 ctx = what_advctx_update(txq, tx_ol_req,
630 /* Only allocate context descriptor if required*/
631 new_ctx = (ctx == IXGBE_CTX_NUM);
636 * Keep track of how many descriptors are used this loop
637 * This will always be the number of segments + the number of
638 * Context descriptors required to transmit the packet
640 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
643 * The number of descriptors that must be allocated for a
644 * packet is the number of segments of that packet, plus 1
645 * Context Descriptor for the hardware offload, if any.
646 * Determine the last TX descriptor to allocate in the TX ring
647 * for the packet, starting from the current position (tx_id)
650 tx_last = (uint16_t) (tx_id + nb_used - 1);
653 if (tx_last >= txq->nb_tx_desc)
654 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
656 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
657 " tx_first=%u tx_last=%u",
658 (unsigned) txq->port_id,
659 (unsigned) txq->queue_id,
665 * Make sure there are enough TX descriptors available to
666 * transmit the entire packet.
667 * nb_used better be less than or equal to txq->tx_rs_thresh
669 if (nb_used > txq->nb_tx_free) {
670 PMD_TX_FREE_LOG(DEBUG,
671 "Not enough free TX descriptors "
672 "nb_used=%4u nb_free=%4u "
673 "(port=%d queue=%d)",
674 nb_used, txq->nb_tx_free,
675 txq->port_id, txq->queue_id);
677 if (ixgbe_xmit_cleanup(txq) != 0) {
678 /* Could not clean any descriptors */
684 /* nb_used better be <= txq->tx_rs_thresh */
685 if (unlikely(nb_used > txq->tx_rs_thresh)) {
686 PMD_TX_FREE_LOG(DEBUG,
687 "The number of descriptors needed to "
688 "transmit the packet exceeds the "
689 "RS bit threshold. This will impact "
691 "nb_used=%4u nb_free=%4u "
693 "(port=%d queue=%d)",
694 nb_used, txq->nb_tx_free,
696 txq->port_id, txq->queue_id);
698 * Loop here until there are enough TX
699 * descriptors or until the ring cannot be
702 while (nb_used > txq->nb_tx_free) {
703 if (ixgbe_xmit_cleanup(txq) != 0) {
705 * Could not clean any
717 * By now there are enough free TX descriptors to transmit
722 * Set common flags of all TX Data Descriptors.
724 * The following bits must be set in all Data Descriptors:
725 * - IXGBE_ADVTXD_DTYP_DATA
726 * - IXGBE_ADVTXD_DCMD_DEXT
728 * The following bits must be set in the first Data Descriptor
729 * and are ignored in the other ones:
730 * - IXGBE_ADVTXD_DCMD_IFCS
731 * - IXGBE_ADVTXD_MAC_1588
732 * - IXGBE_ADVTXD_DCMD_VLE
734 * The following bits must only be set in the last Data
736 * - IXGBE_TXD_CMD_EOP
738 * The following bits can be set in any Data Descriptor, but
739 * are only set in the last Data Descriptor:
742 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
743 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
745 #ifdef RTE_LIBRTE_IEEE1588
746 if (ol_flags & PKT_TX_IEEE1588_TMST)
747 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
753 if (ol_flags & PKT_TX_TCP_SEG) {
754 /* when TSO is on, paylen in descriptor is the
755 * not the packet len but the tcp payload len */
756 pkt_len -= (tx_offload.l2_len +
757 tx_offload.l3_len + tx_offload.l4_len);
761 * Setup the TX Advanced Context Descriptor if required
764 volatile struct ixgbe_adv_tx_context_desc *
767 ctx_txd = (volatile struct
768 ixgbe_adv_tx_context_desc *)
771 txn = &sw_ring[txe->next_id];
772 rte_prefetch0(&txn->mbuf->pool);
774 if (txe->mbuf != NULL) {
775 rte_pktmbuf_free_seg(txe->mbuf);
779 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
782 txe->last_id = tx_last;
783 tx_id = txe->next_id;
788 * Setup the TX Advanced Data Descriptor,
789 * This path will go through
790 * whatever new/reuse the context descriptor
792 cmd_type_len |= tx_desc_ol_flags_to_cmdtype(ol_flags);
793 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
794 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
797 olinfo_status |= (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
802 txn = &sw_ring[txe->next_id];
803 rte_prefetch0(&txn->mbuf->pool);
805 if (txe->mbuf != NULL)
806 rte_pktmbuf_free_seg(txe->mbuf);
810 * Set up Transmit Data Descriptor.
812 slen = m_seg->data_len;
813 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
814 txd->read.buffer_addr =
815 rte_cpu_to_le_64(buf_dma_addr);
816 txd->read.cmd_type_len =
817 rte_cpu_to_le_32(cmd_type_len | slen);
818 txd->read.olinfo_status =
819 rte_cpu_to_le_32(olinfo_status);
820 txe->last_id = tx_last;
821 tx_id = txe->next_id;
824 } while (m_seg != NULL);
827 * The last packet data descriptor needs End Of Packet (EOP)
829 cmd_type_len |= IXGBE_TXD_CMD_EOP;
830 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
831 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
833 /* Set RS bit only on threshold packets' last descriptor */
834 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
835 PMD_TX_FREE_LOG(DEBUG,
836 "Setting RS bit on TXD id="
837 "%4u (port=%d queue=%d)",
838 tx_last, txq->port_id, txq->queue_id);
840 cmd_type_len |= IXGBE_TXD_CMD_RS;
842 /* Update txq RS bit counters */
845 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
851 * Set the Transmit Descriptor Tail (TDT)
853 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
854 (unsigned) txq->port_id, (unsigned) txq->queue_id,
855 (unsigned) tx_id, (unsigned) nb_tx);
856 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
857 txq->tx_tail = tx_id;
862 /*********************************************************************
866 **********************************************************************/
868 #define IXGBE_PACKET_TYPE_IPV4 0X01
869 #define IXGBE_PACKET_TYPE_IPV4_TCP 0X11
870 #define IXGBE_PACKET_TYPE_IPV4_UDP 0X21
871 #define IXGBE_PACKET_TYPE_IPV4_SCTP 0X41
872 #define IXGBE_PACKET_TYPE_IPV4_EXT 0X03
873 #define IXGBE_PACKET_TYPE_IPV4_EXT_SCTP 0X43
874 #define IXGBE_PACKET_TYPE_IPV6 0X04
875 #define IXGBE_PACKET_TYPE_IPV6_TCP 0X14
876 #define IXGBE_PACKET_TYPE_IPV6_UDP 0X24
877 #define IXGBE_PACKET_TYPE_IPV6_EXT 0X0C
878 #define IXGBE_PACKET_TYPE_IPV6_EXT_TCP 0X1C
879 #define IXGBE_PACKET_TYPE_IPV6_EXT_UDP 0X2C
880 #define IXGBE_PACKET_TYPE_IPV4_IPV6 0X05
881 #define IXGBE_PACKET_TYPE_IPV4_IPV6_TCP 0X15
882 #define IXGBE_PACKET_TYPE_IPV4_IPV6_UDP 0X25
883 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT 0X0D
884 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP 0X1D
885 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP 0X2D
886 #define IXGBE_PACKET_TYPE_MAX 0X80
887 #define IXGBE_PACKET_TYPE_MASK 0X7F
888 #define IXGBE_PACKET_TYPE_SHIFT 0X04
889 static inline uint32_t
890 ixgbe_rxd_pkt_info_to_pkt_type(uint16_t pkt_info)
892 static const uint32_t
893 ptype_table[IXGBE_PACKET_TYPE_MAX] __rte_cache_aligned = {
894 [IXGBE_PACKET_TYPE_IPV4] = RTE_PTYPE_L2_ETHER |
896 [IXGBE_PACKET_TYPE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
897 RTE_PTYPE_L3_IPV4_EXT,
898 [IXGBE_PACKET_TYPE_IPV6] = RTE_PTYPE_L2_ETHER |
900 [IXGBE_PACKET_TYPE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
901 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
902 RTE_PTYPE_INNER_L3_IPV6,
903 [IXGBE_PACKET_TYPE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
904 RTE_PTYPE_L3_IPV6_EXT,
905 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
906 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
907 RTE_PTYPE_INNER_L3_IPV6_EXT,
908 [IXGBE_PACKET_TYPE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
909 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
910 [IXGBE_PACKET_TYPE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
911 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
912 [IXGBE_PACKET_TYPE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
913 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
914 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
915 [IXGBE_PACKET_TYPE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
916 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,
917 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
918 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
919 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
920 [IXGBE_PACKET_TYPE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
921 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
922 [IXGBE_PACKET_TYPE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
923 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
924 [IXGBE_PACKET_TYPE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
925 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
926 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
927 [IXGBE_PACKET_TYPE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
928 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
929 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
930 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
931 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
932 [IXGBE_PACKET_TYPE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
933 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP,
934 [IXGBE_PACKET_TYPE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
935 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_SCTP,
937 if (unlikely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
938 return RTE_PTYPE_UNKNOWN;
940 pkt_info = (pkt_info >> IXGBE_PACKET_TYPE_SHIFT) &
941 IXGBE_PACKET_TYPE_MASK;
943 return ptype_table[pkt_info];
946 static inline uint64_t
947 ixgbe_rxd_pkt_info_to_pkt_flags(uint16_t pkt_info)
949 static uint64_t ip_rss_types_map[16] __rte_cache_aligned = {
950 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
951 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
952 PKT_RX_RSS_HASH, 0, 0, 0,
953 0, 0, 0, PKT_RX_FDIR,
955 #ifdef RTE_LIBRTE_IEEE1588
956 static uint64_t ip_pkt_etqf_map[8] = {
957 0, 0, 0, PKT_RX_IEEE1588_PTP,
961 if (likely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
962 return ip_pkt_etqf_map[(pkt_info >> 4) & 0X07] |
963 ip_rss_types_map[pkt_info & 0XF];
965 return ip_rss_types_map[pkt_info & 0XF];
967 return ip_rss_types_map[pkt_info & 0XF];
970 #else /* RTE_NEXT_ABI */
971 static inline uint64_t
972 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
976 static const uint64_t ip_pkt_types_map[16] = {
977 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
978 PKT_RX_IPV6_HDR, 0, 0, 0,
979 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
980 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
983 static const uint64_t ip_rss_types_map[16] = {
984 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
985 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
986 PKT_RX_RSS_HASH, 0, 0, 0,
987 0, 0, 0, PKT_RX_FDIR,
990 #ifdef RTE_LIBRTE_IEEE1588
991 static uint64_t ip_pkt_etqf_map[8] = {
992 0, 0, 0, PKT_RX_IEEE1588_PTP,
996 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
997 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
998 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
1000 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
1001 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
1004 return pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF];
1006 #endif /* RTE_NEXT_ABI */
1008 static inline uint64_t
1009 rx_desc_status_to_pkt_flags(uint32_t rx_status)
1014 * Check if VLAN present only.
1015 * Do not check whether L3/L4 rx checksum done by NIC or not,
1016 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
1018 pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;
1020 #ifdef RTE_LIBRTE_IEEE1588
1021 if (rx_status & IXGBE_RXD_STAT_TMST)
1022 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
1027 static inline uint64_t
1028 rx_desc_error_to_pkt_flags(uint32_t rx_status)
1031 * Bit 31: IPE, IPv4 checksum error
1032 * Bit 30: L4I, L4I integrity error
1034 static uint64_t error_to_pkt_flags_map[4] = {
1035 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
1036 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
1038 return error_to_pkt_flags_map[(rx_status >>
1039 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
1043 * LOOK_AHEAD defines how many desc statuses to check beyond the
1044 * current descriptor.
1045 * It must be a pound define for optimal performance.
1046 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
1047 * function only works with LOOK_AHEAD=8.
1049 #define LOOK_AHEAD 8
1050 #if (LOOK_AHEAD != 8)
1051 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
1054 ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
1056 volatile union ixgbe_adv_rx_desc *rxdp;
1057 struct ixgbe_rx_entry *rxep;
1058 struct rte_mbuf *mb;
1063 uint32_t s[LOOK_AHEAD];
1064 uint16_t pkt_info[LOOK_AHEAD];
1066 int s[LOOK_AHEAD], nb_dd;
1067 #endif /* RTE_NEXT_ABI */
1068 int i, j, nb_rx = 0;
1071 /* get references to current descriptor and S/W ring entry */
1072 rxdp = &rxq->rx_ring[rxq->rx_tail];
1073 rxep = &rxq->sw_ring[rxq->rx_tail];
1075 status = rxdp->wb.upper.status_error;
1076 /* check to make sure there is at least 1 packet to receive */
1077 if (!(status & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1081 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
1082 * reference packets that are ready to be received.
1084 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
1085 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
1087 /* Read desc statuses backwards to avoid race condition */
1088 for (j = LOOK_AHEAD-1; j >= 0; --j)
1089 s[j] = rte_le_to_cpu_32(rxdp[j].wb.upper.status_error);
1092 for (j = LOOK_AHEAD - 1; j >= 0; --j)
1093 pkt_info[j] = rxdp[j].wb.lower.lo_dword.
1095 #endif /* RTE_NEXT_ABI */
1097 /* Compute how many status bits were set */
1099 for (j = 0; j < LOOK_AHEAD; ++j)
1100 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
1104 /* Translate descriptor info to mbuf format */
1105 for (j = 0; j < nb_dd; ++j) {
1107 pkt_len = rte_le_to_cpu_16(rxdp[j].wb.upper.length) -
1109 mb->data_len = pkt_len;
1110 mb->pkt_len = pkt_len;
1111 mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
1113 /* convert descriptor fields to rte mbuf flags */
1115 pkt_flags = rx_desc_status_to_pkt_flags(s[j]);
1116 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
1118 ixgbe_rxd_pkt_info_to_pkt_flags(pkt_info[j]);
1119 mb->ol_flags = pkt_flags;
1121 ixgbe_rxd_pkt_info_to_pkt_type(pkt_info[j]);
1122 #else /* RTE_NEXT_ABI */
1123 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(
1125 rxdp[j].wb.lower.lo_dword.data));
1126 /* reuse status field from scan list */
1127 pkt_flags |= rx_desc_status_to_pkt_flags(s[j]);
1128 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
1129 mb->ol_flags = pkt_flags;
1130 #endif /* RTE_NEXT_ABI */
1132 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1133 mb->hash.rss = rte_le_to_cpu_32(
1134 rxdp[j].wb.lower.hi_dword.rss);
1135 else if (pkt_flags & PKT_RX_FDIR) {
1136 mb->hash.fdir.hash = rte_le_to_cpu_16(
1137 rxdp[j].wb.lower.hi_dword.csum_ip.csum) &
1138 IXGBE_ATR_HASH_MASK;
1139 mb->hash.fdir.id = rte_le_to_cpu_16(
1140 rxdp[j].wb.lower.hi_dword.csum_ip.ip_id);
1144 /* Move mbuf pointers from the S/W ring to the stage */
1145 for (j = 0; j < LOOK_AHEAD; ++j) {
1146 rxq->rx_stage[i + j] = rxep[j].mbuf;
1149 /* stop if all requested packets could not be received */
1150 if (nb_dd != LOOK_AHEAD)
1154 /* clear software ring entries so we can cleanup correctly */
1155 for (i = 0; i < nb_rx; ++i) {
1156 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1164 ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq, bool reset_mbuf)
1166 volatile union ixgbe_adv_rx_desc *rxdp;
1167 struct ixgbe_rx_entry *rxep;
1168 struct rte_mbuf *mb;
1173 /* allocate buffers in bulk directly into the S/W ring */
1174 alloc_idx = rxq->rx_free_trigger - (rxq->rx_free_thresh - 1);
1175 rxep = &rxq->sw_ring[alloc_idx];
1176 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1177 rxq->rx_free_thresh);
1178 if (unlikely(diag != 0))
1181 rxdp = &rxq->rx_ring[alloc_idx];
1182 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1183 /* populate the static rte mbuf fields */
1188 mb->port = rxq->port_id;
1191 rte_mbuf_refcnt_set(mb, 1);
1192 mb->data_off = RTE_PKTMBUF_HEADROOM;
1194 /* populate the descriptors */
1195 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
1196 rxdp[i].read.hdr_addr = dma_addr;
1197 rxdp[i].read.pkt_addr = dma_addr;
1200 /* update state of internal queue structure */
1201 rxq->rx_free_trigger = rxq->rx_free_trigger + rxq->rx_free_thresh;
1202 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1203 rxq->rx_free_trigger = rxq->rx_free_thresh - 1;
1209 static inline uint16_t
1210 ixgbe_rx_fill_from_stage(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1213 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1216 /* how many packets are ready to return? */
1217 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1219 /* copy mbuf pointers to the application's packet list */
1220 for (i = 0; i < nb_pkts; ++i)
1221 rx_pkts[i] = stage[i];
1223 /* update internal queue state */
1224 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1225 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1230 static inline uint16_t
1231 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1234 struct ixgbe_rx_queue *rxq = (struct ixgbe_rx_queue *)rx_queue;
1237 /* Any previously recv'd pkts will be returned from the Rx stage */
1238 if (rxq->rx_nb_avail)
1239 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1241 /* Scan the H/W ring for packets to receive */
1242 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1244 /* update internal queue state */
1245 rxq->rx_next_avail = 0;
1246 rxq->rx_nb_avail = nb_rx;
1247 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1249 /* if required, allocate new buffers to replenish descriptors */
1250 if (rxq->rx_tail > rxq->rx_free_trigger) {
1251 uint16_t cur_free_trigger = rxq->rx_free_trigger;
1253 if (ixgbe_rx_alloc_bufs(rxq, true) != 0) {
1255 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1256 "queue_id=%u", (unsigned) rxq->port_id,
1257 (unsigned) rxq->queue_id);
1259 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1260 rxq->rx_free_thresh;
1263 * Need to rewind any previous receives if we cannot
1264 * allocate new buffers to replenish the old ones.
1266 rxq->rx_nb_avail = 0;
1267 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1268 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1269 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1274 /* update tail pointer */
1276 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, cur_free_trigger);
1279 if (rxq->rx_tail >= rxq->nb_rx_desc)
1282 /* received any packets this loop? */
1283 if (rxq->rx_nb_avail)
1284 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1289 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1291 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1296 if (unlikely(nb_pkts == 0))
1299 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1300 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1302 /* request is relatively large, chunk it up */
1306 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1307 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1308 nb_rx = (uint16_t)(nb_rx + ret);
1309 nb_pkts = (uint16_t)(nb_pkts - ret);
1318 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1321 struct ixgbe_rx_queue *rxq;
1322 volatile union ixgbe_adv_rx_desc *rx_ring;
1323 volatile union ixgbe_adv_rx_desc *rxdp;
1324 struct ixgbe_rx_entry *sw_ring;
1325 struct ixgbe_rx_entry *rxe;
1326 struct rte_mbuf *rxm;
1327 struct rte_mbuf *nmb;
1328 union ixgbe_adv_rx_desc rxd;
1334 uint32_t hlen_type_rss;
1345 rx_id = rxq->rx_tail;
1346 rx_ring = rxq->rx_ring;
1347 sw_ring = rxq->sw_ring;
1348 while (nb_rx < nb_pkts) {
1350 * The order of operations here is important as the DD status
1351 * bit must not be read after any other descriptor fields.
1352 * rx_ring and rxdp are pointing to volatile data so the order
1353 * of accesses cannot be reordered by the compiler. If they were
1354 * not volatile, they could be reordered which could lead to
1355 * using invalid descriptor fields when read from rxd.
1357 rxdp = &rx_ring[rx_id];
1358 staterr = rxdp->wb.upper.status_error;
1359 if (!(staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1366 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1367 * is likely to be invalid and to be dropped by the various
1368 * validation checks performed by the network stack.
1370 * Allocate a new mbuf to replenish the RX ring descriptor.
1371 * If the allocation fails:
1372 * - arrange for that RX descriptor to be the first one
1373 * being parsed the next time the receive function is
1374 * invoked [on the same queue].
1376 * - Stop parsing the RX ring and return immediately.
1378 * This policy do not drop the packet received in the RX
1379 * descriptor for which the allocation of a new mbuf failed.
1380 * Thus, it allows that packet to be later retrieved if
1381 * mbuf have been freed in the mean time.
1382 * As a side effect, holding RX descriptors instead of
1383 * systematically giving them back to the NIC may lead to
1384 * RX ring exhaustion situations.
1385 * However, the NIC can gracefully prevent such situations
1386 * to happen by sending specific "back-pressure" flow control
1387 * frames to its peer(s).
1389 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1390 "ext_err_stat=0x%08x pkt_len=%u",
1391 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1392 (unsigned) rx_id, (unsigned) staterr,
1393 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1395 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1397 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1398 "queue_id=%u", (unsigned) rxq->port_id,
1399 (unsigned) rxq->queue_id);
1400 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1405 rxe = &sw_ring[rx_id];
1407 if (rx_id == rxq->nb_rx_desc)
1410 /* Prefetch next mbuf while processing current one. */
1411 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1414 * When next RX descriptor is on a cache-line boundary,
1415 * prefetch the next 4 RX descriptors and the next 8 pointers
1418 if ((rx_id & 0x3) == 0) {
1419 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1420 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1426 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1427 rxdp->read.hdr_addr = dma_addr;
1428 rxdp->read.pkt_addr = dma_addr;
1431 * Initialize the returned mbuf.
1432 * 1) setup generic mbuf fields:
1433 * - number of segments,
1436 * - RX port identifier.
1437 * 2) integrate hardware offload data, if any:
1438 * - RSS flag & hash,
1439 * - IP checksum flag,
1440 * - VLAN TCI, if any,
1443 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1445 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1446 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1449 rxm->pkt_len = pkt_len;
1450 rxm->data_len = pkt_len;
1451 rxm->port = rxq->port_id;
1454 pkt_info = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.hs_rss.
1456 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1457 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1459 pkt_flags = rx_desc_status_to_pkt_flags(staterr);
1460 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1461 pkt_flags = pkt_flags |
1462 ixgbe_rxd_pkt_info_to_pkt_flags(pkt_info);
1463 rxm->ol_flags = pkt_flags;
1464 rxm->packet_type = ixgbe_rxd_pkt_info_to_pkt_type(pkt_info);
1465 #else /* RTE_NEXT_ABI */
1466 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1467 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1468 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1470 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1471 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1472 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1473 rxm->ol_flags = pkt_flags;
1474 #endif /* RTE_NEXT_ABI */
1476 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1477 rxm->hash.rss = rte_le_to_cpu_32(
1478 rxd.wb.lower.hi_dword.rss);
1479 else if (pkt_flags & PKT_RX_FDIR) {
1480 rxm->hash.fdir.hash = rte_le_to_cpu_16(
1481 rxd.wb.lower.hi_dword.csum_ip.csum) &
1482 IXGBE_ATR_HASH_MASK;
1483 rxm->hash.fdir.id = rte_le_to_cpu_16(
1484 rxd.wb.lower.hi_dword.csum_ip.ip_id);
1487 * Store the mbuf address into the next entry of the array
1488 * of returned packets.
1490 rx_pkts[nb_rx++] = rxm;
1492 rxq->rx_tail = rx_id;
1495 * If the number of free RX descriptors is greater than the RX free
1496 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1498 * Update the RDT with the value of the last processed RX descriptor
1499 * minus 1, to guarantee that the RDT register is never equal to the
1500 * RDH register, which creates a "full" ring situtation from the
1501 * hardware point of view...
1503 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1504 if (nb_hold > rxq->rx_free_thresh) {
1505 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1506 "nb_hold=%u nb_rx=%u",
1507 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1508 (unsigned) rx_id, (unsigned) nb_hold,
1510 rx_id = (uint16_t) ((rx_id == 0) ?
1511 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1512 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1515 rxq->nb_rx_hold = nb_hold;
1520 * Detect an RSC descriptor.
1522 static inline uint32_t
1523 ixgbe_rsc_count(union ixgbe_adv_rx_desc *rx)
1525 return (rte_le_to_cpu_32(rx->wb.lower.lo_dword.data) &
1526 IXGBE_RXDADV_RSCCNT_MASK) >> IXGBE_RXDADV_RSCCNT_SHIFT;
1530 * ixgbe_fill_cluster_head_buf - fill the first mbuf of the returned packet
1532 * Fill the following info in the HEAD buffer of the Rx cluster:
1533 * - RX port identifier
1534 * - hardware offload data, if any:
1536 * - IP checksum flag
1537 * - VLAN TCI, if any
1539 * @head HEAD of the packet cluster
1540 * @desc HW descriptor to get data from
1541 * @port_id Port ID of the Rx queue
1544 ixgbe_fill_cluster_head_buf(
1545 struct rte_mbuf *head,
1546 union ixgbe_adv_rx_desc *desc,
1554 head->port = port_id;
1556 /* The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1557 * set in the pkt_flags field.
1559 head->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);
1560 pkt_info = rte_le_to_cpu_32(desc->wb.lower.lo_dword.hs_rss.pkt_info);
1561 pkt_flags = rx_desc_status_to_pkt_flags(staterr);
1562 pkt_flags |= rx_desc_error_to_pkt_flags(staterr);
1563 pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags(pkt_info);
1564 head->ol_flags = pkt_flags;
1565 head->packet_type = ixgbe_rxd_pkt_info_to_pkt_type(pkt_info);
1566 #else /* RTE_NEXT_ABI */
1567 uint32_t hlen_type_rss;
1570 head->port = port_id;
1573 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1574 * set in the pkt_flags field.
1576 head->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);
1577 hlen_type_rss = rte_le_to_cpu_32(desc->wb.lower.lo_dword.data);
1578 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1579 pkt_flags |= rx_desc_status_to_pkt_flags(staterr);
1580 pkt_flags |= rx_desc_error_to_pkt_flags(staterr);
1581 head->ol_flags = pkt_flags;
1582 #endif /* RTE_NEXT_ABI */
1584 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1585 head->hash.rss = rte_le_to_cpu_32(desc->wb.lower.hi_dword.rss);
1586 else if (pkt_flags & PKT_RX_FDIR) {
1587 head->hash.fdir.hash =
1588 rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.csum)
1589 & IXGBE_ATR_HASH_MASK;
1590 head->hash.fdir.id =
1591 rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.ip_id);
1596 * ixgbe_recv_pkts_lro - receive handler for and LRO case.
1598 * @rx_queue Rx queue handle
1599 * @rx_pkts table of received packets
1600 * @nb_pkts size of rx_pkts table
1601 * @bulk_alloc if TRUE bulk allocation is used for a HW ring refilling
1603 * Handles the Rx HW ring completions when RSC feature is configured. Uses an
1604 * additional ring of ixgbe_rsc_entry's that will hold the relevant RSC info.
1606 * We use the same logic as in Linux and in FreeBSD ixgbe drivers:
1607 * 1) When non-EOP RSC completion arrives:
1608 * a) Update the HEAD of the current RSC aggregation cluster with the new
1609 * segment's data length.
1610 * b) Set the "next" pointer of the current segment to point to the segment
1611 * at the NEXTP index.
1612 * c) Pass the HEAD of RSC aggregation cluster on to the next NEXTP entry
1613 * in the sw_rsc_ring.
1614 * 2) When EOP arrives we just update the cluster's total length and offload
1615 * flags and deliver the cluster up to the upper layers. In our case - put it
1616 * in the rx_pkts table.
1618 * Returns the number of received packets/clusters (according to the "bulk
1619 * receive" interface).
1621 static inline uint16_t
1622 ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
1625 struct ixgbe_rx_queue *rxq = rx_queue;
1626 volatile union ixgbe_adv_rx_desc *rx_ring = rxq->rx_ring;
1627 struct ixgbe_rx_entry *sw_ring = rxq->sw_ring;
1628 struct ixgbe_scattered_rx_entry *sw_sc_ring = rxq->sw_sc_ring;
1629 uint16_t rx_id = rxq->rx_tail;
1631 uint16_t nb_hold = rxq->nb_rx_hold;
1632 uint16_t prev_id = rxq->rx_tail;
1634 while (nb_rx < nb_pkts) {
1636 struct ixgbe_rx_entry *rxe;
1637 struct ixgbe_scattered_rx_entry *sc_entry;
1638 struct ixgbe_scattered_rx_entry *next_sc_entry;
1639 struct ixgbe_rx_entry *next_rxe;
1640 struct rte_mbuf *first_seg;
1641 struct rte_mbuf *rxm;
1642 struct rte_mbuf *nmb;
1643 union ixgbe_adv_rx_desc rxd;
1646 volatile union ixgbe_adv_rx_desc *rxdp;
1651 * The code in this whole file uses the volatile pointer to
1652 * ensure the read ordering of the status and the rest of the
1653 * descriptor fields (on the compiler level only!!!). This is so
1654 * UGLY - why not to just use the compiler barrier instead? DPDK
1655 * even has the rte_compiler_barrier() for that.
1657 * But most importantly this is just wrong because this doesn't
1658 * ensure memory ordering in a general case at all. For
1659 * instance, DPDK is supposed to work on Power CPUs where
1660 * compiler barrier may just not be enough!
1662 * I tried to write only this function properly to have a
1663 * starting point (as a part of an LRO/RSC series) but the
1664 * compiler cursed at me when I tried to cast away the
1665 * "volatile" from rx_ring (yes, it's volatile too!!!). So, I'm
1666 * keeping it the way it is for now.
1668 * The code in this file is broken in so many other places and
1669 * will just not work on a big endian CPU anyway therefore the
1670 * lines below will have to be revisited together with the rest
1674 * - Get rid of "volatile" crap and let the compiler do its
1676 * - Use the proper memory barrier (rte_rmb()) to ensure the
1677 * memory ordering below.
1679 rxdp = &rx_ring[rx_id];
1680 staterr = rte_le_to_cpu_32(rxdp->wb.upper.status_error);
1682 if (!(staterr & IXGBE_RXDADV_STAT_DD))
1687 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1688 "staterr=0x%x data_len=%u",
1689 rxq->port_id, rxq->queue_id, rx_id, staterr,
1690 rte_le_to_cpu_16(rxd.wb.upper.length));
1693 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1695 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed "
1696 "port_id=%u queue_id=%u",
1697 rxq->port_id, rxq->queue_id);
1699 rte_eth_devices[rxq->port_id].data->
1700 rx_mbuf_alloc_failed++;
1704 else if (nb_hold > rxq->rx_free_thresh) {
1705 uint16_t next_rdt = rxq->rx_free_trigger;
1707 if (!ixgbe_rx_alloc_bufs(rxq, false)) {
1709 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr,
1711 nb_hold -= rxq->rx_free_thresh;
1713 PMD_RX_LOG(DEBUG, "RX bulk alloc failed "
1714 "port_id=%u queue_id=%u",
1715 rxq->port_id, rxq->queue_id);
1717 rte_eth_devices[rxq->port_id].data->
1718 rx_mbuf_alloc_failed++;
1724 rxe = &sw_ring[rx_id];
1725 eop = staterr & IXGBE_RXDADV_STAT_EOP;
1727 next_id = rx_id + 1;
1728 if (next_id == rxq->nb_rx_desc)
1731 /* Prefetch next mbuf while processing current one. */
1732 rte_ixgbe_prefetch(sw_ring[next_id].mbuf);
1735 * When next RX descriptor is on a cache-line boundary,
1736 * prefetch the next 4 RX descriptors and the next 4 pointers
1739 if ((next_id & 0x3) == 0) {
1740 rte_ixgbe_prefetch(&rx_ring[next_id]);
1741 rte_ixgbe_prefetch(&sw_ring[next_id]);
1748 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1750 * Update RX descriptor with the physical address of the
1751 * new data buffer of the new allocated mbuf.
1755 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1756 rxdp->read.hdr_addr = dma;
1757 rxdp->read.pkt_addr = dma;
1762 * Set data length & data buffer address of mbuf.
1764 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1765 rxm->data_len = data_len;
1770 * Get next descriptor index:
1771 * - For RSC it's in the NEXTP field.
1772 * - For a scattered packet - it's just a following
1775 if (ixgbe_rsc_count(&rxd))
1777 (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1778 IXGBE_RXDADV_NEXTP_SHIFT;
1782 next_sc_entry = &sw_sc_ring[nextp_id];
1783 next_rxe = &sw_ring[nextp_id];
1784 rte_ixgbe_prefetch(next_rxe);
1787 sc_entry = &sw_sc_ring[rx_id];
1788 first_seg = sc_entry->fbuf;
1789 sc_entry->fbuf = NULL;
1792 * If this is the first buffer of the received packet,
1793 * set the pointer to the first mbuf of the packet and
1794 * initialize its context.
1795 * Otherwise, update the total length and the number of segments
1796 * of the current scattered packet, and update the pointer to
1797 * the last mbuf of the current packet.
1799 if (first_seg == NULL) {
1801 first_seg->pkt_len = data_len;
1802 first_seg->nb_segs = 1;
1804 first_seg->pkt_len += data_len;
1805 first_seg->nb_segs++;
1812 * If this is not the last buffer of the received packet, update
1813 * the pointer to the first mbuf at the NEXTP entry in the
1814 * sw_sc_ring and continue to parse the RX ring.
1817 rxm->next = next_rxe->mbuf;
1818 next_sc_entry->fbuf = first_seg;
1823 * This is the last buffer of the received packet - return
1824 * the current cluster to the user.
1828 /* Initialize the first mbuf of the returned packet */
1829 ixgbe_fill_cluster_head_buf(first_seg, &rxd, rxq->port_id,
1832 /* Prefetch data of first segment, if configured to do so. */
1833 rte_packet_prefetch((char *)first_seg->buf_addr +
1834 first_seg->data_off);
1837 * Store the mbuf address into the next entry of the array
1838 * of returned packets.
1840 rx_pkts[nb_rx++] = first_seg;
1844 * Record index of the next RX descriptor to probe.
1846 rxq->rx_tail = rx_id;
1849 * If the number of free RX descriptors is greater than the RX free
1850 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1852 * Update the RDT with the value of the last processed RX descriptor
1853 * minus 1, to guarantee that the RDT register is never equal to the
1854 * RDH register, which creates a "full" ring situtation from the
1855 * hardware point of view...
1857 if (!bulk_alloc && nb_hold > rxq->rx_free_thresh) {
1858 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1859 "nb_hold=%u nb_rx=%u",
1860 rxq->port_id, rxq->queue_id, rx_id, nb_hold, nb_rx);
1863 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, prev_id);
1867 rxq->nb_rx_hold = nb_hold;
1872 ixgbe_recv_pkts_lro_single_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1875 return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, false);
1879 ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1882 return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, true);
1885 /*********************************************************************
1887 * Queue management functions
1889 **********************************************************************/
1892 * Rings setup and release.
1894 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1895 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1896 * also optimize cache line size effect. H/W supports up to cache line size 128.
1898 #define IXGBE_ALIGN 128
1901 * Maximum number of Ring Descriptors.
1903 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1904 * descriptors should meet the following condition:
1905 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1907 #define IXGBE_MIN_RING_DESC 32
1908 #define IXGBE_MAX_RING_DESC 4096
1911 * Create memzone for HW rings. malloc can't be used as the physical address is
1912 * needed. If the memzone is already created, then this function returns a ptr
1915 static const struct rte_memzone * __attribute__((cold))
1916 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1917 uint16_t queue_id, uint32_t ring_size, int socket_id)
1919 char z_name[RTE_MEMZONE_NAMESIZE];
1920 const struct rte_memzone *mz;
1922 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1923 dev->driver->pci_drv.name, ring_name,
1924 dev->data->port_id, queue_id);
1926 mz = rte_memzone_lookup(z_name);
1930 #ifdef RTE_LIBRTE_XEN_DOM0
1931 return rte_memzone_reserve_bounded(z_name, ring_size,
1932 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1934 return rte_memzone_reserve_aligned(z_name, ring_size,
1935 socket_id, 0, IXGBE_ALIGN);
1939 static void __attribute__((cold))
1940 ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)
1944 if (txq->sw_ring != NULL) {
1945 for (i = 0; i < txq->nb_tx_desc; i++) {
1946 if (txq->sw_ring[i].mbuf != NULL) {
1947 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1948 txq->sw_ring[i].mbuf = NULL;
1954 static void __attribute__((cold))
1955 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
1958 txq->sw_ring != NULL)
1959 rte_free(txq->sw_ring);
1962 static void __attribute__((cold))
1963 ixgbe_tx_queue_release(struct ixgbe_tx_queue *txq)
1965 if (txq != NULL && txq->ops != NULL) {
1966 txq->ops->release_mbufs(txq);
1967 txq->ops->free_swring(txq);
1972 void __attribute__((cold))
1973 ixgbe_dev_tx_queue_release(void *txq)
1975 ixgbe_tx_queue_release(txq);
1978 /* (Re)set dynamic ixgbe_tx_queue fields to defaults */
1979 static void __attribute__((cold))
1980 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
1982 static const union ixgbe_adv_tx_desc zeroed_desc = {{0}};
1983 struct ixgbe_tx_entry *txe = txq->sw_ring;
1986 /* Zero out HW ring memory */
1987 for (i = 0; i < txq->nb_tx_desc; i++) {
1988 txq->tx_ring[i] = zeroed_desc;
1991 /* Initialize SW ring entries */
1992 prev = (uint16_t) (txq->nb_tx_desc - 1);
1993 for (i = 0; i < txq->nb_tx_desc; i++) {
1994 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1995 txd->wb.status = rte_cpu_to_le_32(IXGBE_TXD_STAT_DD);
1998 txe[prev].next_id = i;
2002 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2003 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2006 txq->nb_tx_used = 0;
2008 * Always allow 1 descriptor to be un-allocated to avoid
2009 * a H/W race condition
2011 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2012 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2014 memset((void*)&txq->ctx_cache, 0,
2015 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
2018 static const struct ixgbe_txq_ops def_txq_ops = {
2019 .release_mbufs = ixgbe_tx_queue_release_mbufs,
2020 .free_swring = ixgbe_tx_free_swring,
2021 .reset = ixgbe_reset_tx_queue,
2024 /* Takes an ethdev and a queue and sets up the tx function to be used based on
2025 * the queue parameters. Used in tx_queue_setup by primary process and then
2026 * in dev_init by secondary process when attaching to an existing ethdev.
2028 void __attribute__((cold))
2029 ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)
2031 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2032 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS)
2033 && (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
2034 PMD_INIT_LOG(INFO, "Using simple tx code path");
2035 #ifdef RTE_IXGBE_INC_VECTOR
2036 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
2037 (rte_eal_process_type() != RTE_PROC_PRIMARY ||
2038 ixgbe_txq_vec_setup(txq) == 0)) {
2039 PMD_INIT_LOG(INFO, "Vector tx enabled.");
2040 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
2043 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
2045 PMD_INIT_LOG(INFO, "Using full-featured tx code path");
2047 " - txq_flags = %lx " "[IXGBE_SIMPLE_FLAGS=%lx]",
2048 (unsigned long)txq->txq_flags,
2049 (unsigned long)IXGBE_SIMPLE_FLAGS);
2051 " - tx_rs_thresh = %lu " "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
2052 (unsigned long)txq->tx_rs_thresh,
2053 (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST);
2054 dev->tx_pkt_burst = ixgbe_xmit_pkts;
2058 int __attribute__((cold))
2059 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
2062 unsigned int socket_id,
2063 const struct rte_eth_txconf *tx_conf)
2065 const struct rte_memzone *tz;
2066 struct ixgbe_tx_queue *txq;
2067 struct ixgbe_hw *hw;
2068 uint16_t tx_rs_thresh, tx_free_thresh;
2070 PMD_INIT_FUNC_TRACE();
2071 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2074 * Validate number of transmit descriptors.
2075 * It must not exceed hardware maximum, and must be multiple
2078 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
2079 (nb_desc > IXGBE_MAX_RING_DESC) ||
2080 (nb_desc < IXGBE_MIN_RING_DESC)) {
2085 * The following two parameters control the setting of the RS bit on
2086 * transmit descriptors.
2087 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
2088 * descriptors have been used.
2089 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
2090 * descriptors are used or if the number of descriptors required
2091 * to transmit a packet is greater than the number of free TX
2093 * The following constraints must be satisfied:
2094 * tx_rs_thresh must be greater than 0.
2095 * tx_rs_thresh must be less than the size of the ring minus 2.
2096 * tx_rs_thresh must be less than or equal to tx_free_thresh.
2097 * tx_rs_thresh must be a divisor of the ring size.
2098 * tx_free_thresh must be greater than 0.
2099 * tx_free_thresh must be less than the size of the ring minus 3.
2100 * One descriptor in the TX ring is used as a sentinel to avoid a
2101 * H/W race condition, hence the maximum threshold constraints.
2102 * When set to zero use default values.
2104 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2105 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2106 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2107 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2108 if (tx_rs_thresh >= (nb_desc - 2)) {
2109 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
2110 "of TX descriptors minus 2. (tx_rs_thresh=%u "
2111 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2112 (int)dev->data->port_id, (int)queue_idx);
2115 if (tx_free_thresh >= (nb_desc - 3)) {
2116 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2117 "tx_free_thresh must be less than the number of "
2118 "TX descriptors minus 3. (tx_free_thresh=%u "
2119 "port=%d queue=%d)",
2120 (unsigned int)tx_free_thresh,
2121 (int)dev->data->port_id, (int)queue_idx);
2124 if (tx_rs_thresh > tx_free_thresh) {
2125 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
2126 "tx_free_thresh. (tx_free_thresh=%u "
2127 "tx_rs_thresh=%u port=%d queue=%d)",
2128 (unsigned int)tx_free_thresh,
2129 (unsigned int)tx_rs_thresh,
2130 (int)dev->data->port_id,
2134 if ((nb_desc % tx_rs_thresh) != 0) {
2135 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2136 "number of TX descriptors. (tx_rs_thresh=%u "
2137 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2138 (int)dev->data->port_id, (int)queue_idx);
2143 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
2144 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
2145 * by the NIC and all descriptors are written back after the NIC
2146 * accumulates WTHRESH descriptors.
2148 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2149 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2150 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
2151 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2152 (int)dev->data->port_id, (int)queue_idx);
2156 /* Free memory prior to re-allocation if needed... */
2157 if (dev->data->tx_queues[queue_idx] != NULL) {
2158 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
2159 dev->data->tx_queues[queue_idx] = NULL;
2162 /* First allocate the tx queue data structure */
2163 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct ixgbe_tx_queue),
2164 RTE_CACHE_LINE_SIZE, socket_id);
2169 * Allocate TX ring hardware descriptors. A memzone large enough to
2170 * handle the maximum ring size is allocated in order to allow for
2171 * resizing in later calls to the queue setup function.
2173 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
2174 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
2177 ixgbe_tx_queue_release(txq);
2181 txq->nb_tx_desc = nb_desc;
2182 txq->tx_rs_thresh = tx_rs_thresh;
2183 txq->tx_free_thresh = tx_free_thresh;
2184 txq->pthresh = tx_conf->tx_thresh.pthresh;
2185 txq->hthresh = tx_conf->tx_thresh.hthresh;
2186 txq->wthresh = tx_conf->tx_thresh.wthresh;
2187 txq->queue_id = queue_idx;
2188 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2189 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2190 txq->port_id = dev->data->port_id;
2191 txq->txq_flags = tx_conf->txq_flags;
2192 txq->ops = &def_txq_ops;
2193 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2196 * Modification to set VFTDT for virtual function if vf is detected
2198 if (hw->mac.type == ixgbe_mac_82599_vf ||
2199 hw->mac.type == ixgbe_mac_X540_vf ||
2200 hw->mac.type == ixgbe_mac_X550_vf ||
2201 hw->mac.type == ixgbe_mac_X550EM_x_vf)
2202 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
2204 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
2205 #ifndef RTE_LIBRTE_XEN_DOM0
2206 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
2208 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2210 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
2212 /* Allocate software ring */
2213 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
2214 sizeof(struct ixgbe_tx_entry) * nb_desc,
2215 RTE_CACHE_LINE_SIZE, socket_id);
2216 if (txq->sw_ring == NULL) {
2217 ixgbe_tx_queue_release(txq);
2220 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2221 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
2223 /* set up vector or scalar TX function as appropriate */
2224 ixgbe_set_tx_function(dev, txq);
2226 txq->ops->reset(txq);
2228 dev->data->tx_queues[queue_idx] = txq;
2235 * ixgbe_free_sc_cluster - free the not-yet-completed scattered cluster
2237 * The "next" pointer of the last segment of (not-yet-completed) RSC clusters
2238 * in the sw_rsc_ring is not set to NULL but rather points to the next
2239 * mbuf of this RSC aggregation (that has not been completed yet and still
2240 * resides on the HW ring). So, instead of calling for rte_pktmbuf_free() we
2241 * will just free first "nb_segs" segments of the cluster explicitly by calling
2242 * an rte_pktmbuf_free_seg().
2244 * @m scattered cluster head
2246 static void __attribute__((cold))
2247 ixgbe_free_sc_cluster(struct rte_mbuf *m)
2249 uint8_t i, nb_segs = m->nb_segs;
2250 struct rte_mbuf *next_seg;
2252 for (i = 0; i < nb_segs; i++) {
2254 rte_pktmbuf_free_seg(m);
2259 static void __attribute__((cold))
2260 ixgbe_rx_queue_release_mbufs(struct ixgbe_rx_queue *rxq)
2264 #ifdef RTE_IXGBE_INC_VECTOR
2265 /* SSE Vector driver has a different way of releasing mbufs. */
2266 if (rxq->rx_using_sse) {
2267 ixgbe_rx_queue_release_mbufs_vec(rxq);
2272 if (rxq->sw_ring != NULL) {
2273 for (i = 0; i < rxq->nb_rx_desc; i++) {
2274 if (rxq->sw_ring[i].mbuf != NULL) {
2275 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2276 rxq->sw_ring[i].mbuf = NULL;
2279 if (rxq->rx_nb_avail) {
2280 for (i = 0; i < rxq->rx_nb_avail; ++i) {
2281 struct rte_mbuf *mb;
2282 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2283 rte_pktmbuf_free_seg(mb);
2285 rxq->rx_nb_avail = 0;
2289 if (rxq->sw_sc_ring)
2290 for (i = 0; i < rxq->nb_rx_desc; i++)
2291 if (rxq->sw_sc_ring[i].fbuf) {
2292 ixgbe_free_sc_cluster(rxq->sw_sc_ring[i].fbuf);
2293 rxq->sw_sc_ring[i].fbuf = NULL;
2297 static void __attribute__((cold))
2298 ixgbe_rx_queue_release(struct ixgbe_rx_queue *rxq)
2301 ixgbe_rx_queue_release_mbufs(rxq);
2302 rte_free(rxq->sw_ring);
2303 rte_free(rxq->sw_sc_ring);
2308 void __attribute__((cold))
2309 ixgbe_dev_rx_queue_release(void *rxq)
2311 ixgbe_rx_queue_release(rxq);
2315 * Check if Rx Burst Bulk Alloc function can be used.
2317 * 0: the preconditions are satisfied and the bulk allocation function
2319 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2320 * function must be used.
2322 static inline int __attribute__((cold))
2323 check_rx_burst_bulk_alloc_preconditions(struct ixgbe_rx_queue *rxq)
2328 * Make sure the following pre-conditions are satisfied:
2329 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2330 * rxq->rx_free_thresh < rxq->nb_rx_desc
2331 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2332 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
2333 * Scattered packets are not supported. This should be checked
2334 * outside of this function.
2336 if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
2337 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2338 "rxq->rx_free_thresh=%d, "
2339 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2340 rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
2342 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
2343 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2344 "rxq->rx_free_thresh=%d, "
2345 "rxq->nb_rx_desc=%d",
2346 rxq->rx_free_thresh, rxq->nb_rx_desc);
2348 } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
2349 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2350 "rxq->nb_rx_desc=%d, "
2351 "rxq->rx_free_thresh=%d",
2352 rxq->nb_rx_desc, rxq->rx_free_thresh);
2354 } else if (!(rxq->nb_rx_desc <
2355 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST))) {
2356 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2357 "rxq->nb_rx_desc=%d, "
2358 "IXGBE_MAX_RING_DESC=%d, "
2359 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2360 rxq->nb_rx_desc, IXGBE_MAX_RING_DESC,
2361 RTE_PMD_IXGBE_RX_MAX_BURST);
2368 /* Reset dynamic ixgbe_rx_queue fields back to defaults */
2369 static void __attribute__((cold))
2370 ixgbe_reset_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_rx_queue *rxq)
2372 static const union ixgbe_adv_rx_desc zeroed_desc = {{0}};
2374 uint16_t len = rxq->nb_rx_desc;
2377 * By default, the Rx queue setup function allocates enough memory for
2378 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2379 * extra memory at the end of the descriptor ring to be zero'd out. A
2380 * pre-condition for using the Rx burst bulk alloc function is that the
2381 * number of descriptors is less than or equal to
2382 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2383 * constraints here to see if we need to zero out memory after the end
2384 * of the H/W descriptor ring.
2386 if (adapter->rx_bulk_alloc_allowed)
2387 /* zero out extra memory */
2388 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2391 * Zero out HW ring memory. Zero out extra memory at the end of
2392 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2393 * reads extra memory as zeros.
2395 for (i = 0; i < len; i++) {
2396 rxq->rx_ring[i] = zeroed_desc;
2400 * initialize extra software ring entries. Space for these extra
2401 * entries is always allocated
2403 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2404 for (i = rxq->nb_rx_desc; i < len; ++i) {
2405 rxq->sw_ring[i].mbuf = &rxq->fake_mbuf;
2408 rxq->rx_nb_avail = 0;
2409 rxq->rx_next_avail = 0;
2410 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2412 rxq->nb_rx_hold = 0;
2413 rxq->pkt_first_seg = NULL;
2414 rxq->pkt_last_seg = NULL;
2416 #ifdef RTE_IXGBE_INC_VECTOR
2417 rxq->rxrearm_start = 0;
2418 rxq->rxrearm_nb = 0;
2422 int __attribute__((cold))
2423 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2426 unsigned int socket_id,
2427 const struct rte_eth_rxconf *rx_conf,
2428 struct rte_mempool *mp)
2430 const struct rte_memzone *rz;
2431 struct ixgbe_rx_queue *rxq;
2432 struct ixgbe_hw *hw;
2434 struct ixgbe_adapter *adapter =
2435 (struct ixgbe_adapter *)dev->data->dev_private;
2437 PMD_INIT_FUNC_TRACE();
2438 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2441 * Validate number of receive descriptors.
2442 * It must not exceed hardware maximum, and must be multiple
2445 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2446 (nb_desc > IXGBE_MAX_RING_DESC) ||
2447 (nb_desc < IXGBE_MIN_RING_DESC)) {
2451 /* Free memory prior to re-allocation if needed... */
2452 if (dev->data->rx_queues[queue_idx] != NULL) {
2453 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2454 dev->data->rx_queues[queue_idx] = NULL;
2457 /* First allocate the rx queue data structure */
2458 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct ixgbe_rx_queue),
2459 RTE_CACHE_LINE_SIZE, socket_id);
2463 rxq->nb_rx_desc = nb_desc;
2464 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2465 rxq->queue_id = queue_idx;
2466 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2467 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2468 rxq->port_id = dev->data->port_id;
2469 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2471 rxq->drop_en = rx_conf->rx_drop_en;
2472 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2475 * Allocate RX ring hardware descriptors. A memzone large enough to
2476 * handle the maximum ring size is allocated in order to allow for
2477 * resizing in later calls to the queue setup function.
2479 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2480 RX_RING_SZ, socket_id);
2482 ixgbe_rx_queue_release(rxq);
2487 * Zero init all the descriptors in the ring.
2489 memset (rz->addr, 0, RX_RING_SZ);
2492 * Modified to setup VFRDT for Virtual Function
2494 if (hw->mac.type == ixgbe_mac_82599_vf ||
2495 hw->mac.type == ixgbe_mac_X540_vf ||
2496 hw->mac.type == ixgbe_mac_X550_vf ||
2497 hw->mac.type == ixgbe_mac_X550EM_x_vf) {
2499 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2501 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2505 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2507 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2509 #ifndef RTE_LIBRTE_XEN_DOM0
2510 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2512 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2514 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2517 * Certain constraints must be met in order to use the bulk buffer
2518 * allocation Rx burst function. If any of Rx queues doesn't meet them
2519 * the feature should be disabled for the whole port.
2521 if (check_rx_burst_bulk_alloc_preconditions(rxq)) {
2522 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Rx Bulk Alloc "
2523 "preconditions - canceling the feature for "
2524 "the whole port[%d]",
2525 rxq->queue_id, rxq->port_id);
2526 adapter->rx_bulk_alloc_allowed = false;
2530 * Allocate software ring. Allow for space at the end of the
2531 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2532 * function does not access an invalid memory region.
2535 if (adapter->rx_bulk_alloc_allowed)
2536 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2538 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2539 sizeof(struct ixgbe_rx_entry) * len,
2540 RTE_CACHE_LINE_SIZE, socket_id);
2541 if (!rxq->sw_ring) {
2542 ixgbe_rx_queue_release(rxq);
2547 * Always allocate even if it's not going to be needed in order to
2548 * simplify the code.
2550 * This ring is used in LRO and Scattered Rx cases and Scattered Rx may
2551 * be requested in ixgbe_dev_rx_init(), which is called later from
2555 rte_zmalloc_socket("rxq->sw_sc_ring",
2556 sizeof(struct ixgbe_scattered_rx_entry) * len,
2557 RTE_CACHE_LINE_SIZE, socket_id);
2558 if (!rxq->sw_sc_ring) {
2559 ixgbe_rx_queue_release(rxq);
2563 PMD_INIT_LOG(DEBUG, "sw_ring=%p sw_sc_ring=%p hw_ring=%p "
2564 "dma_addr=0x%"PRIx64,
2565 rxq->sw_ring, rxq->sw_sc_ring, rxq->rx_ring,
2566 rxq->rx_ring_phys_addr);
2568 if (!rte_is_power_of_2(nb_desc)) {
2569 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
2570 "preconditions - canceling the feature for "
2571 "the whole port[%d]",
2572 rxq->queue_id, rxq->port_id);
2573 adapter->rx_vec_allowed = false;
2575 ixgbe_rxq_vec_setup(rxq);
2577 dev->data->rx_queues[queue_idx] = rxq;
2579 ixgbe_reset_rx_queue(adapter, rxq);
2585 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2587 #define IXGBE_RXQ_SCAN_INTERVAL 4
2588 volatile union ixgbe_adv_rx_desc *rxdp;
2589 struct ixgbe_rx_queue *rxq;
2592 if (rx_queue_id >= dev->data->nb_rx_queues) {
2593 PMD_RX_LOG(ERR, "Invalid RX queue id=%d", rx_queue_id);
2597 rxq = dev->data->rx_queues[rx_queue_id];
2598 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2600 while ((desc < rxq->nb_rx_desc) &&
2601 (rxdp->wb.upper.status_error &
2602 rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))) {
2603 desc += IXGBE_RXQ_SCAN_INTERVAL;
2604 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2605 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2606 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2607 desc - rxq->nb_rx_desc]);
2614 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2616 volatile union ixgbe_adv_rx_desc *rxdp;
2617 struct ixgbe_rx_queue *rxq = rx_queue;
2620 if (unlikely(offset >= rxq->nb_rx_desc))
2622 desc = rxq->rx_tail + offset;
2623 if (desc >= rxq->nb_rx_desc)
2624 desc -= rxq->nb_rx_desc;
2626 rxdp = &rxq->rx_ring[desc];
2627 return !!(rxdp->wb.upper.status_error &
2628 rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD));
2631 void __attribute__((cold))
2632 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2635 struct ixgbe_adapter *adapter =
2636 (struct ixgbe_adapter *)dev->data->dev_private;
2638 PMD_INIT_FUNC_TRACE();
2640 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2641 struct ixgbe_tx_queue *txq = dev->data->tx_queues[i];
2643 txq->ops->release_mbufs(txq);
2644 txq->ops->reset(txq);
2648 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2649 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
2651 ixgbe_rx_queue_release_mbufs(rxq);
2652 ixgbe_reset_rx_queue(adapter, rxq);
2658 ixgbe_dev_free_queues(struct rte_eth_dev *dev)
2662 PMD_INIT_FUNC_TRACE();
2664 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2665 ixgbe_dev_rx_queue_release(dev->data->rx_queues[i]);
2666 dev->data->rx_queues[i] = NULL;
2668 dev->data->nb_rx_queues = 0;
2670 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2671 ixgbe_dev_tx_queue_release(dev->data->tx_queues[i]);
2672 dev->data->tx_queues[i] = NULL;
2674 dev->data->nb_tx_queues = 0;
2677 /*********************************************************************
2679 * Device RX/TX init functions
2681 **********************************************************************/
2684 * Receive Side Scaling (RSS)
2685 * See section 7.1.2.8 in the following document:
2686 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2689 * The source and destination IP addresses of the IP header and the source
2690 * and destination ports of TCP/UDP headers, if any, of received packets are
2691 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2692 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2693 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2694 * RSS output index which is used as the RX queue index where to store the
2696 * The following output is supplied in the RX write-back descriptor:
2697 * - 32-bit result of the Microsoft RSS hash function,
2698 * - 4-bit RSS type field.
2702 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2703 * Used as the default key.
2705 static uint8_t rss_intel_key[40] = {
2706 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2707 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2708 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2709 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2710 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2714 ixgbe_rss_disable(struct rte_eth_dev *dev)
2716 struct ixgbe_hw *hw;
2719 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2720 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2721 mrqc &= ~IXGBE_MRQC_RSSEN;
2722 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2726 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2734 hash_key = rss_conf->rss_key;
2735 if (hash_key != NULL) {
2736 /* Fill in RSS hash key */
2737 for (i = 0; i < 10; i++) {
2738 rss_key = hash_key[(i * 4)];
2739 rss_key |= hash_key[(i * 4) + 1] << 8;
2740 rss_key |= hash_key[(i * 4) + 2] << 16;
2741 rss_key |= hash_key[(i * 4) + 3] << 24;
2742 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2746 /* Set configured hashing protocols in MRQC register */
2747 rss_hf = rss_conf->rss_hf;
2748 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2749 if (rss_hf & ETH_RSS_IPV4)
2750 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2751 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2752 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2753 if (rss_hf & ETH_RSS_IPV6)
2754 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2755 if (rss_hf & ETH_RSS_IPV6_EX)
2756 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2757 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2758 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2759 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2760 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2761 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2762 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2763 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2764 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2765 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2766 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2767 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2771 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2772 struct rte_eth_rss_conf *rss_conf)
2774 struct ixgbe_hw *hw;
2778 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2781 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2782 * "RSS enabling cannot be done dynamically while it must be
2783 * preceded by a software reset"
2784 * Before changing anything, first check that the update RSS operation
2785 * does not attempt to disable RSS, if RSS was enabled at
2786 * initialization time, or does not attempt to enable RSS, if RSS was
2787 * disabled at initialization time.
2789 rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
2790 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2791 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2792 if (rss_hf != 0) /* Enable RSS */
2794 return 0; /* Nothing to do */
2797 if (rss_hf == 0) /* Disable RSS */
2799 ixgbe_hw_rss_hash_set(hw, rss_conf);
2804 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2805 struct rte_eth_rss_conf *rss_conf)
2807 struct ixgbe_hw *hw;
2814 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2815 hash_key = rss_conf->rss_key;
2816 if (hash_key != NULL) {
2817 /* Return RSS hash key */
2818 for (i = 0; i < 10; i++) {
2819 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2820 hash_key[(i * 4)] = rss_key & 0x000000FF;
2821 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2822 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2823 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2827 /* Get RSS functions configured in MRQC register */
2828 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2829 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2830 rss_conf->rss_hf = 0;
2834 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2835 rss_hf |= ETH_RSS_IPV4;
2836 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2837 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2838 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2839 rss_hf |= ETH_RSS_IPV6;
2840 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2841 rss_hf |= ETH_RSS_IPV6_EX;
2842 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2843 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2844 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2845 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2846 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2847 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2848 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2849 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2850 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2851 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2852 rss_conf->rss_hf = rss_hf;
2857 ixgbe_rss_configure(struct rte_eth_dev *dev)
2859 struct rte_eth_rss_conf rss_conf;
2860 struct ixgbe_hw *hw;
2865 PMD_INIT_FUNC_TRACE();
2866 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2869 * Fill in redirection table
2870 * The byte-swap is needed because NIC registers are in
2871 * little-endian order.
2874 for (i = 0, j = 0; i < 128; i++, j++) {
2875 if (j == dev->data->nb_rx_queues)
2877 reta = (reta << 8) | j;
2879 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2884 * Configure the RSS key and the RSS protocols used to compute
2885 * the RSS hash of input packets.
2887 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2888 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
2889 ixgbe_rss_disable(dev);
2892 if (rss_conf.rss_key == NULL)
2893 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2894 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2897 #define NUM_VFTA_REGISTERS 128
2898 #define NIC_RX_BUFFER_SIZE 0x200
2901 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2903 struct rte_eth_vmdq_dcb_conf *cfg;
2904 struct ixgbe_hw *hw;
2905 enum rte_eth_nb_pools num_pools;
2906 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2908 uint8_t nb_tcs; /* number of traffic classes */
2911 PMD_INIT_FUNC_TRACE();
2912 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2913 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2914 num_pools = cfg->nb_queue_pools;
2915 /* Check we have a valid number of pools */
2916 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2917 ixgbe_rss_disable(dev);
2920 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2921 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2925 * split rx buffer up into sections, each for 1 traffic class
2927 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2928 for (i = 0 ; i < nb_tcs; i++) {
2929 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2930 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2931 /* clear 10 bits. */
2932 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2933 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2935 /* zero alloc all unused TCs */
2936 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2937 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2938 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2939 /* clear 10 bits. */
2940 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2943 /* MRQC: enable vmdq and dcb */
2944 mrqc = ((num_pools == ETH_16_POOLS) ? \
2945 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2946 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2948 /* PFVTCTL: turn on virtualisation and set the default pool */
2949 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2950 if (cfg->enable_default_pool) {
2951 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2953 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2956 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2958 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2960 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2962 * mapping is done with 3 bits per priority,
2963 * so shift by i*3 each time
2965 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2967 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2969 /* RTRPCS: DCB related */
2970 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2972 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2973 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2974 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2975 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2977 /* VFTA - enable all vlan filters */
2978 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2979 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2982 /* VFRE: pool enabling for receive - 16 or 32 */
2983 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2984 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2987 * MPSAR - allow pools to read specific mac addresses
2988 * In this case, all pools should be able to read from mac addr 0
2990 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2991 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2993 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2994 for (i = 0; i < cfg->nb_pool_maps; i++) {
2995 /* set vlan id in VF register and set the valid bit */
2996 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2997 (cfg->pool_map[i].vlan_id & 0xFFF)));
2999 * Put the allowed pools in VFB reg. As we only have 16 or 32
3000 * pools, we only need to use the first half of the register
3003 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
3008 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
3009 * @hw: pointer to hardware structure
3010 * @dcb_config: pointer to ixgbe_dcb_config structure
3013 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
3014 struct ixgbe_dcb_config *dcb_config)
3019 PMD_INIT_FUNC_TRACE();
3020 if (hw->mac.type != ixgbe_mac_82598EB) {
3021 /* Disable the Tx desc arbiter so that MTQC can be changed */
3022 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3023 reg |= IXGBE_RTTDCS_ARBDIS;
3024 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3026 /* Enable DCB for Tx with 8 TCs */
3027 if (dcb_config->num_tcs.pg_tcs == 8) {
3028 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3031 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3033 if (dcb_config->vt_mode)
3034 reg |= IXGBE_MTQC_VT_ENA;
3035 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3037 /* Disable drop for all queues */
3038 for (q = 0; q < 128; q++)
3039 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3040 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3042 /* Enable the Tx desc arbiter */
3043 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3044 reg &= ~IXGBE_RTTDCS_ARBDIS;
3045 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3047 /* Enable Security TX Buffer IFG for DCB */
3048 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3049 reg |= IXGBE_SECTX_DCB;
3050 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
3056 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
3057 * @dev: pointer to rte_eth_dev structure
3058 * @dcb_config: pointer to ixgbe_dcb_config structure
3061 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
3062 struct ixgbe_dcb_config *dcb_config)
3064 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3065 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3066 struct ixgbe_hw *hw =
3067 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3069 PMD_INIT_FUNC_TRACE();
3070 if (hw->mac.type != ixgbe_mac_82598EB)
3071 /*PF VF Transmit Enable*/
3072 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
3073 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3075 /*Configure general DCB TX parameters*/
3076 ixgbe_dcb_tx_hw_config(hw,dcb_config);
3081 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
3082 struct ixgbe_dcb_config *dcb_config)
3084 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
3085 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3086 struct ixgbe_dcb_tc_config *tc;
3089 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3090 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
3091 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3092 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3095 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3096 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3098 /* User Priority to Traffic Class mapping */
3099 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3100 j = vmdq_rx_conf->dcb_queue[i];
3101 tc = &dcb_config->tc_config[j];
3102 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
3108 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
3109 struct ixgbe_dcb_config *dcb_config)
3111 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3112 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3113 struct ixgbe_dcb_tc_config *tc;
3116 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3117 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
3118 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3119 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3122 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3123 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3126 /* User Priority to Traffic Class mapping */
3127 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3128 j = vmdq_tx_conf->dcb_queue[i];
3129 tc = &dcb_config->tc_config[j];
3130 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
3137 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
3138 struct ixgbe_dcb_config *dcb_config)
3140 struct rte_eth_dcb_rx_conf *rx_conf =
3141 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
3142 struct ixgbe_dcb_tc_config *tc;
3145 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
3146 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
3148 /* User Priority to Traffic Class mapping */
3149 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3150 j = rx_conf->dcb_queue[i];
3151 tc = &dcb_config->tc_config[j];
3152 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
3158 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
3159 struct ixgbe_dcb_config *dcb_config)
3161 struct rte_eth_dcb_tx_conf *tx_conf =
3162 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
3163 struct ixgbe_dcb_tc_config *tc;
3166 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
3167 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
3169 /* User Priority to Traffic Class mapping */
3170 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3171 j = tx_conf->dcb_queue[i];
3172 tc = &dcb_config->tc_config[j];
3173 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
3179 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
3180 * @hw: pointer to hardware structure
3181 * @dcb_config: pointer to ixgbe_dcb_config structure
3184 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
3185 struct ixgbe_dcb_config *dcb_config)
3191 PMD_INIT_FUNC_TRACE();
3193 * Disable the arbiter before changing parameters
3194 * (always enable recycle mode; WSP)
3196 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
3197 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3199 if (hw->mac.type != ixgbe_mac_82598EB) {
3200 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
3201 if (dcb_config->num_tcs.pg_tcs == 4) {
3202 if (dcb_config->vt_mode)
3203 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3204 IXGBE_MRQC_VMDQRT4TCEN;
3206 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3207 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3211 if (dcb_config->num_tcs.pg_tcs == 8) {
3212 if (dcb_config->vt_mode)
3213 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3214 IXGBE_MRQC_VMDQRT8TCEN;
3216 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3217 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3222 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
3225 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3226 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3227 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3228 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3230 /* VFTA - enable all vlan filters */
3231 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3232 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3236 * Configure Rx packet plane (recycle mode; WSP) and
3239 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
3240 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3246 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
3247 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3249 switch (hw->mac.type) {
3250 case ixgbe_mac_82598EB:
3251 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
3253 case ixgbe_mac_82599EB:
3254 case ixgbe_mac_X540:
3255 case ixgbe_mac_X550:
3256 case ixgbe_mac_X550EM_x:
3257 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
3266 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
3267 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3269 switch (hw->mac.type) {
3270 case ixgbe_mac_82598EB:
3271 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
3272 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
3274 case ixgbe_mac_82599EB:
3275 case ixgbe_mac_X540:
3276 case ixgbe_mac_X550:
3277 case ixgbe_mac_X550EM_x:
3278 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
3279 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
3286 #define DCB_RX_CONFIG 1
3287 #define DCB_TX_CONFIG 1
3288 #define DCB_TX_PB 1024
3290 * ixgbe_dcb_hw_configure - Enable DCB and configure
3291 * general DCB in VT mode and non-VT mode parameters
3292 * @dev: pointer to rte_eth_dev structure
3293 * @dcb_config: pointer to ixgbe_dcb_config structure
3296 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
3297 struct ixgbe_dcb_config *dcb_config)
3300 uint8_t i,pfc_en,nb_tcs;
3302 uint8_t config_dcb_rx = 0;
3303 uint8_t config_dcb_tx = 0;
3304 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3305 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3306 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3307 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3308 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3309 struct ixgbe_dcb_tc_config *tc;
3310 uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3311 struct ixgbe_hw *hw =
3312 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3314 switch(dev->data->dev_conf.rxmode.mq_mode){
3315 case ETH_MQ_RX_VMDQ_DCB:
3316 dcb_config->vt_mode = true;
3317 if (hw->mac.type != ixgbe_mac_82598EB) {
3318 config_dcb_rx = DCB_RX_CONFIG;
3320 *get dcb and VT rx configuration parameters
3323 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
3324 /*Configure general VMDQ and DCB RX parameters*/
3325 ixgbe_vmdq_dcb_configure(dev);
3329 dcb_config->vt_mode = false;
3330 config_dcb_rx = DCB_RX_CONFIG;
3331 /* Get dcb TX configuration parameters from rte_eth_conf */
3332 ixgbe_dcb_rx_config(dev,dcb_config);
3333 /*Configure general DCB RX parameters*/
3334 ixgbe_dcb_rx_hw_config(hw, dcb_config);
3337 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
3340 switch (dev->data->dev_conf.txmode.mq_mode) {
3341 case ETH_MQ_TX_VMDQ_DCB:
3342 dcb_config->vt_mode = true;
3343 config_dcb_tx = DCB_TX_CONFIG;
3344 /* get DCB and VT TX configuration parameters from rte_eth_conf */
3345 ixgbe_dcb_vt_tx_config(dev,dcb_config);
3346 /*Configure general VMDQ and DCB TX parameters*/
3347 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
3351 dcb_config->vt_mode = false;
3352 config_dcb_tx = DCB_TX_CONFIG;
3353 /*get DCB TX configuration parameters from rte_eth_conf*/
3354 ixgbe_dcb_tx_config(dev,dcb_config);
3355 /*Configure general DCB TX parameters*/
3356 ixgbe_dcb_tx_hw_config(hw, dcb_config);
3359 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
3363 nb_tcs = dcb_config->num_tcs.pfc_tcs;
3365 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3366 if(nb_tcs == ETH_4_TCS) {
3367 /* Avoid un-configured priority mapping to TC0 */
3369 uint8_t mask = 0xFF;
3370 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
3371 mask = (uint8_t)(mask & (~ (1 << map[i])));
3372 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
3373 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
3377 /* Re-configure 4 TCs BW */
3378 for (i = 0; i < nb_tcs; i++) {
3379 tc = &dcb_config->tc_config[i];
3380 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
3381 (uint8_t)(100 / nb_tcs);
3382 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
3383 (uint8_t)(100 / nb_tcs);
3385 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3386 tc = &dcb_config->tc_config[i];
3387 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
3388 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
3393 /* Set RX buffer size */
3394 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3395 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
3396 for (i = 0 ; i < nb_tcs; i++) {
3397 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3399 /* zero alloc all unused TCs */
3400 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3401 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3405 /* Only support an equally distributed Tx packet buffer strategy. */
3406 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
3407 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
3408 for (i = 0; i < nb_tcs; i++) {
3409 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3410 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3412 /* Clear unused TCs, if any, to zero buffer size*/
3413 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3414 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3415 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3419 /*Calculates traffic class credits*/
3420 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3421 IXGBE_DCB_TX_CONFIG);
3422 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3423 IXGBE_DCB_RX_CONFIG);
3426 /* Unpack CEE standard containers */
3427 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
3428 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3429 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3430 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3431 /* Configure PG(ETS) RX */
3432 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3436 /* Unpack CEE standard containers */
3437 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3438 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3439 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3440 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3441 /* Configure PG(ETS) TX */
3442 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3445 /*Configure queue statistics registers*/
3446 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3448 /* Check if the PFC is supported */
3449 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3450 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3451 for (i = 0; i < nb_tcs; i++) {
3453 * If the TC count is 8,and the default high_water is 48,
3454 * the low_water is 16 as default.
3456 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3457 hw->fc.low_water[i] = pbsize / 4;
3458 /* Enable pfc for this TC */
3459 tc = &dcb_config->tc_config[i];
3460 tc->pfc = ixgbe_dcb_pfc_enabled;
3462 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3463 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3465 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3472 * ixgbe_configure_dcb - Configure DCB Hardware
3473 * @dev: pointer to rte_eth_dev
3475 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3477 struct ixgbe_dcb_config *dcb_cfg =
3478 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3479 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3481 PMD_INIT_FUNC_TRACE();
3483 /* check support mq_mode for DCB */
3484 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3485 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3488 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3491 /** Configure DCB hardware **/
3492 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3498 * VMDq only support for 10 GbE NIC.
3501 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3503 struct rte_eth_vmdq_rx_conf *cfg;
3504 struct ixgbe_hw *hw;
3505 enum rte_eth_nb_pools num_pools;
3506 uint32_t mrqc, vt_ctl, vlanctrl;
3510 PMD_INIT_FUNC_TRACE();
3511 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3512 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3513 num_pools = cfg->nb_queue_pools;
3515 ixgbe_rss_disable(dev);
3517 /* MRQC: enable vmdq */
3518 mrqc = IXGBE_MRQC_VMDQEN;
3519 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3521 /* PFVTCTL: turn on virtualisation and set the default pool */
3522 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3523 if (cfg->enable_default_pool)
3524 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3526 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3528 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3530 for (i = 0; i < (int)num_pools; i++) {
3531 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
3532 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
3535 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3536 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3537 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3538 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3540 /* VFTA - enable all vlan filters */
3541 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3542 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3544 /* VFRE: pool enabling for receive - 64 */
3545 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3546 if (num_pools == ETH_64_POOLS)
3547 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3550 * MPSAR - allow pools to read specific mac addresses
3551 * In this case, all pools should be able to read from mac addr 0
3553 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3554 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3556 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3557 for (i = 0; i < cfg->nb_pool_maps; i++) {
3558 /* set vlan id in VF register and set the valid bit */
3559 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3560 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3562 * Put the allowed pools in VFB reg. As we only have 16 or 64
3563 * pools, we only need to use the first half of the register
3566 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3567 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3568 (cfg->pool_map[i].pools & UINT32_MAX));
3570 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3571 ((cfg->pool_map[i].pools >> 32) \
3576 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3577 if (cfg->enable_loop_back) {
3578 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3579 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3580 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3583 IXGBE_WRITE_FLUSH(hw);
3587 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3588 * @hw: pointer to hardware structure
3591 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3596 PMD_INIT_FUNC_TRACE();
3597 /*PF VF Transmit Enable*/
3598 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3599 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3601 /* Disable the Tx desc arbiter so that MTQC can be changed */
3602 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3603 reg |= IXGBE_RTTDCS_ARBDIS;
3604 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3606 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3607 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3609 /* Disable drop for all queues */
3610 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3611 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3612 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3614 /* Enable the Tx desc arbiter */
3615 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3616 reg &= ~IXGBE_RTTDCS_ARBDIS;
3617 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3619 IXGBE_WRITE_FLUSH(hw);
3624 static int __attribute__((cold))
3625 ixgbe_alloc_rx_queue_mbufs(struct ixgbe_rx_queue *rxq)
3627 struct ixgbe_rx_entry *rxe = rxq->sw_ring;
3631 /* Initialize software ring entries */
3632 for (i = 0; i < rxq->nb_rx_desc; i++) {
3633 volatile union ixgbe_adv_rx_desc *rxd;
3634 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3636 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
3637 (unsigned) rxq->queue_id);
3641 rte_mbuf_refcnt_set(mbuf, 1);
3643 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
3645 mbuf->port = rxq->port_id;
3648 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3649 rxd = &rxq->rx_ring[i];
3650 rxd->read.hdr_addr = dma_addr;
3651 rxd->read.pkt_addr = dma_addr;
3659 ixgbe_config_vf_rss(struct rte_eth_dev *dev)
3661 struct ixgbe_hw *hw;
3664 ixgbe_rss_configure(dev);
3666 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3668 /* MRQC: enable VF RSS */
3669 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
3670 mrqc &= ~IXGBE_MRQC_MRQE_MASK;
3671 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3673 mrqc |= IXGBE_MRQC_VMDQRSS64EN;
3677 mrqc |= IXGBE_MRQC_VMDQRSS32EN;
3681 PMD_INIT_LOG(ERR, "Invalid pool number in IOV mode with VMDQ RSS");
3685 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3691 ixgbe_config_vf_default(struct rte_eth_dev *dev)
3693 struct ixgbe_hw *hw =
3694 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3696 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3698 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3703 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3704 IXGBE_MRQC_VMDQRT4TCEN);
3708 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3709 IXGBE_MRQC_VMDQRT8TCEN);
3713 "invalid pool number in IOV mode");
3720 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3722 struct ixgbe_hw *hw =
3723 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3725 if (hw->mac.type == ixgbe_mac_82598EB)
3728 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3730 * SRIOV inactive scheme
3731 * any DCB/RSS w/o VMDq multi-queue setting
3733 switch (dev->data->dev_conf.rxmode.mq_mode) {
3735 ixgbe_rss_configure(dev);
3738 case ETH_MQ_RX_VMDQ_DCB:
3739 ixgbe_vmdq_dcb_configure(dev);
3742 case ETH_MQ_RX_VMDQ_ONLY:
3743 ixgbe_vmdq_rx_hw_configure(dev);
3746 case ETH_MQ_RX_NONE:
3747 /* if mq_mode is none, disable rss mode.*/
3748 default: ixgbe_rss_disable(dev);
3752 * SRIOV active scheme
3753 * Support RSS together with VMDq & SRIOV
3755 switch (dev->data->dev_conf.rxmode.mq_mode) {
3757 case ETH_MQ_RX_VMDQ_RSS:
3758 ixgbe_config_vf_rss(dev);
3761 /* FIXME if support DCB/RSS together with VMDq & SRIOV */
3762 case ETH_MQ_RX_VMDQ_DCB:
3763 case ETH_MQ_RX_VMDQ_DCB_RSS:
3765 "Could not support DCB with VMDq & SRIOV");
3768 ixgbe_config_vf_default(dev);
3777 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3779 struct ixgbe_hw *hw =
3780 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3784 if (hw->mac.type == ixgbe_mac_82598EB)
3787 /* disable arbiter before setting MTQC */
3788 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3789 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3790 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3792 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3794 * SRIOV inactive scheme
3795 * any DCB w/o VMDq multi-queue setting
3797 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3798 ixgbe_vmdq_tx_hw_configure(hw);
3800 mtqc = IXGBE_MTQC_64Q_1PB;
3801 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3804 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3807 * SRIOV active scheme
3808 * FIXME if support DCB together with VMDq & SRIOV
3811 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3814 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3817 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3821 mtqc = IXGBE_MTQC_64Q_1PB;
3822 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
3824 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3827 /* re-enable arbiter */
3828 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3829 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3835 * ixgbe_get_rscctl_maxdesc - Calculate the RSCCTL[n].MAXDESC for PF
3837 * Return the RSCCTL[n].MAXDESC for 82599 and x540 PF devices according to the
3838 * spec rev. 3.0 chapter 8.2.3.8.13.
3840 * @pool Memory pool of the Rx queue
3842 static inline uint32_t
3843 ixgbe_get_rscctl_maxdesc(struct rte_mempool *pool)
3845 struct rte_pktmbuf_pool_private *mp_priv = rte_mempool_get_priv(pool);
3847 /* MAXDESC * SRRCTL.BSIZEPKT must not exceed 64 KB minus one */
3850 (mp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM);
3853 return IXGBE_RSCCTL_MAXDESC_16;
3854 else if (maxdesc >= 8)
3855 return IXGBE_RSCCTL_MAXDESC_8;
3856 else if (maxdesc >= 4)
3857 return IXGBE_RSCCTL_MAXDESC_4;
3859 return IXGBE_RSCCTL_MAXDESC_1;
3863 * ixgbe_set_ivar - Setup the correct IVAR register for a particular MSIX
3866 * (Taken from FreeBSD tree)
3867 * (yes this is all very magic and confusing :)
3870 * @entry the register array entry
3871 * @vector the MSIX vector for this queue
3875 ixgbe_set_ivar(struct rte_eth_dev *dev, u8 entry, u8 vector, s8 type)
3877 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3880 vector |= IXGBE_IVAR_ALLOC_VAL;
3882 switch (hw->mac.type) {
3884 case ixgbe_mac_82598EB:
3886 entry = IXGBE_IVAR_OTHER_CAUSES_INDEX;
3888 entry += (type * 64);
3889 index = (entry >> 2) & 0x1F;
3890 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
3891 ivar &= ~(0xFF << (8 * (entry & 0x3)));
3892 ivar |= (vector << (8 * (entry & 0x3)));
3893 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
3896 case ixgbe_mac_82599EB:
3897 case ixgbe_mac_X540:
3898 if (type == -1) { /* MISC IVAR */
3899 index = (entry & 1) * 8;
3900 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
3901 ivar &= ~(0xFF << index);
3902 ivar |= (vector << index);
3903 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
3904 } else { /* RX/TX IVARS */
3905 index = (16 * (entry & 1)) + (8 * type);
3906 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1));
3907 ivar &= ~(0xFF << index);
3908 ivar |= (vector << index);
3909 IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar);
3919 void __attribute__((cold))
3920 ixgbe_set_rx_function(struct rte_eth_dev *dev)
3922 uint16_t i, rx_using_sse;
3923 struct ixgbe_adapter *adapter =
3924 (struct ixgbe_adapter *)dev->data->dev_private;
3927 * In order to allow Vector Rx there are a few configuration
3928 * conditions to be met and Rx Bulk Allocation should be allowed.
3930 if (ixgbe_rx_vec_dev_conf_condition_check(dev) ||
3931 !adapter->rx_bulk_alloc_allowed) {
3932 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx "
3933 "preconditions or RTE_IXGBE_INC_VECTOR is "
3935 dev->data->port_id);
3937 adapter->rx_vec_allowed = false;
3941 * Initialize the appropriate LRO callback.
3943 * If all queues satisfy the bulk allocation preconditions
3944 * (hw->rx_bulk_alloc_allowed is TRUE) then we may use bulk allocation.
3945 * Otherwise use a single allocation version.
3947 if (dev->data->lro) {
3948 if (adapter->rx_bulk_alloc_allowed) {
3949 PMD_INIT_LOG(INFO, "LRO is requested. Using a bulk "
3950 "allocation version");
3951 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
3953 PMD_INIT_LOG(INFO, "LRO is requested. Using a single "
3954 "allocation version");
3955 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
3957 } else if (dev->data->scattered_rx) {
3959 * Set the non-LRO scattered callback: there are Vector and
3960 * single allocation versions.
3962 if (adapter->rx_vec_allowed) {
3963 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
3964 "callback (port=%d).",
3965 dev->data->port_id);
3967 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3968 } else if (adapter->rx_bulk_alloc_allowed) {
3969 PMD_INIT_LOG(INFO, "Using a Scattered with bulk "
3970 "allocation callback (port=%d).",
3971 dev->data->port_id);
3972 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
3974 PMD_INIT_LOG(DEBUG, "Using Regualr (non-vector, "
3975 "single allocation) "
3976 "Scattered Rx callback "
3978 dev->data->port_id);
3980 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
3983 * Below we set "simple" callbacks according to port/queues parameters.
3984 * If parameters allow we are going to choose between the following
3988 * - Single buffer allocation (the simplest one)
3990 } else if (adapter->rx_vec_allowed) {
3991 PMD_INIT_LOG(INFO, "Vector rx enabled, please make sure RX "
3992 "burst size no less than 32.");
3994 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
3995 } else if (adapter->rx_bulk_alloc_allowed) {
3996 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3997 "satisfied. Rx Burst Bulk Alloc function "
3998 "will be used on port=%d.",
3999 dev->data->port_id);
4001 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
4003 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
4004 "satisfied, or Scattered Rx is requested "
4006 dev->data->port_id);
4008 dev->rx_pkt_burst = ixgbe_recv_pkts;
4011 /* Propagate information about RX function choice through all queues. */
4014 (dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec ||
4015 dev->rx_pkt_burst == ixgbe_recv_pkts_vec);
4017 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4018 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4019 rxq->rx_using_sse = rx_using_sse;
4024 * ixgbe_set_rsc - configure RSC related port HW registers
4026 * Configures the port's RSC related registers according to the 4.6.7.2 chapter
4027 * of 82599 Spec (x540 configuration is virtually the same).
4031 * Returns 0 in case of success or a non-zero error code
4034 ixgbe_set_rsc(struct rte_eth_dev *dev)
4036 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4037 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4038 struct rte_eth_dev_info dev_info = { 0 };
4039 bool rsc_capable = false;
4044 dev->dev_ops->dev_infos_get(dev, &dev_info);
4045 if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_TCP_LRO)
4048 if (!rsc_capable && rx_conf->enable_lro) {
4049 PMD_INIT_LOG(CRIT, "LRO is requested on HW that doesn't "
4054 /* RSC global configuration (chapter 4.6.7.2.1 of 82599 Spec) */
4056 if (!rx_conf->hw_strip_crc && rx_conf->enable_lro) {
4058 * According to chapter of 4.6.7.2.1 of the Spec Rev.
4059 * 3.0 RSC configuration requires HW CRC stripping being
4060 * enabled. If user requested both HW CRC stripping off
4061 * and RSC on - return an error.
4063 PMD_INIT_LOG(CRIT, "LRO can't be enabled when HW CRC "
4068 /* RFCTL configuration */
4070 uint32_t rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4071 if (rx_conf->enable_lro)
4073 * Since NFS packets coalescing is not supported - clear
4074 * RFCTL.NFSW_DIS and RFCTL.NFSR_DIS when RSC is
4077 rfctl &= ~(IXGBE_RFCTL_RSC_DIS | IXGBE_RFCTL_NFSW_DIS |
4078 IXGBE_RFCTL_NFSR_DIS);
4080 rfctl |= IXGBE_RFCTL_RSC_DIS;
4082 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4085 /* If LRO hasn't been requested - we are done here. */
4086 if (!rx_conf->enable_lro)
4089 /* Set RDRXCTL.RSCACKC bit */
4090 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4091 rdrxctl |= IXGBE_RDRXCTL_RSCACKC;
4092 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4094 /* Per-queue RSC configuration (chapter 4.6.7.2.2 of 82599 Spec) */
4095 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4096 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4098 IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxq->reg_idx));
4100 IXGBE_READ_REG(hw, IXGBE_RSCCTL(rxq->reg_idx));
4102 IXGBE_READ_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx));
4104 IXGBE_READ_REG(hw, IXGBE_EITR(rxq->reg_idx));
4107 * ixgbe PMD doesn't support header-split at the moment.
4109 * Following the 4.6.7.2.1 chapter of the 82599/x540
4110 * Spec if RSC is enabled the SRRCTL[n].BSIZEHEADER
4111 * should be configured even if header split is not
4112 * enabled. We will configure it 128 bytes following the
4113 * recommendation in the spec.
4115 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
4116 srrctl |= (128 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4117 IXGBE_SRRCTL_BSIZEHDR_MASK;
4120 * TODO: Consider setting the Receive Descriptor Minimum
4121 * Threshold Size for an RSC case. This is not an obviously
4122 * beneficiary option but the one worth considering...
4125 rscctl |= IXGBE_RSCCTL_RSCEN;
4126 rscctl |= ixgbe_get_rscctl_maxdesc(rxq->mb_pool);
4127 psrtype |= IXGBE_PSRTYPE_TCPHDR;
4130 * RSC: Set ITR interval corresponding to 2K ints/s.
4132 * Full-sized RSC aggregations for a 10Gb/s link will
4133 * arrive at about 20K aggregation/s rate.
4135 * 2K inst/s rate will make only 10% of the
4136 * aggregations to be closed due to the interrupt timer
4137 * expiration for a streaming at wire-speed case.
4139 * For a sparse streaming case this setting will yield
4140 * at most 500us latency for a single RSC aggregation.
4142 eitr &= ~IXGBE_EITR_ITR_INT_MASK;
4143 eitr |= IXGBE_EITR_INTERVAL_US(500) | IXGBE_EITR_CNT_WDIS;
4145 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4146 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(rxq->reg_idx), rscctl);
4147 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
4148 IXGBE_WRITE_REG(hw, IXGBE_EITR(rxq->reg_idx), eitr);
4151 * RSC requires the mapping of the queue to the
4154 ixgbe_set_ivar(dev, rxq->reg_idx, i, 0);
4159 PMD_INIT_LOG(INFO, "enabling LRO mode");
4165 * Initializes Receive Unit.
4167 int __attribute__((cold))
4168 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
4170 struct ixgbe_hw *hw;
4171 struct ixgbe_rx_queue *rxq;
4182 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4185 PMD_INIT_FUNC_TRACE();
4186 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4189 * Make sure receives are disabled while setting
4190 * up the RX context (registers, descriptor rings, etc.).
4192 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4193 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4195 /* Enable receipt of broadcasted frames */
4196 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4197 fctrl |= IXGBE_FCTRL_BAM;
4198 fctrl |= IXGBE_FCTRL_DPF;
4199 fctrl |= IXGBE_FCTRL_PMCF;
4200 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4203 * Configure CRC stripping, if any.
4205 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4206 if (rx_conf->hw_strip_crc)
4207 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
4209 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
4212 * Configure jumbo frame support, if any.
4214 if (rx_conf->jumbo_frame == 1) {
4215 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4216 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4217 maxfrs &= 0x0000FFFF;
4218 maxfrs |= (rx_conf->max_rx_pkt_len << 16);
4219 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4221 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4224 * If loopback mode is configured for 82599, set LPBK bit.
4226 if (hw->mac.type == ixgbe_mac_82599EB &&
4227 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
4228 hlreg0 |= IXGBE_HLREG0_LPBK;
4230 hlreg0 &= ~IXGBE_HLREG0_LPBK;
4232 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4234 /* Setup RX queues */
4235 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4236 rxq = dev->data->rx_queues[i];
4239 * Reset crc_len in case it was changed after queue setup by a
4240 * call to configure.
4242 rxq->crc_len = rx_conf->hw_strip_crc ? 0 : ETHER_CRC_LEN;
4244 /* Setup the Base and Length of the Rx Descriptor Rings */
4245 bus_addr = rxq->rx_ring_phys_addr;
4246 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
4247 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4248 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
4249 (uint32_t)(bus_addr >> 32));
4250 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
4251 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4252 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
4253 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
4255 /* Configure the SRRCTL register */
4256 #ifdef RTE_HEADER_SPLIT_ENABLE
4258 * Configure Header Split
4260 if (rx_conf->header_split) {
4261 if (hw->mac.type == ixgbe_mac_82599EB) {
4262 /* Must setup the PSRTYPE register */
4264 psrtype = IXGBE_PSRTYPE_TCPHDR |
4265 IXGBE_PSRTYPE_UDPHDR |
4266 IXGBE_PSRTYPE_IPV4HDR |
4267 IXGBE_PSRTYPE_IPV6HDR;
4268 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
4270 srrctl = ((rx_conf->split_hdr_size <<
4271 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4272 IXGBE_SRRCTL_BSIZEHDR_MASK);
4273 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4276 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4278 /* Set if packets are dropped when no descriptors available */
4280 srrctl |= IXGBE_SRRCTL_DROP_EN;
4283 * Configure the RX buffer size in the BSIZEPACKET field of
4284 * the SRRCTL register of the queue.
4285 * The value is in 1 KB resolution. Valid values can be from
4288 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
4289 RTE_PKTMBUF_HEADROOM);
4290 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4291 IXGBE_SRRCTL_BSIZEPKT_MASK);
4293 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4295 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4296 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4298 /* It adds dual VLAN length for supporting dual VLAN */
4299 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4300 2 * IXGBE_VLAN_TAG_SIZE > buf_size)
4301 dev->data->scattered_rx = 1;
4304 if (rx_conf->enable_scatter)
4305 dev->data->scattered_rx = 1;
4308 * Device configured with multiple RX queues.
4310 ixgbe_dev_mq_rx_configure(dev);
4313 * Setup the Checksum Register.
4314 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
4315 * Enable IP/L4 checkum computation by hardware if requested to do so.
4317 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
4318 rxcsum |= IXGBE_RXCSUM_PCSD;
4319 if (rx_conf->hw_ip_checksum)
4320 rxcsum |= IXGBE_RXCSUM_IPPCSE;
4322 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
4324 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
4326 if (hw->mac.type == ixgbe_mac_82599EB ||
4327 hw->mac.type == ixgbe_mac_X540) {
4328 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4329 if (rx_conf->hw_strip_crc)
4330 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4332 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
4333 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4334 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4337 rc = ixgbe_set_rsc(dev);
4341 ixgbe_set_rx_function(dev);
4347 * Initializes Transmit Unit.
4349 void __attribute__((cold))
4350 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
4352 struct ixgbe_hw *hw;
4353 struct ixgbe_tx_queue *txq;
4359 PMD_INIT_FUNC_TRACE();
4360 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4362 /* Enable TX CRC (checksum offload requirement) and hw padding
4363 * (TSO requirement) */
4364 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4365 hlreg0 |= (IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);
4366 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4368 /* Setup the Base and Length of the Tx Descriptor Rings */
4369 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4370 txq = dev->data->tx_queues[i];
4372 bus_addr = txq->tx_ring_phys_addr;
4373 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
4374 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4375 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
4376 (uint32_t)(bus_addr >> 32));
4377 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
4378 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4379 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4380 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
4381 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
4384 * Disable Tx Head Writeback RO bit, since this hoses
4385 * bookkeeping if things aren't delivered in order.
4387 switch (hw->mac.type) {
4388 case ixgbe_mac_82598EB:
4389 txctrl = IXGBE_READ_REG(hw,
4390 IXGBE_DCA_TXCTRL(txq->reg_idx));
4391 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4392 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
4396 case ixgbe_mac_82599EB:
4397 case ixgbe_mac_X540:
4398 case ixgbe_mac_X550:
4399 case ixgbe_mac_X550EM_x:
4401 txctrl = IXGBE_READ_REG(hw,
4402 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
4403 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4404 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
4410 /* Device configured with multiple TX queues. */
4411 ixgbe_dev_mq_tx_configure(dev);
4415 * Set up link for 82599 loopback mode Tx->Rx.
4417 static inline void __attribute__((cold))
4418 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
4420 PMD_INIT_FUNC_TRACE();
4422 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
4423 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
4425 PMD_INIT_LOG(ERR, "Could not enable loopback mode");
4434 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
4435 ixgbe_reset_pipeline_82599(hw);
4437 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
4443 * Start Transmit and Receive Units.
4445 int __attribute__((cold))
4446 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
4448 struct ixgbe_hw *hw;
4449 struct ixgbe_tx_queue *txq;
4450 struct ixgbe_rx_queue *rxq;
4457 PMD_INIT_FUNC_TRACE();
4458 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4460 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4461 txq = dev->data->tx_queues[i];
4462 /* Setup Transmit Threshold Registers */
4463 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4464 txdctl |= txq->pthresh & 0x7F;
4465 txdctl |= ((txq->hthresh & 0x7F) << 8);
4466 txdctl |= ((txq->wthresh & 0x7F) << 16);
4467 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4470 if (hw->mac.type != ixgbe_mac_82598EB) {
4471 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
4472 dmatxctl |= IXGBE_DMATXCTL_TE;
4473 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
4476 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4477 txq = dev->data->tx_queues[i];
4478 if (!txq->tx_deferred_start) {
4479 ret = ixgbe_dev_tx_queue_start(dev, i);
4485 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4486 rxq = dev->data->rx_queues[i];
4487 if (!rxq->rx_deferred_start) {
4488 ret = ixgbe_dev_rx_queue_start(dev, i);
4494 /* Enable Receive engine */
4495 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4496 if (hw->mac.type == ixgbe_mac_82598EB)
4497 rxctrl |= IXGBE_RXCTRL_DMBYPS;
4498 rxctrl |= IXGBE_RXCTRL_RXEN;
4499 hw->mac.ops.enable_rx_dma(hw, rxctrl);
4501 /* If loopback mode is enabled for 82599, set up the link accordingly */
4502 if (hw->mac.type == ixgbe_mac_82599EB &&
4503 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
4504 ixgbe_setup_loopback_link_82599(hw);
4510 * Start Receive Units for specified queue.
4512 int __attribute__((cold))
4513 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4515 struct ixgbe_hw *hw;
4516 struct ixgbe_rx_queue *rxq;
4520 PMD_INIT_FUNC_TRACE();
4521 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4523 if (rx_queue_id < dev->data->nb_rx_queues) {
4524 rxq = dev->data->rx_queues[rx_queue_id];
4526 /* Allocate buffers for descriptor rings */
4527 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
4528 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
4532 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4533 rxdctl |= IXGBE_RXDCTL_ENABLE;
4534 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
4536 /* Wait until RX Enable ready */
4537 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4540 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4541 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4543 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d",
4546 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
4547 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
4555 * Stop Receive Units for specified queue.
4557 int __attribute__((cold))
4558 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4560 struct ixgbe_hw *hw;
4561 struct ixgbe_adapter *adapter =
4562 (struct ixgbe_adapter *)dev->data->dev_private;
4563 struct ixgbe_rx_queue *rxq;
4567 PMD_INIT_FUNC_TRACE();
4568 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4570 if (rx_queue_id < dev->data->nb_rx_queues) {
4571 rxq = dev->data->rx_queues[rx_queue_id];
4573 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4574 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
4575 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
4577 /* Wait until RX Enable ready */
4578 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4581 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4582 } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));
4584 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d",
4587 rte_delay_us(RTE_IXGBE_WAIT_100_US);
4589 ixgbe_rx_queue_release_mbufs(rxq);
4590 ixgbe_reset_rx_queue(adapter, rxq);
4599 * Start Transmit Units for specified queue.
4601 int __attribute__((cold))
4602 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4604 struct ixgbe_hw *hw;
4605 struct ixgbe_tx_queue *txq;
4609 PMD_INIT_FUNC_TRACE();
4610 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4612 if (tx_queue_id < dev->data->nb_tx_queues) {
4613 txq = dev->data->tx_queues[tx_queue_id];
4614 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4615 txdctl |= IXGBE_TXDCTL_ENABLE;
4616 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4618 /* Wait until TX Enable ready */
4619 if (hw->mac.type == ixgbe_mac_82599EB) {
4620 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4623 txdctl = IXGBE_READ_REG(hw,
4624 IXGBE_TXDCTL(txq->reg_idx));
4625 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4627 PMD_INIT_LOG(ERR, "Could not enable "
4628 "Tx Queue %d", tx_queue_id);
4631 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
4632 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
4640 * Stop Transmit Units for specified queue.
4642 int __attribute__((cold))
4643 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4645 struct ixgbe_hw *hw;
4646 struct ixgbe_tx_queue *txq;
4648 uint32_t txtdh, txtdt;
4651 PMD_INIT_FUNC_TRACE();
4652 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4654 if (tx_queue_id < dev->data->nb_tx_queues) {
4655 txq = dev->data->tx_queues[tx_queue_id];
4657 /* Wait until TX queue is empty */
4658 if (hw->mac.type == ixgbe_mac_82599EB) {
4659 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4661 rte_delay_us(RTE_IXGBE_WAIT_100_US);
4662 txtdh = IXGBE_READ_REG(hw,
4663 IXGBE_TDH(txq->reg_idx));
4664 txtdt = IXGBE_READ_REG(hw,
4665 IXGBE_TDT(txq->reg_idx));
4666 } while (--poll_ms && (txtdh != txtdt));
4668 PMD_INIT_LOG(ERR, "Tx Queue %d is not empty "
4669 "when stopping.", tx_queue_id);
4672 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4673 txdctl &= ~IXGBE_TXDCTL_ENABLE;
4674 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4676 /* Wait until TX Enable ready */
4677 if (hw->mac.type == ixgbe_mac_82599EB) {
4678 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4681 txdctl = IXGBE_READ_REG(hw,
4682 IXGBE_TXDCTL(txq->reg_idx));
4683 } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));
4685 PMD_INIT_LOG(ERR, "Could not disable "
4686 "Tx Queue %d", tx_queue_id);
4689 if (txq->ops != NULL) {
4690 txq->ops->release_mbufs(txq);
4691 txq->ops->reset(txq);
4700 * [VF] Initializes Receive Unit.
4702 int __attribute__((cold))
4703 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
4705 struct ixgbe_hw *hw;
4706 struct ixgbe_rx_queue *rxq;
4708 uint32_t srrctl, psrtype = 0;
4713 PMD_INIT_FUNC_TRACE();
4714 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4716 if (rte_is_power_of_2(dev->data->nb_rx_queues) == 0) {
4717 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4718 "it should be power of 2");
4722 if (dev->data->nb_rx_queues > hw->mac.max_rx_queues) {
4723 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4724 "it should be equal to or less than %d",
4725 hw->mac.max_rx_queues);
4730 * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
4731 * disables the VF receipt of packets if the PF MTU is > 1500.
4732 * This is done to deal with 82599 limitations that imposes
4733 * the PF and all VFs to share the same MTU.
4734 * Then, the PF driver enables again the VF receipt of packet when
4735 * the VF driver issues a IXGBE_VF_SET_LPE request.
4736 * In the meantime, the VF device cannot be used, even if the VF driver
4737 * and the Guest VM network stack are ready to accept packets with a
4738 * size up to the PF MTU.
4739 * As a work-around to this PF behaviour, force the call to
4740 * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
4741 * VF packets received can work in all cases.
4743 ixgbevf_rlpml_set_vf(hw,
4744 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
4746 /* Setup RX queues */
4747 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4748 rxq = dev->data->rx_queues[i];
4750 /* Allocate buffers for descriptor rings */
4751 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
4755 /* Setup the Base and Length of the Rx Descriptor Rings */
4756 bus_addr = rxq->rx_ring_phys_addr;
4758 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
4759 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4760 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
4761 (uint32_t)(bus_addr >> 32));
4762 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
4763 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4764 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
4765 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
4768 /* Configure the SRRCTL register */
4769 #ifdef RTE_HEADER_SPLIT_ENABLE
4771 * Configure Header Split
4773 if (dev->data->dev_conf.rxmode.header_split) {
4774 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
4775 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4776 IXGBE_SRRCTL_BSIZEHDR_MASK);
4777 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4780 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4782 /* Set if packets are dropped when no descriptors available */
4784 srrctl |= IXGBE_SRRCTL_DROP_EN;
4787 * Configure the RX buffer size in the BSIZEPACKET field of
4788 * the SRRCTL register of the queue.
4789 * The value is in 1 KB resolution. Valid values can be from
4792 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
4793 RTE_PKTMBUF_HEADROOM);
4794 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4795 IXGBE_SRRCTL_BSIZEPKT_MASK);
4798 * VF modification to write virtual function SRRCTL register
4800 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
4802 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4803 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4805 if (dev->data->dev_conf.rxmode.enable_scatter ||
4806 /* It adds dual VLAN length for supporting dual VLAN */
4807 (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4808 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
4809 if (!dev->data->scattered_rx)
4810 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
4811 dev->data->scattered_rx = 1;
4815 #ifdef RTE_HEADER_SPLIT_ENABLE
4816 if (dev->data->dev_conf.rxmode.header_split)
4817 /* Must setup the PSRTYPE register */
4818 psrtype = IXGBE_PSRTYPE_TCPHDR |
4819 IXGBE_PSRTYPE_UDPHDR |
4820 IXGBE_PSRTYPE_IPV4HDR |
4821 IXGBE_PSRTYPE_IPV6HDR;
4824 /* Set RQPL for VF RSS according to max Rx queue */
4825 psrtype |= (dev->data->nb_rx_queues >> 1) <<
4826 IXGBE_PSRTYPE_RQPL_SHIFT;
4827 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
4829 ixgbe_set_rx_function(dev);
4835 * [VF] Initializes Transmit Unit.
4837 void __attribute__((cold))
4838 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
4840 struct ixgbe_hw *hw;
4841 struct ixgbe_tx_queue *txq;
4846 PMD_INIT_FUNC_TRACE();
4847 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4849 /* Setup the Base and Length of the Tx Descriptor Rings */
4850 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4851 txq = dev->data->tx_queues[i];
4852 bus_addr = txq->tx_ring_phys_addr;
4853 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
4854 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4855 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
4856 (uint32_t)(bus_addr >> 32));
4857 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
4858 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4859 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4860 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
4861 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
4864 * Disable Tx Head Writeback RO bit, since this hoses
4865 * bookkeeping if things aren't delivered in order.
4867 txctrl = IXGBE_READ_REG(hw,
4868 IXGBE_VFDCA_TXCTRL(i));
4869 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4870 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
4876 * [VF] Start Transmit and Receive Units.
4878 void __attribute__((cold))
4879 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
4881 struct ixgbe_hw *hw;
4882 struct ixgbe_tx_queue *txq;
4883 struct ixgbe_rx_queue *rxq;
4889 PMD_INIT_FUNC_TRACE();
4890 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4892 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4893 txq = dev->data->tx_queues[i];
4894 /* Setup Transmit Threshold Registers */
4895 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4896 txdctl |= txq->pthresh & 0x7F;
4897 txdctl |= ((txq->hthresh & 0x7F) << 8);
4898 txdctl |= ((txq->wthresh & 0x7F) << 16);
4899 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4902 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4904 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4905 txdctl |= IXGBE_TXDCTL_ENABLE;
4906 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4909 /* Wait until TX Enable ready */
4912 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4913 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4915 PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
4917 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4919 rxq = dev->data->rx_queues[i];
4921 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4922 rxdctl |= IXGBE_RXDCTL_ENABLE;
4923 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
4925 /* Wait until RX Enable ready */
4929 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4930 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4932 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
4934 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);
4939 /* Stubs needed for linkage when CONFIG_RTE_IXGBE_INC_VECTOR is set to 'n' */
4940 int __attribute__((weak))
4941 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
4946 uint16_t __attribute__((weak))
4947 ixgbe_recv_pkts_vec(
4948 void __rte_unused *rx_queue,
4949 struct rte_mbuf __rte_unused **rx_pkts,
4950 uint16_t __rte_unused nb_pkts)
4955 uint16_t __attribute__((weak))
4956 ixgbe_recv_scattered_pkts_vec(
4957 void __rte_unused *rx_queue,
4958 struct rte_mbuf __rte_unused **rx_pkts,
4959 uint16_t __rte_unused nb_pkts)
4964 int __attribute__((weak))
4965 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue __rte_unused *rxq)