4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5 * Copyright 2014 6WIND S.A.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
18 * * Neither the name of Intel Corporation nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/queue.h>
46 #include <rte_byteorder.h>
47 #include <rte_common.h>
48 #include <rte_cycles.h>
50 #include <rte_debug.h>
51 #include <rte_interrupts.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_launch.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
75 #include "ixgbe_logs.h"
76 #include "base/ixgbe_api.h"
77 #include "base/ixgbe_vf.h"
78 #include "ixgbe_ethdev.h"
79 #include "base/ixgbe_dcb.h"
80 #include "base/ixgbe_common.h"
81 #include "ixgbe_rxtx.h"
83 /* Bit Mask to indicate what bits required for building TX context */
84 #define IXGBE_TX_OFFLOAD_MASK ( \
90 static inline struct rte_mbuf *
91 rte_rxmbuf_alloc(struct rte_mempool *mp)
95 m = __rte_mbuf_raw_alloc(mp);
96 __rte_mbuf_sanity_check_raw(m, 0);
102 #define RTE_PMD_USE_PREFETCH
105 #ifdef RTE_PMD_USE_PREFETCH
107 * Prefetch a cache line into all cache levels.
109 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
111 #define rte_ixgbe_prefetch(p) do {} while(0)
114 /*********************************************************************
118 **********************************************************************/
121 * Check for descriptors with their DD bit set and free mbufs.
122 * Return the total number of buffers freed.
124 static inline int __attribute__((always_inline))
125 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
127 struct ixgbe_tx_entry *txep;
131 /* check DD bit on threshold descriptor */
132 status = txq->tx_ring[txq->tx_next_dd].wb.status;
133 if (!(status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD)))
137 * first buffer to free from S/W ring is at index
138 * tx_next_dd - (tx_rs_thresh-1)
140 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
142 /* free buffers one at a time */
143 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
144 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
145 txep->mbuf->next = NULL;
146 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
150 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
151 rte_pktmbuf_free_seg(txep->mbuf);
156 /* buffers were freed, update counters */
157 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
158 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
159 if (txq->tx_next_dd >= txq->nb_tx_desc)
160 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
162 return txq->tx_rs_thresh;
165 /* Populate 4 descriptors with data from 4 mbufs */
167 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
169 uint64_t buf_dma_addr;
173 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
174 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
175 pkt_len = (*pkts)->data_len;
177 /* write data to descriptor */
178 txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
180 txdp->read.cmd_type_len =
181 rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
183 txdp->read.olinfo_status =
184 rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
186 rte_prefetch0(&(*pkts)->pool);
190 /* Populate 1 descriptor with data from 1 mbuf */
192 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
194 uint64_t buf_dma_addr;
197 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
198 pkt_len = (*pkts)->data_len;
200 /* write data to descriptor */
201 txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
202 txdp->read.cmd_type_len =
203 rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
204 txdp->read.olinfo_status =
205 rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
206 rte_prefetch0(&(*pkts)->pool);
210 * Fill H/W descriptor ring with mbuf data.
211 * Copy mbuf pointers to the S/W ring.
214 ixgbe_tx_fill_hw_ring(struct ixgbe_tx_queue *txq, struct rte_mbuf **pkts,
217 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
218 struct ixgbe_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
219 const int N_PER_LOOP = 4;
220 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
221 int mainpart, leftover;
225 * Process most of the packets in chunks of N pkts. Any
226 * leftover packets will get processed one at a time.
228 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
229 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
230 for (i = 0; i < mainpart; i += N_PER_LOOP) {
231 /* Copy N mbuf pointers to the S/W ring */
232 for (j = 0; j < N_PER_LOOP; ++j) {
233 (txep + i + j)->mbuf = *(pkts + i + j);
235 tx4(txdp + i, pkts + i);
238 if (unlikely(leftover > 0)) {
239 for (i = 0; i < leftover; ++i) {
240 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
241 tx1(txdp + mainpart + i, pkts + mainpart + i);
246 static inline uint16_t
247 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
250 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
251 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
255 * Begin scanning the H/W ring for done descriptors when the
256 * number of available descriptors drops below tx_free_thresh. For
257 * each done descriptor, free the associated buffer.
259 if (txq->nb_tx_free < txq->tx_free_thresh)
260 ixgbe_tx_free_bufs(txq);
262 /* Only use descriptors that are available */
263 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
264 if (unlikely(nb_pkts == 0))
267 /* Use exactly nb_pkts descriptors */
268 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
271 * At this point, we know there are enough descriptors in the
272 * ring to transmit all the packets. This assumes that each
273 * mbuf contains a single segment, and that no new offloads
274 * are expected, which would require a new context descriptor.
278 * See if we're going to wrap-around. If so, handle the top
279 * of the descriptor ring first, then do the bottom. If not,
280 * the processing looks just like the "bottom" part anyway...
282 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
283 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
284 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
287 * We know that the last descriptor in the ring will need to
288 * have its RS bit set because tx_rs_thresh has to be
289 * a divisor of the ring size
291 tx_r[txq->tx_next_rs].read.cmd_type_len |=
292 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
293 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
298 /* Fill H/W descriptor ring with mbuf data */
299 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
300 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
303 * Determine if RS bit should be set
304 * This is what we actually want:
305 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
306 * but instead of subtracting 1 and doing >=, we can just do
307 * greater than without subtracting.
309 if (txq->tx_tail > txq->tx_next_rs) {
310 tx_r[txq->tx_next_rs].read.cmd_type_len |=
311 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
312 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
314 if (txq->tx_next_rs >= txq->nb_tx_desc)
315 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
319 * Check for wrap-around. This would only happen if we used
320 * up to the last descriptor in the ring, no more, no less.
322 if (txq->tx_tail >= txq->nb_tx_desc)
325 /* update tail pointer */
327 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
333 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
338 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
339 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
340 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
342 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
346 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
347 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
348 nb_tx = (uint16_t)(nb_tx + ret);
349 nb_pkts = (uint16_t)(nb_pkts - ret);
358 ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,
359 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
360 uint64_t ol_flags, union ixgbe_tx_offload tx_offload)
362 uint32_t type_tucmd_mlhl;
363 uint32_t mss_l4len_idx = 0;
365 uint32_t vlan_macip_lens;
366 union ixgbe_tx_offload tx_offload_mask;
368 ctx_idx = txq->ctx_curr;
369 tx_offload_mask.data = 0;
372 /* Specify which HW CTX to upload. */
373 mss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
375 if (ol_flags & PKT_TX_VLAN_PKT) {
376 tx_offload_mask.vlan_tci |= ~0;
379 /* check if TCP segmentation required for this packet */
380 if (ol_flags & PKT_TX_TCP_SEG) {
381 /* implies IP cksum in IPv4 */
382 if (ol_flags & PKT_TX_IP_CKSUM)
383 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |
384 IXGBE_ADVTXD_TUCMD_L4T_TCP |
385 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
387 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV6 |
388 IXGBE_ADVTXD_TUCMD_L4T_TCP |
389 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
391 tx_offload_mask.l2_len |= ~0;
392 tx_offload_mask.l3_len |= ~0;
393 tx_offload_mask.l4_len |= ~0;
394 tx_offload_mask.tso_segsz |= ~0;
395 mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
396 mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;
397 } else { /* no TSO, check if hardware checksum is needed */
398 if (ol_flags & PKT_TX_IP_CKSUM) {
399 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
400 tx_offload_mask.l2_len |= ~0;
401 tx_offload_mask.l3_len |= ~0;
404 switch (ol_flags & PKT_TX_L4_MASK) {
405 case PKT_TX_UDP_CKSUM:
406 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
407 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
408 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
409 tx_offload_mask.l2_len |= ~0;
410 tx_offload_mask.l3_len |= ~0;
412 case PKT_TX_TCP_CKSUM:
413 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
414 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
415 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
416 tx_offload_mask.l2_len |= ~0;
417 tx_offload_mask.l3_len |= ~0;
418 tx_offload_mask.l4_len |= ~0;
420 case PKT_TX_SCTP_CKSUM:
421 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
422 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
423 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
424 tx_offload_mask.l2_len |= ~0;
425 tx_offload_mask.l3_len |= ~0;
428 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
429 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
434 txq->ctx_cache[ctx_idx].flags = ol_flags;
435 txq->ctx_cache[ctx_idx].tx_offload.data =
436 tx_offload_mask.data & tx_offload.data;
437 txq->ctx_cache[ctx_idx].tx_offload_mask = tx_offload_mask;
439 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
440 vlan_macip_lens = tx_offload.l3_len;
441 vlan_macip_lens |= (tx_offload.l2_len << IXGBE_ADVTXD_MACLEN_SHIFT);
442 vlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);
443 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
444 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
445 ctx_txd->seqnum_seed = 0;
449 * Check which hardware context can be used. Use the existing match
450 * or create a new context descriptor.
452 static inline uint32_t
453 what_advctx_update(struct ixgbe_tx_queue *txq, uint64_t flags,
454 union ixgbe_tx_offload tx_offload)
456 /* If match with the current used context */
457 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
458 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
459 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
460 return txq->ctx_curr;
463 /* What if match with the next context */
465 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
466 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
467 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
468 return txq->ctx_curr;
471 /* Mismatch, use the previous context */
472 return (IXGBE_CTX_NUM);
475 static inline uint32_t
476 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
479 if ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM)
480 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
481 if (ol_flags & PKT_TX_IP_CKSUM)
482 tmp |= IXGBE_ADVTXD_POPTS_IXSM;
483 if (ol_flags & PKT_TX_TCP_SEG)
484 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
488 static inline uint32_t
489 tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)
491 uint32_t cmdtype = 0;
492 if (ol_flags & PKT_TX_VLAN_PKT)
493 cmdtype |= IXGBE_ADVTXD_DCMD_VLE;
494 if (ol_flags & PKT_TX_TCP_SEG)
495 cmdtype |= IXGBE_ADVTXD_DCMD_TSE;
499 /* Default RS bit threshold values */
500 #ifndef DEFAULT_TX_RS_THRESH
501 #define DEFAULT_TX_RS_THRESH 32
503 #ifndef DEFAULT_TX_FREE_THRESH
504 #define DEFAULT_TX_FREE_THRESH 32
507 /* Reset transmit descriptors after they have been used */
509 ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)
511 struct ixgbe_tx_entry *sw_ring = txq->sw_ring;
512 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
513 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
514 uint16_t nb_tx_desc = txq->nb_tx_desc;
515 uint16_t desc_to_clean_to;
516 uint16_t nb_tx_to_clean;
519 /* Determine the last descriptor needing to be cleaned */
520 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
521 if (desc_to_clean_to >= nb_tx_desc)
522 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
524 /* Check to make sure the last descriptor to clean is done */
525 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
526 status = txr[desc_to_clean_to].wb.status;
527 if (!(status & rte_cpu_to_le_32(IXGBE_TXD_STAT_DD)))
529 PMD_TX_FREE_LOG(DEBUG,
530 "TX descriptor %4u is not done"
531 "(port=%d queue=%d)",
533 txq->port_id, txq->queue_id);
534 /* Failed to clean any descriptors, better luck next time */
538 /* Figure out how many descriptors will be cleaned */
539 if (last_desc_cleaned > desc_to_clean_to)
540 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
543 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
546 PMD_TX_FREE_LOG(DEBUG,
547 "Cleaning %4u TX descriptors: %4u to %4u "
548 "(port=%d queue=%d)",
549 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
550 txq->port_id, txq->queue_id);
553 * The last descriptor to clean is done, so that means all the
554 * descriptors from the last descriptor that was cleaned
555 * up to the last descriptor with the RS bit set
556 * are done. Only reset the threshold descriptor.
558 txr[desc_to_clean_to].wb.status = 0;
560 /* Update the txq to reflect the last descriptor that was cleaned */
561 txq->last_desc_cleaned = desc_to_clean_to;
562 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
569 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
572 struct ixgbe_tx_queue *txq;
573 struct ixgbe_tx_entry *sw_ring;
574 struct ixgbe_tx_entry *txe, *txn;
575 volatile union ixgbe_adv_tx_desc *txr;
576 volatile union ixgbe_adv_tx_desc *txd;
577 struct rte_mbuf *tx_pkt;
578 struct rte_mbuf *m_seg;
579 uint64_t buf_dma_addr;
580 uint32_t olinfo_status;
581 uint32_t cmd_type_len;
592 union ixgbe_tx_offload tx_offload = {0};
595 sw_ring = txq->sw_ring;
597 tx_id = txq->tx_tail;
598 txe = &sw_ring[tx_id];
600 /* Determine if the descriptor ring needs to be cleaned. */
601 if (txq->nb_tx_free < txq->tx_free_thresh)
602 ixgbe_xmit_cleanup(txq);
604 rte_prefetch0(&txe->mbuf->pool);
607 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
610 pkt_len = tx_pkt->pkt_len;
613 * Determine how many (if any) context descriptors
614 * are needed for offload functionality.
616 ol_flags = tx_pkt->ol_flags;
618 /* If hardware offload required */
619 tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
621 tx_offload.l2_len = tx_pkt->l2_len;
622 tx_offload.l3_len = tx_pkt->l3_len;
623 tx_offload.l4_len = tx_pkt->l4_len;
624 tx_offload.vlan_tci = tx_pkt->vlan_tci;
625 tx_offload.tso_segsz = tx_pkt->tso_segsz;
627 /* If new context need be built or reuse the exist ctx. */
628 ctx = what_advctx_update(txq, tx_ol_req,
630 /* Only allocate context descriptor if required*/
631 new_ctx = (ctx == IXGBE_CTX_NUM);
636 * Keep track of how many descriptors are used this loop
637 * This will always be the number of segments + the number of
638 * Context descriptors required to transmit the packet
640 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
643 * The number of descriptors that must be allocated for a
644 * packet is the number of segments of that packet, plus 1
645 * Context Descriptor for the hardware offload, if any.
646 * Determine the last TX descriptor to allocate in the TX ring
647 * for the packet, starting from the current position (tx_id)
650 tx_last = (uint16_t) (tx_id + nb_used - 1);
653 if (tx_last >= txq->nb_tx_desc)
654 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
656 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
657 " tx_first=%u tx_last=%u",
658 (unsigned) txq->port_id,
659 (unsigned) txq->queue_id,
665 * Make sure there are enough TX descriptors available to
666 * transmit the entire packet.
667 * nb_used better be less than or equal to txq->tx_rs_thresh
669 if (nb_used > txq->nb_tx_free) {
670 PMD_TX_FREE_LOG(DEBUG,
671 "Not enough free TX descriptors "
672 "nb_used=%4u nb_free=%4u "
673 "(port=%d queue=%d)",
674 nb_used, txq->nb_tx_free,
675 txq->port_id, txq->queue_id);
677 if (ixgbe_xmit_cleanup(txq) != 0) {
678 /* Could not clean any descriptors */
684 /* nb_used better be <= txq->tx_rs_thresh */
685 if (unlikely(nb_used > txq->tx_rs_thresh)) {
686 PMD_TX_FREE_LOG(DEBUG,
687 "The number of descriptors needed to "
688 "transmit the packet exceeds the "
689 "RS bit threshold. This will impact "
691 "nb_used=%4u nb_free=%4u "
693 "(port=%d queue=%d)",
694 nb_used, txq->nb_tx_free,
696 txq->port_id, txq->queue_id);
698 * Loop here until there are enough TX
699 * descriptors or until the ring cannot be
702 while (nb_used > txq->nb_tx_free) {
703 if (ixgbe_xmit_cleanup(txq) != 0) {
705 * Could not clean any
717 * By now there are enough free TX descriptors to transmit
722 * Set common flags of all TX Data Descriptors.
724 * The following bits must be set in all Data Descriptors:
725 * - IXGBE_ADVTXD_DTYP_DATA
726 * - IXGBE_ADVTXD_DCMD_DEXT
728 * The following bits must be set in the first Data Descriptor
729 * and are ignored in the other ones:
730 * - IXGBE_ADVTXD_DCMD_IFCS
731 * - IXGBE_ADVTXD_MAC_1588
732 * - IXGBE_ADVTXD_DCMD_VLE
734 * The following bits must only be set in the last Data
736 * - IXGBE_TXD_CMD_EOP
738 * The following bits can be set in any Data Descriptor, but
739 * are only set in the last Data Descriptor:
742 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
743 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
745 #ifdef RTE_LIBRTE_IEEE1588
746 if (ol_flags & PKT_TX_IEEE1588_TMST)
747 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
753 if (ol_flags & PKT_TX_TCP_SEG) {
754 /* when TSO is on, paylen in descriptor is the
755 * not the packet len but the tcp payload len */
756 pkt_len -= (tx_offload.l2_len +
757 tx_offload.l3_len + tx_offload.l4_len);
761 * Setup the TX Advanced Context Descriptor if required
764 volatile struct ixgbe_adv_tx_context_desc *
767 ctx_txd = (volatile struct
768 ixgbe_adv_tx_context_desc *)
771 txn = &sw_ring[txe->next_id];
772 rte_prefetch0(&txn->mbuf->pool);
774 if (txe->mbuf != NULL) {
775 rte_pktmbuf_free_seg(txe->mbuf);
779 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
782 txe->last_id = tx_last;
783 tx_id = txe->next_id;
788 * Setup the TX Advanced Data Descriptor,
789 * This path will go through
790 * whatever new/reuse the context descriptor
792 cmd_type_len |= tx_desc_ol_flags_to_cmdtype(ol_flags);
793 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
794 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
797 olinfo_status |= (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
802 txn = &sw_ring[txe->next_id];
803 rte_prefetch0(&txn->mbuf->pool);
805 if (txe->mbuf != NULL)
806 rte_pktmbuf_free_seg(txe->mbuf);
810 * Set up Transmit Data Descriptor.
812 slen = m_seg->data_len;
813 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
814 txd->read.buffer_addr =
815 rte_cpu_to_le_64(buf_dma_addr);
816 txd->read.cmd_type_len =
817 rte_cpu_to_le_32(cmd_type_len | slen);
818 txd->read.olinfo_status =
819 rte_cpu_to_le_32(olinfo_status);
820 txe->last_id = tx_last;
821 tx_id = txe->next_id;
824 } while (m_seg != NULL);
827 * The last packet data descriptor needs End Of Packet (EOP)
829 cmd_type_len |= IXGBE_TXD_CMD_EOP;
830 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
831 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
833 /* Set RS bit only on threshold packets' last descriptor */
834 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
835 PMD_TX_FREE_LOG(DEBUG,
836 "Setting RS bit on TXD id="
837 "%4u (port=%d queue=%d)",
838 tx_last, txq->port_id, txq->queue_id);
840 cmd_type_len |= IXGBE_TXD_CMD_RS;
842 /* Update txq RS bit counters */
845 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
851 * Set the Transmit Descriptor Tail (TDT)
853 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
854 (unsigned) txq->port_id, (unsigned) txq->queue_id,
855 (unsigned) tx_id, (unsigned) nb_tx);
856 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
857 txq->tx_tail = tx_id;
862 /*********************************************************************
866 **********************************************************************/
867 #define IXGBE_PACKET_TYPE_IPV4 0X01
868 #define IXGBE_PACKET_TYPE_IPV4_TCP 0X11
869 #define IXGBE_PACKET_TYPE_IPV4_UDP 0X21
870 #define IXGBE_PACKET_TYPE_IPV4_SCTP 0X41
871 #define IXGBE_PACKET_TYPE_IPV4_EXT 0X03
872 #define IXGBE_PACKET_TYPE_IPV4_EXT_SCTP 0X43
873 #define IXGBE_PACKET_TYPE_IPV6 0X04
874 #define IXGBE_PACKET_TYPE_IPV6_TCP 0X14
875 #define IXGBE_PACKET_TYPE_IPV6_UDP 0X24
876 #define IXGBE_PACKET_TYPE_IPV6_EXT 0X0C
877 #define IXGBE_PACKET_TYPE_IPV6_EXT_TCP 0X1C
878 #define IXGBE_PACKET_TYPE_IPV6_EXT_UDP 0X2C
879 #define IXGBE_PACKET_TYPE_IPV4_IPV6 0X05
880 #define IXGBE_PACKET_TYPE_IPV4_IPV6_TCP 0X15
881 #define IXGBE_PACKET_TYPE_IPV4_IPV6_UDP 0X25
882 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT 0X0D
883 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP 0X1D
884 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP 0X2D
885 #define IXGBE_PACKET_TYPE_MAX 0X80
886 #define IXGBE_PACKET_TYPE_MASK 0X7F
887 #define IXGBE_PACKET_TYPE_SHIFT 0X04
888 static inline uint32_t
889 ixgbe_rxd_pkt_info_to_pkt_type(uint16_t pkt_info)
891 static const uint32_t
892 ptype_table[IXGBE_PACKET_TYPE_MAX] __rte_cache_aligned = {
893 [IXGBE_PACKET_TYPE_IPV4] = RTE_PTYPE_L2_ETHER |
895 [IXGBE_PACKET_TYPE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
896 RTE_PTYPE_L3_IPV4_EXT,
897 [IXGBE_PACKET_TYPE_IPV6] = RTE_PTYPE_L2_ETHER |
899 [IXGBE_PACKET_TYPE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
900 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
901 RTE_PTYPE_INNER_L3_IPV6,
902 [IXGBE_PACKET_TYPE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
903 RTE_PTYPE_L3_IPV6_EXT,
904 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
905 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
906 RTE_PTYPE_INNER_L3_IPV6_EXT,
907 [IXGBE_PACKET_TYPE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
908 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
909 [IXGBE_PACKET_TYPE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
910 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
911 [IXGBE_PACKET_TYPE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
912 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
913 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
914 [IXGBE_PACKET_TYPE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
915 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,
916 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
917 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
918 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
919 [IXGBE_PACKET_TYPE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
920 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
921 [IXGBE_PACKET_TYPE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
922 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
923 [IXGBE_PACKET_TYPE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
924 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
925 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
926 [IXGBE_PACKET_TYPE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
927 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
928 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
929 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
930 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
931 [IXGBE_PACKET_TYPE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
932 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP,
933 [IXGBE_PACKET_TYPE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
934 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_SCTP,
936 if (unlikely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
937 return RTE_PTYPE_UNKNOWN;
939 pkt_info = (pkt_info >> IXGBE_PACKET_TYPE_SHIFT) &
940 IXGBE_PACKET_TYPE_MASK;
942 return ptype_table[pkt_info];
945 static inline uint64_t
946 ixgbe_rxd_pkt_info_to_pkt_flags(uint16_t pkt_info)
948 static uint64_t ip_rss_types_map[16] __rte_cache_aligned = {
949 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
950 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
951 PKT_RX_RSS_HASH, 0, 0, 0,
952 0, 0, 0, PKT_RX_FDIR,
954 #ifdef RTE_LIBRTE_IEEE1588
955 static uint64_t ip_pkt_etqf_map[8] = {
956 0, 0, 0, PKT_RX_IEEE1588_PTP,
960 if (likely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
961 return ip_pkt_etqf_map[(pkt_info >> 4) & 0X07] |
962 ip_rss_types_map[pkt_info & 0XF];
964 return ip_rss_types_map[pkt_info & 0XF];
966 return ip_rss_types_map[pkt_info & 0XF];
970 static inline uint64_t
971 rx_desc_status_to_pkt_flags(uint32_t rx_status)
976 * Check if VLAN present only.
977 * Do not check whether L3/L4 rx checksum done by NIC or not,
978 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
980 pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;
982 #ifdef RTE_LIBRTE_IEEE1588
983 if (rx_status & IXGBE_RXD_STAT_TMST)
984 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
989 static inline uint64_t
990 rx_desc_error_to_pkt_flags(uint32_t rx_status)
993 * Bit 31: IPE, IPv4 checksum error
994 * Bit 30: L4I, L4I integrity error
996 static uint64_t error_to_pkt_flags_map[4] = {
997 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
998 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
1000 return error_to_pkt_flags_map[(rx_status >>
1001 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
1005 * LOOK_AHEAD defines how many desc statuses to check beyond the
1006 * current descriptor.
1007 * It must be a pound define for optimal performance.
1008 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
1009 * function only works with LOOK_AHEAD=8.
1011 #define LOOK_AHEAD 8
1012 #if (LOOK_AHEAD != 8)
1013 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
1016 ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
1018 volatile union ixgbe_adv_rx_desc *rxdp;
1019 struct ixgbe_rx_entry *rxep;
1020 struct rte_mbuf *mb;
1024 uint32_t s[LOOK_AHEAD];
1025 uint16_t pkt_info[LOOK_AHEAD];
1026 int i, j, nb_rx = 0;
1029 /* get references to current descriptor and S/W ring entry */
1030 rxdp = &rxq->rx_ring[rxq->rx_tail];
1031 rxep = &rxq->sw_ring[rxq->rx_tail];
1033 status = rxdp->wb.upper.status_error;
1034 /* check to make sure there is at least 1 packet to receive */
1035 if (!(status & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1039 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
1040 * reference packets that are ready to be received.
1042 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
1043 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
1045 /* Read desc statuses backwards to avoid race condition */
1046 for (j = LOOK_AHEAD-1; j >= 0; --j)
1047 s[j] = rte_le_to_cpu_32(rxdp[j].wb.upper.status_error);
1049 for (j = LOOK_AHEAD - 1; j >= 0; --j)
1050 pkt_info[j] = rxdp[j].wb.lower.lo_dword.
1053 /* Compute how many status bits were set */
1055 for (j = 0; j < LOOK_AHEAD; ++j)
1056 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
1060 /* Translate descriptor info to mbuf format */
1061 for (j = 0; j < nb_dd; ++j) {
1063 pkt_len = rte_le_to_cpu_16(rxdp[j].wb.upper.length) -
1065 mb->data_len = pkt_len;
1066 mb->pkt_len = pkt_len;
1067 mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
1069 /* convert descriptor fields to rte mbuf flags */
1070 pkt_flags = rx_desc_status_to_pkt_flags(s[j]);
1071 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
1073 ixgbe_rxd_pkt_info_to_pkt_flags(pkt_info[j]);
1074 mb->ol_flags = pkt_flags;
1076 ixgbe_rxd_pkt_info_to_pkt_type(pkt_info[j]);
1078 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1079 mb->hash.rss = rte_le_to_cpu_32(
1080 rxdp[j].wb.lower.hi_dword.rss);
1081 else if (pkt_flags & PKT_RX_FDIR) {
1082 mb->hash.fdir.hash = rte_le_to_cpu_16(
1083 rxdp[j].wb.lower.hi_dword.csum_ip.csum) &
1084 IXGBE_ATR_HASH_MASK;
1085 mb->hash.fdir.id = rte_le_to_cpu_16(
1086 rxdp[j].wb.lower.hi_dword.csum_ip.ip_id);
1090 /* Move mbuf pointers from the S/W ring to the stage */
1091 for (j = 0; j < LOOK_AHEAD; ++j) {
1092 rxq->rx_stage[i + j] = rxep[j].mbuf;
1095 /* stop if all requested packets could not be received */
1096 if (nb_dd != LOOK_AHEAD)
1100 /* clear software ring entries so we can cleanup correctly */
1101 for (i = 0; i < nb_rx; ++i) {
1102 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1110 ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq, bool reset_mbuf)
1112 volatile union ixgbe_adv_rx_desc *rxdp;
1113 struct ixgbe_rx_entry *rxep;
1114 struct rte_mbuf *mb;
1119 /* allocate buffers in bulk directly into the S/W ring */
1120 alloc_idx = rxq->rx_free_trigger - (rxq->rx_free_thresh - 1);
1121 rxep = &rxq->sw_ring[alloc_idx];
1122 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1123 rxq->rx_free_thresh);
1124 if (unlikely(diag != 0))
1127 rxdp = &rxq->rx_ring[alloc_idx];
1128 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1129 /* populate the static rte mbuf fields */
1134 mb->port = rxq->port_id;
1137 rte_mbuf_refcnt_set(mb, 1);
1138 mb->data_off = RTE_PKTMBUF_HEADROOM;
1140 /* populate the descriptors */
1141 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
1142 rxdp[i].read.hdr_addr = 0;
1143 rxdp[i].read.pkt_addr = dma_addr;
1146 /* update state of internal queue structure */
1147 rxq->rx_free_trigger = rxq->rx_free_trigger + rxq->rx_free_thresh;
1148 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1149 rxq->rx_free_trigger = rxq->rx_free_thresh - 1;
1155 static inline uint16_t
1156 ixgbe_rx_fill_from_stage(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1159 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1162 /* how many packets are ready to return? */
1163 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1165 /* copy mbuf pointers to the application's packet list */
1166 for (i = 0; i < nb_pkts; ++i)
1167 rx_pkts[i] = stage[i];
1169 /* update internal queue state */
1170 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1171 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1176 static inline uint16_t
1177 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1180 struct ixgbe_rx_queue *rxq = (struct ixgbe_rx_queue *)rx_queue;
1183 /* Any previously recv'd pkts will be returned from the Rx stage */
1184 if (rxq->rx_nb_avail)
1185 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1187 /* Scan the H/W ring for packets to receive */
1188 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1190 /* update internal queue state */
1191 rxq->rx_next_avail = 0;
1192 rxq->rx_nb_avail = nb_rx;
1193 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1195 /* if required, allocate new buffers to replenish descriptors */
1196 if (rxq->rx_tail > rxq->rx_free_trigger) {
1197 uint16_t cur_free_trigger = rxq->rx_free_trigger;
1199 if (ixgbe_rx_alloc_bufs(rxq, true) != 0) {
1201 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1202 "queue_id=%u", (unsigned) rxq->port_id,
1203 (unsigned) rxq->queue_id);
1205 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1206 rxq->rx_free_thresh;
1209 * Need to rewind any previous receives if we cannot
1210 * allocate new buffers to replenish the old ones.
1212 rxq->rx_nb_avail = 0;
1213 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1214 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1215 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1220 /* update tail pointer */
1222 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, cur_free_trigger);
1225 if (rxq->rx_tail >= rxq->nb_rx_desc)
1228 /* received any packets this loop? */
1229 if (rxq->rx_nb_avail)
1230 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1235 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1237 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1242 if (unlikely(nb_pkts == 0))
1245 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1246 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1248 /* request is relatively large, chunk it up */
1252 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1253 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1254 nb_rx = (uint16_t)(nb_rx + ret);
1255 nb_pkts = (uint16_t)(nb_pkts - ret);
1264 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1267 struct ixgbe_rx_queue *rxq;
1268 volatile union ixgbe_adv_rx_desc *rx_ring;
1269 volatile union ixgbe_adv_rx_desc *rxdp;
1270 struct ixgbe_rx_entry *sw_ring;
1271 struct ixgbe_rx_entry *rxe;
1272 struct rte_mbuf *rxm;
1273 struct rte_mbuf *nmb;
1274 union ixgbe_adv_rx_desc rxd;
1287 rx_id = rxq->rx_tail;
1288 rx_ring = rxq->rx_ring;
1289 sw_ring = rxq->sw_ring;
1290 while (nb_rx < nb_pkts) {
1292 * The order of operations here is important as the DD status
1293 * bit must not be read after any other descriptor fields.
1294 * rx_ring and rxdp are pointing to volatile data so the order
1295 * of accesses cannot be reordered by the compiler. If they were
1296 * not volatile, they could be reordered which could lead to
1297 * using invalid descriptor fields when read from rxd.
1299 rxdp = &rx_ring[rx_id];
1300 staterr = rxdp->wb.upper.status_error;
1301 if (!(staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1308 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1309 * is likely to be invalid and to be dropped by the various
1310 * validation checks performed by the network stack.
1312 * Allocate a new mbuf to replenish the RX ring descriptor.
1313 * If the allocation fails:
1314 * - arrange for that RX descriptor to be the first one
1315 * being parsed the next time the receive function is
1316 * invoked [on the same queue].
1318 * - Stop parsing the RX ring and return immediately.
1320 * This policy do not drop the packet received in the RX
1321 * descriptor for which the allocation of a new mbuf failed.
1322 * Thus, it allows that packet to be later retrieved if
1323 * mbuf have been freed in the mean time.
1324 * As a side effect, holding RX descriptors instead of
1325 * systematically giving them back to the NIC may lead to
1326 * RX ring exhaustion situations.
1327 * However, the NIC can gracefully prevent such situations
1328 * to happen by sending specific "back-pressure" flow control
1329 * frames to its peer(s).
1331 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1332 "ext_err_stat=0x%08x pkt_len=%u",
1333 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1334 (unsigned) rx_id, (unsigned) staterr,
1335 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1337 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1339 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1340 "queue_id=%u", (unsigned) rxq->port_id,
1341 (unsigned) rxq->queue_id);
1342 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1347 rxe = &sw_ring[rx_id];
1349 if (rx_id == rxq->nb_rx_desc)
1352 /* Prefetch next mbuf while processing current one. */
1353 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1356 * When next RX descriptor is on a cache-line boundary,
1357 * prefetch the next 4 RX descriptors and the next 8 pointers
1360 if ((rx_id & 0x3) == 0) {
1361 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1362 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1368 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1369 rxdp->read.hdr_addr = 0;
1370 rxdp->read.pkt_addr = dma_addr;
1373 * Initialize the returned mbuf.
1374 * 1) setup generic mbuf fields:
1375 * - number of segments,
1378 * - RX port identifier.
1379 * 2) integrate hardware offload data, if any:
1380 * - RSS flag & hash,
1381 * - IP checksum flag,
1382 * - VLAN TCI, if any,
1385 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1387 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1388 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1391 rxm->pkt_len = pkt_len;
1392 rxm->data_len = pkt_len;
1393 rxm->port = rxq->port_id;
1395 pkt_info = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.hs_rss.
1397 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1398 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1400 pkt_flags = rx_desc_status_to_pkt_flags(staterr);
1401 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1402 pkt_flags = pkt_flags |
1403 ixgbe_rxd_pkt_info_to_pkt_flags(pkt_info);
1404 rxm->ol_flags = pkt_flags;
1405 rxm->packet_type = ixgbe_rxd_pkt_info_to_pkt_type(pkt_info);
1407 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1408 rxm->hash.rss = rte_le_to_cpu_32(
1409 rxd.wb.lower.hi_dword.rss);
1410 else if (pkt_flags & PKT_RX_FDIR) {
1411 rxm->hash.fdir.hash = rte_le_to_cpu_16(
1412 rxd.wb.lower.hi_dword.csum_ip.csum) &
1413 IXGBE_ATR_HASH_MASK;
1414 rxm->hash.fdir.id = rte_le_to_cpu_16(
1415 rxd.wb.lower.hi_dword.csum_ip.ip_id);
1418 * Store the mbuf address into the next entry of the array
1419 * of returned packets.
1421 rx_pkts[nb_rx++] = rxm;
1423 rxq->rx_tail = rx_id;
1426 * If the number of free RX descriptors is greater than the RX free
1427 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1429 * Update the RDT with the value of the last processed RX descriptor
1430 * minus 1, to guarantee that the RDT register is never equal to the
1431 * RDH register, which creates a "full" ring situtation from the
1432 * hardware point of view...
1434 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1435 if (nb_hold > rxq->rx_free_thresh) {
1436 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1437 "nb_hold=%u nb_rx=%u",
1438 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1439 (unsigned) rx_id, (unsigned) nb_hold,
1441 rx_id = (uint16_t) ((rx_id == 0) ?
1442 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1443 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1446 rxq->nb_rx_hold = nb_hold;
1451 * Detect an RSC descriptor.
1453 static inline uint32_t
1454 ixgbe_rsc_count(union ixgbe_adv_rx_desc *rx)
1456 return (rte_le_to_cpu_32(rx->wb.lower.lo_dword.data) &
1457 IXGBE_RXDADV_RSCCNT_MASK) >> IXGBE_RXDADV_RSCCNT_SHIFT;
1461 * ixgbe_fill_cluster_head_buf - fill the first mbuf of the returned packet
1463 * Fill the following info in the HEAD buffer of the Rx cluster:
1464 * - RX port identifier
1465 * - hardware offload data, if any:
1467 * - IP checksum flag
1468 * - VLAN TCI, if any
1470 * @head HEAD of the packet cluster
1471 * @desc HW descriptor to get data from
1472 * @port_id Port ID of the Rx queue
1475 ixgbe_fill_cluster_head_buf(
1476 struct rte_mbuf *head,
1477 union ixgbe_adv_rx_desc *desc,
1484 head->port = port_id;
1486 /* The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1487 * set in the pkt_flags field.
1489 head->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);
1490 pkt_info = rte_le_to_cpu_32(desc->wb.lower.lo_dword.hs_rss.pkt_info);
1491 pkt_flags = rx_desc_status_to_pkt_flags(staterr);
1492 pkt_flags |= rx_desc_error_to_pkt_flags(staterr);
1493 pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags(pkt_info);
1494 head->ol_flags = pkt_flags;
1495 head->packet_type = ixgbe_rxd_pkt_info_to_pkt_type(pkt_info);
1497 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1498 head->hash.rss = rte_le_to_cpu_32(desc->wb.lower.hi_dword.rss);
1499 else if (pkt_flags & PKT_RX_FDIR) {
1500 head->hash.fdir.hash =
1501 rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.csum)
1502 & IXGBE_ATR_HASH_MASK;
1503 head->hash.fdir.id =
1504 rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.ip_id);
1509 * ixgbe_recv_pkts_lro - receive handler for and LRO case.
1511 * @rx_queue Rx queue handle
1512 * @rx_pkts table of received packets
1513 * @nb_pkts size of rx_pkts table
1514 * @bulk_alloc if TRUE bulk allocation is used for a HW ring refilling
1516 * Handles the Rx HW ring completions when RSC feature is configured. Uses an
1517 * additional ring of ixgbe_rsc_entry's that will hold the relevant RSC info.
1519 * We use the same logic as in Linux and in FreeBSD ixgbe drivers:
1520 * 1) When non-EOP RSC completion arrives:
1521 * a) Update the HEAD of the current RSC aggregation cluster with the new
1522 * segment's data length.
1523 * b) Set the "next" pointer of the current segment to point to the segment
1524 * at the NEXTP index.
1525 * c) Pass the HEAD of RSC aggregation cluster on to the next NEXTP entry
1526 * in the sw_rsc_ring.
1527 * 2) When EOP arrives we just update the cluster's total length and offload
1528 * flags and deliver the cluster up to the upper layers. In our case - put it
1529 * in the rx_pkts table.
1531 * Returns the number of received packets/clusters (according to the "bulk
1532 * receive" interface).
1534 static inline uint16_t
1535 ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
1538 struct ixgbe_rx_queue *rxq = rx_queue;
1539 volatile union ixgbe_adv_rx_desc *rx_ring = rxq->rx_ring;
1540 struct ixgbe_rx_entry *sw_ring = rxq->sw_ring;
1541 struct ixgbe_scattered_rx_entry *sw_sc_ring = rxq->sw_sc_ring;
1542 uint16_t rx_id = rxq->rx_tail;
1544 uint16_t nb_hold = rxq->nb_rx_hold;
1545 uint16_t prev_id = rxq->rx_tail;
1547 while (nb_rx < nb_pkts) {
1549 struct ixgbe_rx_entry *rxe;
1550 struct ixgbe_scattered_rx_entry *sc_entry;
1551 struct ixgbe_scattered_rx_entry *next_sc_entry;
1552 struct ixgbe_rx_entry *next_rxe;
1553 struct rte_mbuf *first_seg;
1554 struct rte_mbuf *rxm;
1555 struct rte_mbuf *nmb;
1556 union ixgbe_adv_rx_desc rxd;
1559 volatile union ixgbe_adv_rx_desc *rxdp;
1564 * The code in this whole file uses the volatile pointer to
1565 * ensure the read ordering of the status and the rest of the
1566 * descriptor fields (on the compiler level only!!!). This is so
1567 * UGLY - why not to just use the compiler barrier instead? DPDK
1568 * even has the rte_compiler_barrier() for that.
1570 * But most importantly this is just wrong because this doesn't
1571 * ensure memory ordering in a general case at all. For
1572 * instance, DPDK is supposed to work on Power CPUs where
1573 * compiler barrier may just not be enough!
1575 * I tried to write only this function properly to have a
1576 * starting point (as a part of an LRO/RSC series) but the
1577 * compiler cursed at me when I tried to cast away the
1578 * "volatile" from rx_ring (yes, it's volatile too!!!). So, I'm
1579 * keeping it the way it is for now.
1581 * The code in this file is broken in so many other places and
1582 * will just not work on a big endian CPU anyway therefore the
1583 * lines below will have to be revisited together with the rest
1587 * - Get rid of "volatile" crap and let the compiler do its
1589 * - Use the proper memory barrier (rte_rmb()) to ensure the
1590 * memory ordering below.
1592 rxdp = &rx_ring[rx_id];
1593 staterr = rte_le_to_cpu_32(rxdp->wb.upper.status_error);
1595 if (!(staterr & IXGBE_RXDADV_STAT_DD))
1600 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1601 "staterr=0x%x data_len=%u",
1602 rxq->port_id, rxq->queue_id, rx_id, staterr,
1603 rte_le_to_cpu_16(rxd.wb.upper.length));
1606 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1608 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed "
1609 "port_id=%u queue_id=%u",
1610 rxq->port_id, rxq->queue_id);
1612 rte_eth_devices[rxq->port_id].data->
1613 rx_mbuf_alloc_failed++;
1617 else if (nb_hold > rxq->rx_free_thresh) {
1618 uint16_t next_rdt = rxq->rx_free_trigger;
1620 if (!ixgbe_rx_alloc_bufs(rxq, false)) {
1622 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr,
1624 nb_hold -= rxq->rx_free_thresh;
1626 PMD_RX_LOG(DEBUG, "RX bulk alloc failed "
1627 "port_id=%u queue_id=%u",
1628 rxq->port_id, rxq->queue_id);
1630 rte_eth_devices[rxq->port_id].data->
1631 rx_mbuf_alloc_failed++;
1637 rxe = &sw_ring[rx_id];
1638 eop = staterr & IXGBE_RXDADV_STAT_EOP;
1640 next_id = rx_id + 1;
1641 if (next_id == rxq->nb_rx_desc)
1644 /* Prefetch next mbuf while processing current one. */
1645 rte_ixgbe_prefetch(sw_ring[next_id].mbuf);
1648 * When next RX descriptor is on a cache-line boundary,
1649 * prefetch the next 4 RX descriptors and the next 4 pointers
1652 if ((next_id & 0x3) == 0) {
1653 rte_ixgbe_prefetch(&rx_ring[next_id]);
1654 rte_ixgbe_prefetch(&sw_ring[next_id]);
1661 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1663 * Update RX descriptor with the physical address of the
1664 * new data buffer of the new allocated mbuf.
1668 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1669 rxdp->read.hdr_addr = 0;
1670 rxdp->read.pkt_addr = dma;
1675 * Set data length & data buffer address of mbuf.
1677 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1678 rxm->data_len = data_len;
1683 * Get next descriptor index:
1684 * - For RSC it's in the NEXTP field.
1685 * - For a scattered packet - it's just a following
1688 if (ixgbe_rsc_count(&rxd))
1690 (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1691 IXGBE_RXDADV_NEXTP_SHIFT;
1695 next_sc_entry = &sw_sc_ring[nextp_id];
1696 next_rxe = &sw_ring[nextp_id];
1697 rte_ixgbe_prefetch(next_rxe);
1700 sc_entry = &sw_sc_ring[rx_id];
1701 first_seg = sc_entry->fbuf;
1702 sc_entry->fbuf = NULL;
1705 * If this is the first buffer of the received packet,
1706 * set the pointer to the first mbuf of the packet and
1707 * initialize its context.
1708 * Otherwise, update the total length and the number of segments
1709 * of the current scattered packet, and update the pointer to
1710 * the last mbuf of the current packet.
1712 if (first_seg == NULL) {
1714 first_seg->pkt_len = data_len;
1715 first_seg->nb_segs = 1;
1717 first_seg->pkt_len += data_len;
1718 first_seg->nb_segs++;
1725 * If this is not the last buffer of the received packet, update
1726 * the pointer to the first mbuf at the NEXTP entry in the
1727 * sw_sc_ring and continue to parse the RX ring.
1730 rxm->next = next_rxe->mbuf;
1731 next_sc_entry->fbuf = first_seg;
1736 * This is the last buffer of the received packet - return
1737 * the current cluster to the user.
1741 /* Initialize the first mbuf of the returned packet */
1742 ixgbe_fill_cluster_head_buf(first_seg, &rxd, rxq->port_id,
1746 * Deal with the case, when HW CRC srip is disabled.
1747 * That can't happen when LRO is enabled, but still could
1748 * happen for scattered RX mode.
1750 first_seg->pkt_len -= rxq->crc_len;
1751 if (unlikely(rxm->data_len <= rxq->crc_len)) {
1752 struct rte_mbuf *lp;
1754 for (lp = first_seg; lp->next != rxm; lp = lp->next)
1757 first_seg->nb_segs--;
1758 lp->data_len -= rxq->crc_len - rxm->data_len;
1760 rte_pktmbuf_free_seg(rxm);
1762 rxm->data_len -= rxq->crc_len;
1764 /* Prefetch data of first segment, if configured to do so. */
1765 rte_packet_prefetch((char *)first_seg->buf_addr +
1766 first_seg->data_off);
1769 * Store the mbuf address into the next entry of the array
1770 * of returned packets.
1772 rx_pkts[nb_rx++] = first_seg;
1776 * Record index of the next RX descriptor to probe.
1778 rxq->rx_tail = rx_id;
1781 * If the number of free RX descriptors is greater than the RX free
1782 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1784 * Update the RDT with the value of the last processed RX descriptor
1785 * minus 1, to guarantee that the RDT register is never equal to the
1786 * RDH register, which creates a "full" ring situtation from the
1787 * hardware point of view...
1789 if (!bulk_alloc && nb_hold > rxq->rx_free_thresh) {
1790 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1791 "nb_hold=%u nb_rx=%u",
1792 rxq->port_id, rxq->queue_id, rx_id, nb_hold, nb_rx);
1795 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, prev_id);
1799 rxq->nb_rx_hold = nb_hold;
1804 ixgbe_recv_pkts_lro_single_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1807 return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, false);
1811 ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1814 return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, true);
1817 /*********************************************************************
1819 * Queue management functions
1821 **********************************************************************/
1824 * Rings setup and release.
1826 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1827 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1828 * also optimize cache line size effect. H/W supports up to cache line size 128.
1830 #define IXGBE_ALIGN 128
1833 * Maximum number of Ring Descriptors.
1835 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1836 * descriptors should meet the following condition:
1837 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1839 #define IXGBE_MIN_RING_DESC 32
1840 #define IXGBE_MAX_RING_DESC 4096
1843 * Create memzone for HW rings. malloc can't be used as the physical address is
1844 * needed. If the memzone is already created, then this function returns a ptr
1847 static const struct rte_memzone * __attribute__((cold))
1848 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1849 uint16_t queue_id, uint32_t ring_size, int socket_id)
1851 char z_name[RTE_MEMZONE_NAMESIZE];
1852 const struct rte_memzone *mz;
1854 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1855 dev->driver->pci_drv.name, ring_name,
1856 dev->data->port_id, queue_id);
1858 mz = rte_memzone_lookup(z_name);
1862 #ifdef RTE_LIBRTE_XEN_DOM0
1863 return rte_memzone_reserve_bounded(z_name, ring_size,
1864 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1866 return rte_memzone_reserve_aligned(z_name, ring_size,
1867 socket_id, 0, IXGBE_ALIGN);
1871 static void __attribute__((cold))
1872 ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)
1876 if (txq->sw_ring != NULL) {
1877 for (i = 0; i < txq->nb_tx_desc; i++) {
1878 if (txq->sw_ring[i].mbuf != NULL) {
1879 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1880 txq->sw_ring[i].mbuf = NULL;
1886 static void __attribute__((cold))
1887 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
1890 txq->sw_ring != NULL)
1891 rte_free(txq->sw_ring);
1894 static void __attribute__((cold))
1895 ixgbe_tx_queue_release(struct ixgbe_tx_queue *txq)
1897 if (txq != NULL && txq->ops != NULL) {
1898 txq->ops->release_mbufs(txq);
1899 txq->ops->free_swring(txq);
1904 void __attribute__((cold))
1905 ixgbe_dev_tx_queue_release(void *txq)
1907 ixgbe_tx_queue_release(txq);
1910 /* (Re)set dynamic ixgbe_tx_queue fields to defaults */
1911 static void __attribute__((cold))
1912 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
1914 static const union ixgbe_adv_tx_desc zeroed_desc = {{0}};
1915 struct ixgbe_tx_entry *txe = txq->sw_ring;
1918 /* Zero out HW ring memory */
1919 for (i = 0; i < txq->nb_tx_desc; i++) {
1920 txq->tx_ring[i] = zeroed_desc;
1923 /* Initialize SW ring entries */
1924 prev = (uint16_t) (txq->nb_tx_desc - 1);
1925 for (i = 0; i < txq->nb_tx_desc; i++) {
1926 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1927 txd->wb.status = rte_cpu_to_le_32(IXGBE_TXD_STAT_DD);
1930 txe[prev].next_id = i;
1934 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1935 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1938 txq->nb_tx_used = 0;
1940 * Always allow 1 descriptor to be un-allocated to avoid
1941 * a H/W race condition
1943 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1944 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1946 memset((void*)&txq->ctx_cache, 0,
1947 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1950 static const struct ixgbe_txq_ops def_txq_ops = {
1951 .release_mbufs = ixgbe_tx_queue_release_mbufs,
1952 .free_swring = ixgbe_tx_free_swring,
1953 .reset = ixgbe_reset_tx_queue,
1956 /* Takes an ethdev and a queue and sets up the tx function to be used based on
1957 * the queue parameters. Used in tx_queue_setup by primary process and then
1958 * in dev_init by secondary process when attaching to an existing ethdev.
1960 void __attribute__((cold))
1961 ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)
1963 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
1964 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS)
1965 && (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
1966 PMD_INIT_LOG(DEBUG, "Using simple tx code path");
1967 #ifdef RTE_IXGBE_INC_VECTOR
1968 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
1969 (rte_eal_process_type() != RTE_PROC_PRIMARY ||
1970 ixgbe_txq_vec_setup(txq) == 0)) {
1971 PMD_INIT_LOG(DEBUG, "Vector tx enabled.");
1972 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
1975 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
1977 PMD_INIT_LOG(DEBUG, "Using full-featured tx code path");
1979 " - txq_flags = %lx " "[IXGBE_SIMPLE_FLAGS=%lx]",
1980 (unsigned long)txq->txq_flags,
1981 (unsigned long)IXGBE_SIMPLE_FLAGS);
1983 " - tx_rs_thresh = %lu " "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
1984 (unsigned long)txq->tx_rs_thresh,
1985 (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST);
1986 dev->tx_pkt_burst = ixgbe_xmit_pkts;
1990 int __attribute__((cold))
1991 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1994 unsigned int socket_id,
1995 const struct rte_eth_txconf *tx_conf)
1997 const struct rte_memzone *tz;
1998 struct ixgbe_tx_queue *txq;
1999 struct ixgbe_hw *hw;
2000 uint16_t tx_rs_thresh, tx_free_thresh;
2002 PMD_INIT_FUNC_TRACE();
2003 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2006 * Validate number of transmit descriptors.
2007 * It must not exceed hardware maximum, and must be multiple
2010 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
2011 (nb_desc > IXGBE_MAX_RING_DESC) ||
2012 (nb_desc < IXGBE_MIN_RING_DESC)) {
2017 * The following two parameters control the setting of the RS bit on
2018 * transmit descriptors.
2019 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
2020 * descriptors have been used.
2021 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
2022 * descriptors are used or if the number of descriptors required
2023 * to transmit a packet is greater than the number of free TX
2025 * The following constraints must be satisfied:
2026 * tx_rs_thresh must be greater than 0.
2027 * tx_rs_thresh must be less than the size of the ring minus 2.
2028 * tx_rs_thresh must be less than or equal to tx_free_thresh.
2029 * tx_rs_thresh must be a divisor of the ring size.
2030 * tx_free_thresh must be greater than 0.
2031 * tx_free_thresh must be less than the size of the ring minus 3.
2032 * One descriptor in the TX ring is used as a sentinel to avoid a
2033 * H/W race condition, hence the maximum threshold constraints.
2034 * When set to zero use default values.
2036 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2037 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2038 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2039 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2040 if (tx_rs_thresh >= (nb_desc - 2)) {
2041 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
2042 "of TX descriptors minus 2. (tx_rs_thresh=%u "
2043 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2044 (int)dev->data->port_id, (int)queue_idx);
2047 if (tx_free_thresh >= (nb_desc - 3)) {
2048 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2049 "tx_free_thresh must be less than the number of "
2050 "TX descriptors minus 3. (tx_free_thresh=%u "
2051 "port=%d queue=%d)",
2052 (unsigned int)tx_free_thresh,
2053 (int)dev->data->port_id, (int)queue_idx);
2056 if (tx_rs_thresh > tx_free_thresh) {
2057 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
2058 "tx_free_thresh. (tx_free_thresh=%u "
2059 "tx_rs_thresh=%u port=%d queue=%d)",
2060 (unsigned int)tx_free_thresh,
2061 (unsigned int)tx_rs_thresh,
2062 (int)dev->data->port_id,
2066 if ((nb_desc % tx_rs_thresh) != 0) {
2067 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2068 "number of TX descriptors. (tx_rs_thresh=%u "
2069 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2070 (int)dev->data->port_id, (int)queue_idx);
2075 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
2076 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
2077 * by the NIC and all descriptors are written back after the NIC
2078 * accumulates WTHRESH descriptors.
2080 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2081 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2082 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
2083 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2084 (int)dev->data->port_id, (int)queue_idx);
2088 /* Free memory prior to re-allocation if needed... */
2089 if (dev->data->tx_queues[queue_idx] != NULL) {
2090 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
2091 dev->data->tx_queues[queue_idx] = NULL;
2094 /* First allocate the tx queue data structure */
2095 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct ixgbe_tx_queue),
2096 RTE_CACHE_LINE_SIZE, socket_id);
2101 * Allocate TX ring hardware descriptors. A memzone large enough to
2102 * handle the maximum ring size is allocated in order to allow for
2103 * resizing in later calls to the queue setup function.
2105 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
2106 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
2109 ixgbe_tx_queue_release(txq);
2113 txq->nb_tx_desc = nb_desc;
2114 txq->tx_rs_thresh = tx_rs_thresh;
2115 txq->tx_free_thresh = tx_free_thresh;
2116 txq->pthresh = tx_conf->tx_thresh.pthresh;
2117 txq->hthresh = tx_conf->tx_thresh.hthresh;
2118 txq->wthresh = tx_conf->tx_thresh.wthresh;
2119 txq->queue_id = queue_idx;
2120 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2121 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2122 txq->port_id = dev->data->port_id;
2123 txq->txq_flags = tx_conf->txq_flags;
2124 txq->ops = &def_txq_ops;
2125 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2128 * Modification to set VFTDT for virtual function if vf is detected
2130 if (hw->mac.type == ixgbe_mac_82599_vf ||
2131 hw->mac.type == ixgbe_mac_X540_vf ||
2132 hw->mac.type == ixgbe_mac_X550_vf ||
2133 hw->mac.type == ixgbe_mac_X550EM_x_vf)
2134 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
2136 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
2137 #ifndef RTE_LIBRTE_XEN_DOM0
2138 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
2140 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2142 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
2144 /* Allocate software ring */
2145 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
2146 sizeof(struct ixgbe_tx_entry) * nb_desc,
2147 RTE_CACHE_LINE_SIZE, socket_id);
2148 if (txq->sw_ring == NULL) {
2149 ixgbe_tx_queue_release(txq);
2152 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2153 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
2155 /* set up vector or scalar TX function as appropriate */
2156 ixgbe_set_tx_function(dev, txq);
2158 txq->ops->reset(txq);
2160 dev->data->tx_queues[queue_idx] = txq;
2167 * ixgbe_free_sc_cluster - free the not-yet-completed scattered cluster
2169 * The "next" pointer of the last segment of (not-yet-completed) RSC clusters
2170 * in the sw_rsc_ring is not set to NULL but rather points to the next
2171 * mbuf of this RSC aggregation (that has not been completed yet and still
2172 * resides on the HW ring). So, instead of calling for rte_pktmbuf_free() we
2173 * will just free first "nb_segs" segments of the cluster explicitly by calling
2174 * an rte_pktmbuf_free_seg().
2176 * @m scattered cluster head
2178 static void __attribute__((cold))
2179 ixgbe_free_sc_cluster(struct rte_mbuf *m)
2181 uint8_t i, nb_segs = m->nb_segs;
2182 struct rte_mbuf *next_seg;
2184 for (i = 0; i < nb_segs; i++) {
2186 rte_pktmbuf_free_seg(m);
2191 static void __attribute__((cold))
2192 ixgbe_rx_queue_release_mbufs(struct ixgbe_rx_queue *rxq)
2196 #ifdef RTE_IXGBE_INC_VECTOR
2197 /* SSE Vector driver has a different way of releasing mbufs. */
2198 if (rxq->rx_using_sse) {
2199 ixgbe_rx_queue_release_mbufs_vec(rxq);
2204 if (rxq->sw_ring != NULL) {
2205 for (i = 0; i < rxq->nb_rx_desc; i++) {
2206 if (rxq->sw_ring[i].mbuf != NULL) {
2207 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2208 rxq->sw_ring[i].mbuf = NULL;
2211 if (rxq->rx_nb_avail) {
2212 for (i = 0; i < rxq->rx_nb_avail; ++i) {
2213 struct rte_mbuf *mb;
2214 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2215 rte_pktmbuf_free_seg(mb);
2217 rxq->rx_nb_avail = 0;
2221 if (rxq->sw_sc_ring)
2222 for (i = 0; i < rxq->nb_rx_desc; i++)
2223 if (rxq->sw_sc_ring[i].fbuf) {
2224 ixgbe_free_sc_cluster(rxq->sw_sc_ring[i].fbuf);
2225 rxq->sw_sc_ring[i].fbuf = NULL;
2229 static void __attribute__((cold))
2230 ixgbe_rx_queue_release(struct ixgbe_rx_queue *rxq)
2233 ixgbe_rx_queue_release_mbufs(rxq);
2234 rte_free(rxq->sw_ring);
2235 rte_free(rxq->sw_sc_ring);
2240 void __attribute__((cold))
2241 ixgbe_dev_rx_queue_release(void *rxq)
2243 ixgbe_rx_queue_release(rxq);
2247 * Check if Rx Burst Bulk Alloc function can be used.
2249 * 0: the preconditions are satisfied and the bulk allocation function
2251 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2252 * function must be used.
2254 static inline int __attribute__((cold))
2255 check_rx_burst_bulk_alloc_preconditions(struct ixgbe_rx_queue *rxq)
2260 * Make sure the following pre-conditions are satisfied:
2261 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2262 * rxq->rx_free_thresh < rxq->nb_rx_desc
2263 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2264 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
2265 * Scattered packets are not supported. This should be checked
2266 * outside of this function.
2268 if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
2269 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2270 "rxq->rx_free_thresh=%d, "
2271 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2272 rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
2274 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
2275 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2276 "rxq->rx_free_thresh=%d, "
2277 "rxq->nb_rx_desc=%d",
2278 rxq->rx_free_thresh, rxq->nb_rx_desc);
2280 } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
2281 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2282 "rxq->nb_rx_desc=%d, "
2283 "rxq->rx_free_thresh=%d",
2284 rxq->nb_rx_desc, rxq->rx_free_thresh);
2286 } else if (!(rxq->nb_rx_desc <
2287 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST))) {
2288 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2289 "rxq->nb_rx_desc=%d, "
2290 "IXGBE_MAX_RING_DESC=%d, "
2291 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2292 rxq->nb_rx_desc, IXGBE_MAX_RING_DESC,
2293 RTE_PMD_IXGBE_RX_MAX_BURST);
2300 /* Reset dynamic ixgbe_rx_queue fields back to defaults */
2301 static void __attribute__((cold))
2302 ixgbe_reset_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_rx_queue *rxq)
2304 static const union ixgbe_adv_rx_desc zeroed_desc = {{0}};
2306 uint16_t len = rxq->nb_rx_desc;
2309 * By default, the Rx queue setup function allocates enough memory for
2310 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2311 * extra memory at the end of the descriptor ring to be zero'd out. A
2312 * pre-condition for using the Rx burst bulk alloc function is that the
2313 * number of descriptors is less than or equal to
2314 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2315 * constraints here to see if we need to zero out memory after the end
2316 * of the H/W descriptor ring.
2318 if (adapter->rx_bulk_alloc_allowed)
2319 /* zero out extra memory */
2320 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2323 * Zero out HW ring memory. Zero out extra memory at the end of
2324 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2325 * reads extra memory as zeros.
2327 for (i = 0; i < len; i++) {
2328 rxq->rx_ring[i] = zeroed_desc;
2332 * initialize extra software ring entries. Space for these extra
2333 * entries is always allocated
2335 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2336 for (i = rxq->nb_rx_desc; i < len; ++i) {
2337 rxq->sw_ring[i].mbuf = &rxq->fake_mbuf;
2340 rxq->rx_nb_avail = 0;
2341 rxq->rx_next_avail = 0;
2342 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2344 rxq->nb_rx_hold = 0;
2345 rxq->pkt_first_seg = NULL;
2346 rxq->pkt_last_seg = NULL;
2348 #ifdef RTE_IXGBE_INC_VECTOR
2349 rxq->rxrearm_start = 0;
2350 rxq->rxrearm_nb = 0;
2354 int __attribute__((cold))
2355 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2358 unsigned int socket_id,
2359 const struct rte_eth_rxconf *rx_conf,
2360 struct rte_mempool *mp)
2362 const struct rte_memzone *rz;
2363 struct ixgbe_rx_queue *rxq;
2364 struct ixgbe_hw *hw;
2366 struct ixgbe_adapter *adapter =
2367 (struct ixgbe_adapter *)dev->data->dev_private;
2369 PMD_INIT_FUNC_TRACE();
2370 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2373 * Validate number of receive descriptors.
2374 * It must not exceed hardware maximum, and must be multiple
2377 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2378 (nb_desc > IXGBE_MAX_RING_DESC) ||
2379 (nb_desc < IXGBE_MIN_RING_DESC)) {
2383 /* Free memory prior to re-allocation if needed... */
2384 if (dev->data->rx_queues[queue_idx] != NULL) {
2385 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2386 dev->data->rx_queues[queue_idx] = NULL;
2389 /* First allocate the rx queue data structure */
2390 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct ixgbe_rx_queue),
2391 RTE_CACHE_LINE_SIZE, socket_id);
2395 rxq->nb_rx_desc = nb_desc;
2396 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2397 rxq->queue_id = queue_idx;
2398 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2399 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2400 rxq->port_id = dev->data->port_id;
2401 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2403 rxq->drop_en = rx_conf->rx_drop_en;
2404 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2407 * Allocate RX ring hardware descriptors. A memzone large enough to
2408 * handle the maximum ring size is allocated in order to allow for
2409 * resizing in later calls to the queue setup function.
2411 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2412 RX_RING_SZ, socket_id);
2414 ixgbe_rx_queue_release(rxq);
2419 * Zero init all the descriptors in the ring.
2421 memset (rz->addr, 0, RX_RING_SZ);
2424 * Modified to setup VFRDT for Virtual Function
2426 if (hw->mac.type == ixgbe_mac_82599_vf ||
2427 hw->mac.type == ixgbe_mac_X540_vf ||
2428 hw->mac.type == ixgbe_mac_X550_vf ||
2429 hw->mac.type == ixgbe_mac_X550EM_x_vf) {
2431 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2433 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2437 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2439 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2441 #ifndef RTE_LIBRTE_XEN_DOM0
2442 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2444 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2446 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2449 * Certain constraints must be met in order to use the bulk buffer
2450 * allocation Rx burst function. If any of Rx queues doesn't meet them
2451 * the feature should be disabled for the whole port.
2453 if (check_rx_burst_bulk_alloc_preconditions(rxq)) {
2454 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Rx Bulk Alloc "
2455 "preconditions - canceling the feature for "
2456 "the whole port[%d]",
2457 rxq->queue_id, rxq->port_id);
2458 adapter->rx_bulk_alloc_allowed = false;
2462 * Allocate software ring. Allow for space at the end of the
2463 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2464 * function does not access an invalid memory region.
2467 if (adapter->rx_bulk_alloc_allowed)
2468 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2470 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2471 sizeof(struct ixgbe_rx_entry) * len,
2472 RTE_CACHE_LINE_SIZE, socket_id);
2473 if (!rxq->sw_ring) {
2474 ixgbe_rx_queue_release(rxq);
2479 * Always allocate even if it's not going to be needed in order to
2480 * simplify the code.
2482 * This ring is used in LRO and Scattered Rx cases and Scattered Rx may
2483 * be requested in ixgbe_dev_rx_init(), which is called later from
2487 rte_zmalloc_socket("rxq->sw_sc_ring",
2488 sizeof(struct ixgbe_scattered_rx_entry) * len,
2489 RTE_CACHE_LINE_SIZE, socket_id);
2490 if (!rxq->sw_sc_ring) {
2491 ixgbe_rx_queue_release(rxq);
2495 PMD_INIT_LOG(DEBUG, "sw_ring=%p sw_sc_ring=%p hw_ring=%p "
2496 "dma_addr=0x%"PRIx64,
2497 rxq->sw_ring, rxq->sw_sc_ring, rxq->rx_ring,
2498 rxq->rx_ring_phys_addr);
2500 if (!rte_is_power_of_2(nb_desc)) {
2501 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
2502 "preconditions - canceling the feature for "
2503 "the whole port[%d]",
2504 rxq->queue_id, rxq->port_id);
2505 adapter->rx_vec_allowed = false;
2507 ixgbe_rxq_vec_setup(rxq);
2509 dev->data->rx_queues[queue_idx] = rxq;
2511 ixgbe_reset_rx_queue(adapter, rxq);
2517 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2519 #define IXGBE_RXQ_SCAN_INTERVAL 4
2520 volatile union ixgbe_adv_rx_desc *rxdp;
2521 struct ixgbe_rx_queue *rxq;
2524 if (rx_queue_id >= dev->data->nb_rx_queues) {
2525 PMD_RX_LOG(ERR, "Invalid RX queue id=%d", rx_queue_id);
2529 rxq = dev->data->rx_queues[rx_queue_id];
2530 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2532 while ((desc < rxq->nb_rx_desc) &&
2533 (rxdp->wb.upper.status_error &
2534 rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))) {
2535 desc += IXGBE_RXQ_SCAN_INTERVAL;
2536 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2537 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2538 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2539 desc - rxq->nb_rx_desc]);
2546 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2548 volatile union ixgbe_adv_rx_desc *rxdp;
2549 struct ixgbe_rx_queue *rxq = rx_queue;
2552 if (unlikely(offset >= rxq->nb_rx_desc))
2554 desc = rxq->rx_tail + offset;
2555 if (desc >= rxq->nb_rx_desc)
2556 desc -= rxq->nb_rx_desc;
2558 rxdp = &rxq->rx_ring[desc];
2559 return !!(rxdp->wb.upper.status_error &
2560 rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD));
2563 void __attribute__((cold))
2564 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2567 struct ixgbe_adapter *adapter =
2568 (struct ixgbe_adapter *)dev->data->dev_private;
2570 PMD_INIT_FUNC_TRACE();
2572 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2573 struct ixgbe_tx_queue *txq = dev->data->tx_queues[i];
2575 txq->ops->release_mbufs(txq);
2576 txq->ops->reset(txq);
2580 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2581 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
2583 ixgbe_rx_queue_release_mbufs(rxq);
2584 ixgbe_reset_rx_queue(adapter, rxq);
2590 ixgbe_dev_free_queues(struct rte_eth_dev *dev)
2594 PMD_INIT_FUNC_TRACE();
2596 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2597 ixgbe_dev_rx_queue_release(dev->data->rx_queues[i]);
2598 dev->data->rx_queues[i] = NULL;
2600 dev->data->nb_rx_queues = 0;
2602 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2603 ixgbe_dev_tx_queue_release(dev->data->tx_queues[i]);
2604 dev->data->tx_queues[i] = NULL;
2606 dev->data->nb_tx_queues = 0;
2609 /*********************************************************************
2611 * Device RX/TX init functions
2613 **********************************************************************/
2616 * Receive Side Scaling (RSS)
2617 * See section 7.1.2.8 in the following document:
2618 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2621 * The source and destination IP addresses of the IP header and the source
2622 * and destination ports of TCP/UDP headers, if any, of received packets are
2623 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2624 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2625 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2626 * RSS output index which is used as the RX queue index where to store the
2628 * The following output is supplied in the RX write-back descriptor:
2629 * - 32-bit result of the Microsoft RSS hash function,
2630 * - 4-bit RSS type field.
2634 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2635 * Used as the default key.
2637 static uint8_t rss_intel_key[40] = {
2638 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2639 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2640 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2641 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2642 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2646 ixgbe_rss_disable(struct rte_eth_dev *dev)
2648 struct ixgbe_hw *hw;
2651 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2652 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2653 mrqc &= ~IXGBE_MRQC_RSSEN;
2654 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2658 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2666 hash_key = rss_conf->rss_key;
2667 if (hash_key != NULL) {
2668 /* Fill in RSS hash key */
2669 for (i = 0; i < 10; i++) {
2670 rss_key = hash_key[(i * 4)];
2671 rss_key |= hash_key[(i * 4) + 1] << 8;
2672 rss_key |= hash_key[(i * 4) + 2] << 16;
2673 rss_key |= hash_key[(i * 4) + 3] << 24;
2674 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2678 /* Set configured hashing protocols in MRQC register */
2679 rss_hf = rss_conf->rss_hf;
2680 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2681 if (rss_hf & ETH_RSS_IPV4)
2682 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2683 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2684 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2685 if (rss_hf & ETH_RSS_IPV6)
2686 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2687 if (rss_hf & ETH_RSS_IPV6_EX)
2688 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2689 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2690 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2691 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2692 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2693 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2694 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2695 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2696 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2697 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2698 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2699 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2703 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2704 struct rte_eth_rss_conf *rss_conf)
2706 struct ixgbe_hw *hw;
2710 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2713 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2714 * "RSS enabling cannot be done dynamically while it must be
2715 * preceded by a software reset"
2716 * Before changing anything, first check that the update RSS operation
2717 * does not attempt to disable RSS, if RSS was enabled at
2718 * initialization time, or does not attempt to enable RSS, if RSS was
2719 * disabled at initialization time.
2721 rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
2722 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2723 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2724 if (rss_hf != 0) /* Enable RSS */
2726 return 0; /* Nothing to do */
2729 if (rss_hf == 0) /* Disable RSS */
2731 ixgbe_hw_rss_hash_set(hw, rss_conf);
2736 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2737 struct rte_eth_rss_conf *rss_conf)
2739 struct ixgbe_hw *hw;
2746 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2747 hash_key = rss_conf->rss_key;
2748 if (hash_key != NULL) {
2749 /* Return RSS hash key */
2750 for (i = 0; i < 10; i++) {
2751 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2752 hash_key[(i * 4)] = rss_key & 0x000000FF;
2753 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2754 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2755 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2759 /* Get RSS functions configured in MRQC register */
2760 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2761 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2762 rss_conf->rss_hf = 0;
2766 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2767 rss_hf |= ETH_RSS_IPV4;
2768 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2769 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2770 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2771 rss_hf |= ETH_RSS_IPV6;
2772 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2773 rss_hf |= ETH_RSS_IPV6_EX;
2774 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2775 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2776 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2777 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2778 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2779 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2780 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2781 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2782 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2783 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2784 rss_conf->rss_hf = rss_hf;
2789 ixgbe_rss_configure(struct rte_eth_dev *dev)
2791 struct rte_eth_rss_conf rss_conf;
2792 struct ixgbe_hw *hw;
2797 PMD_INIT_FUNC_TRACE();
2798 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2801 * Fill in redirection table
2802 * The byte-swap is needed because NIC registers are in
2803 * little-endian order.
2806 for (i = 0, j = 0; i < 128; i++, j++) {
2807 if (j == dev->data->nb_rx_queues)
2809 reta = (reta << 8) | j;
2811 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2816 * Configure the RSS key and the RSS protocols used to compute
2817 * the RSS hash of input packets.
2819 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2820 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
2821 ixgbe_rss_disable(dev);
2824 if (rss_conf.rss_key == NULL)
2825 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2826 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2829 #define NUM_VFTA_REGISTERS 128
2830 #define NIC_RX_BUFFER_SIZE 0x200
2833 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2835 struct rte_eth_vmdq_dcb_conf *cfg;
2836 struct ixgbe_hw *hw;
2837 enum rte_eth_nb_pools num_pools;
2838 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2840 uint8_t nb_tcs; /* number of traffic classes */
2843 PMD_INIT_FUNC_TRACE();
2844 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2845 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2846 num_pools = cfg->nb_queue_pools;
2847 /* Check we have a valid number of pools */
2848 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2849 ixgbe_rss_disable(dev);
2852 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2853 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2857 * split rx buffer up into sections, each for 1 traffic class
2859 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2860 for (i = 0 ; i < nb_tcs; i++) {
2861 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2862 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2863 /* clear 10 bits. */
2864 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2865 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2867 /* zero alloc all unused TCs */
2868 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2869 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2870 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2871 /* clear 10 bits. */
2872 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2875 /* MRQC: enable vmdq and dcb */
2876 mrqc = ((num_pools == ETH_16_POOLS) ? \
2877 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2878 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2880 /* PFVTCTL: turn on virtualisation and set the default pool */
2881 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2882 if (cfg->enable_default_pool) {
2883 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2885 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2888 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2890 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2892 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2894 * mapping is done with 3 bits per priority,
2895 * so shift by i*3 each time
2897 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2899 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2901 /* RTRPCS: DCB related */
2902 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2904 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2905 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2906 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2907 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2909 /* VFTA - enable all vlan filters */
2910 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2911 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2914 /* VFRE: pool enabling for receive - 16 or 32 */
2915 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2916 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2919 * MPSAR - allow pools to read specific mac addresses
2920 * In this case, all pools should be able to read from mac addr 0
2922 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2923 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2925 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2926 for (i = 0; i < cfg->nb_pool_maps; i++) {
2927 /* set vlan id in VF register and set the valid bit */
2928 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2929 (cfg->pool_map[i].vlan_id & 0xFFF)));
2931 * Put the allowed pools in VFB reg. As we only have 16 or 32
2932 * pools, we only need to use the first half of the register
2935 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2940 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2941 * @hw: pointer to hardware structure
2942 * @dcb_config: pointer to ixgbe_dcb_config structure
2945 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2946 struct ixgbe_dcb_config *dcb_config)
2951 PMD_INIT_FUNC_TRACE();
2952 if (hw->mac.type != ixgbe_mac_82598EB) {
2953 /* Disable the Tx desc arbiter so that MTQC can be changed */
2954 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2955 reg |= IXGBE_RTTDCS_ARBDIS;
2956 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2958 /* Enable DCB for Tx with 8 TCs */
2959 if (dcb_config->num_tcs.pg_tcs == 8) {
2960 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2963 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2965 if (dcb_config->vt_mode)
2966 reg |= IXGBE_MTQC_VT_ENA;
2967 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2969 /* Disable drop for all queues */
2970 for (q = 0; q < 128; q++)
2971 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2972 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2974 /* Enable the Tx desc arbiter */
2975 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2976 reg &= ~IXGBE_RTTDCS_ARBDIS;
2977 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2979 /* Enable Security TX Buffer IFG for DCB */
2980 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2981 reg |= IXGBE_SECTX_DCB;
2982 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2988 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2989 * @dev: pointer to rte_eth_dev structure
2990 * @dcb_config: pointer to ixgbe_dcb_config structure
2993 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2994 struct ixgbe_dcb_config *dcb_config)
2996 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2997 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2998 struct ixgbe_hw *hw =
2999 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3001 PMD_INIT_FUNC_TRACE();
3002 if (hw->mac.type != ixgbe_mac_82598EB)
3003 /*PF VF Transmit Enable*/
3004 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
3005 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3007 /*Configure general DCB TX parameters*/
3008 ixgbe_dcb_tx_hw_config(hw,dcb_config);
3013 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
3014 struct ixgbe_dcb_config *dcb_config)
3016 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
3017 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3018 struct ixgbe_dcb_tc_config *tc;
3021 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3022 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
3023 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3024 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3027 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3028 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3030 /* User Priority to Traffic Class mapping */
3031 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3032 j = vmdq_rx_conf->dcb_queue[i];
3033 tc = &dcb_config->tc_config[j];
3034 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
3040 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
3041 struct ixgbe_dcb_config *dcb_config)
3043 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3044 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3045 struct ixgbe_dcb_tc_config *tc;
3048 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3049 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
3050 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3051 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3054 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3055 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3058 /* User Priority to Traffic Class mapping */
3059 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3060 j = vmdq_tx_conf->dcb_queue[i];
3061 tc = &dcb_config->tc_config[j];
3062 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
3069 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
3070 struct ixgbe_dcb_config *dcb_config)
3072 struct rte_eth_dcb_rx_conf *rx_conf =
3073 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
3074 struct ixgbe_dcb_tc_config *tc;
3077 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
3078 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
3080 /* User Priority to Traffic Class mapping */
3081 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3082 j = rx_conf->dcb_queue[i];
3083 tc = &dcb_config->tc_config[j];
3084 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
3090 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
3091 struct ixgbe_dcb_config *dcb_config)
3093 struct rte_eth_dcb_tx_conf *tx_conf =
3094 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
3095 struct ixgbe_dcb_tc_config *tc;
3098 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
3099 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
3101 /* User Priority to Traffic Class mapping */
3102 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3103 j = tx_conf->dcb_queue[i];
3104 tc = &dcb_config->tc_config[j];
3105 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
3111 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
3112 * @hw: pointer to hardware structure
3113 * @dcb_config: pointer to ixgbe_dcb_config structure
3116 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
3117 struct ixgbe_dcb_config *dcb_config)
3123 PMD_INIT_FUNC_TRACE();
3125 * Disable the arbiter before changing parameters
3126 * (always enable recycle mode; WSP)
3128 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
3129 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3131 if (hw->mac.type != ixgbe_mac_82598EB) {
3132 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
3133 if (dcb_config->num_tcs.pg_tcs == 4) {
3134 if (dcb_config->vt_mode)
3135 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3136 IXGBE_MRQC_VMDQRT4TCEN;
3138 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3139 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3143 if (dcb_config->num_tcs.pg_tcs == 8) {
3144 if (dcb_config->vt_mode)
3145 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3146 IXGBE_MRQC_VMDQRT8TCEN;
3148 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3149 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3154 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
3157 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3158 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3159 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3160 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3162 /* VFTA - enable all vlan filters */
3163 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3164 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3168 * Configure Rx packet plane (recycle mode; WSP) and
3171 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
3172 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3178 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
3179 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3181 switch (hw->mac.type) {
3182 case ixgbe_mac_82598EB:
3183 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
3185 case ixgbe_mac_82599EB:
3186 case ixgbe_mac_X540:
3187 case ixgbe_mac_X550:
3188 case ixgbe_mac_X550EM_x:
3189 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
3198 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
3199 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3201 switch (hw->mac.type) {
3202 case ixgbe_mac_82598EB:
3203 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
3204 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
3206 case ixgbe_mac_82599EB:
3207 case ixgbe_mac_X540:
3208 case ixgbe_mac_X550:
3209 case ixgbe_mac_X550EM_x:
3210 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
3211 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
3218 #define DCB_RX_CONFIG 1
3219 #define DCB_TX_CONFIG 1
3220 #define DCB_TX_PB 1024
3222 * ixgbe_dcb_hw_configure - Enable DCB and configure
3223 * general DCB in VT mode and non-VT mode parameters
3224 * @dev: pointer to rte_eth_dev structure
3225 * @dcb_config: pointer to ixgbe_dcb_config structure
3228 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
3229 struct ixgbe_dcb_config *dcb_config)
3232 uint8_t i,pfc_en,nb_tcs;
3234 uint8_t config_dcb_rx = 0;
3235 uint8_t config_dcb_tx = 0;
3236 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3237 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3238 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3239 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3240 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3241 struct ixgbe_dcb_tc_config *tc;
3242 uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3243 struct ixgbe_hw *hw =
3244 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3246 switch(dev->data->dev_conf.rxmode.mq_mode){
3247 case ETH_MQ_RX_VMDQ_DCB:
3248 dcb_config->vt_mode = true;
3249 if (hw->mac.type != ixgbe_mac_82598EB) {
3250 config_dcb_rx = DCB_RX_CONFIG;
3252 *get dcb and VT rx configuration parameters
3255 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
3256 /*Configure general VMDQ and DCB RX parameters*/
3257 ixgbe_vmdq_dcb_configure(dev);
3261 dcb_config->vt_mode = false;
3262 config_dcb_rx = DCB_RX_CONFIG;
3263 /* Get dcb TX configuration parameters from rte_eth_conf */
3264 ixgbe_dcb_rx_config(dev,dcb_config);
3265 /*Configure general DCB RX parameters*/
3266 ixgbe_dcb_rx_hw_config(hw, dcb_config);
3269 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
3272 switch (dev->data->dev_conf.txmode.mq_mode) {
3273 case ETH_MQ_TX_VMDQ_DCB:
3274 dcb_config->vt_mode = true;
3275 config_dcb_tx = DCB_TX_CONFIG;
3276 /* get DCB and VT TX configuration parameters from rte_eth_conf */
3277 ixgbe_dcb_vt_tx_config(dev,dcb_config);
3278 /*Configure general VMDQ and DCB TX parameters*/
3279 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
3283 dcb_config->vt_mode = false;
3284 config_dcb_tx = DCB_TX_CONFIG;
3285 /*get DCB TX configuration parameters from rte_eth_conf*/
3286 ixgbe_dcb_tx_config(dev,dcb_config);
3287 /*Configure general DCB TX parameters*/
3288 ixgbe_dcb_tx_hw_config(hw, dcb_config);
3291 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
3295 nb_tcs = dcb_config->num_tcs.pfc_tcs;
3297 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3298 if(nb_tcs == ETH_4_TCS) {
3299 /* Avoid un-configured priority mapping to TC0 */
3301 uint8_t mask = 0xFF;
3302 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
3303 mask = (uint8_t)(mask & (~ (1 << map[i])));
3304 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
3305 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
3309 /* Re-configure 4 TCs BW */
3310 for (i = 0; i < nb_tcs; i++) {
3311 tc = &dcb_config->tc_config[i];
3312 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
3313 (uint8_t)(100 / nb_tcs);
3314 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
3315 (uint8_t)(100 / nb_tcs);
3317 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3318 tc = &dcb_config->tc_config[i];
3319 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
3320 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
3325 /* Set RX buffer size */
3326 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3327 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
3328 for (i = 0 ; i < nb_tcs; i++) {
3329 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3331 /* zero alloc all unused TCs */
3332 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3333 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3337 /* Only support an equally distributed Tx packet buffer strategy. */
3338 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
3339 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
3340 for (i = 0; i < nb_tcs; i++) {
3341 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3342 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3344 /* Clear unused TCs, if any, to zero buffer size*/
3345 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3346 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3347 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3351 /*Calculates traffic class credits*/
3352 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3353 IXGBE_DCB_TX_CONFIG);
3354 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3355 IXGBE_DCB_RX_CONFIG);
3358 /* Unpack CEE standard containers */
3359 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
3360 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3361 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3362 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3363 /* Configure PG(ETS) RX */
3364 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3368 /* Unpack CEE standard containers */
3369 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3370 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3371 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3372 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3373 /* Configure PG(ETS) TX */
3374 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3377 /*Configure queue statistics registers*/
3378 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3380 /* Check if the PFC is supported */
3381 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3382 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3383 for (i = 0; i < nb_tcs; i++) {
3385 * If the TC count is 8,and the default high_water is 48,
3386 * the low_water is 16 as default.
3388 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3389 hw->fc.low_water[i] = pbsize / 4;
3390 /* Enable pfc for this TC */
3391 tc = &dcb_config->tc_config[i];
3392 tc->pfc = ixgbe_dcb_pfc_enabled;
3394 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3395 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3397 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3404 * ixgbe_configure_dcb - Configure DCB Hardware
3405 * @dev: pointer to rte_eth_dev
3407 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3409 struct ixgbe_dcb_config *dcb_cfg =
3410 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3411 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3413 PMD_INIT_FUNC_TRACE();
3415 /* check support mq_mode for DCB */
3416 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3417 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3420 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3423 /** Configure DCB hardware **/
3424 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3430 * VMDq only support for 10 GbE NIC.
3433 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3435 struct rte_eth_vmdq_rx_conf *cfg;
3436 struct ixgbe_hw *hw;
3437 enum rte_eth_nb_pools num_pools;
3438 uint32_t mrqc, vt_ctl, vlanctrl;
3442 PMD_INIT_FUNC_TRACE();
3443 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3444 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3445 num_pools = cfg->nb_queue_pools;
3447 ixgbe_rss_disable(dev);
3449 /* MRQC: enable vmdq */
3450 mrqc = IXGBE_MRQC_VMDQEN;
3451 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3453 /* PFVTCTL: turn on virtualisation and set the default pool */
3454 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3455 if (cfg->enable_default_pool)
3456 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3458 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3460 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3462 for (i = 0; i < (int)num_pools; i++) {
3463 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
3464 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
3467 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3468 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3469 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3470 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3472 /* VFTA - enable all vlan filters */
3473 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3474 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3476 /* VFRE: pool enabling for receive - 64 */
3477 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3478 if (num_pools == ETH_64_POOLS)
3479 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3482 * MPSAR - allow pools to read specific mac addresses
3483 * In this case, all pools should be able to read from mac addr 0
3485 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3486 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3488 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3489 for (i = 0; i < cfg->nb_pool_maps; i++) {
3490 /* set vlan id in VF register and set the valid bit */
3491 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3492 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3494 * Put the allowed pools in VFB reg. As we only have 16 or 64
3495 * pools, we only need to use the first half of the register
3498 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3499 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3500 (cfg->pool_map[i].pools & UINT32_MAX));
3502 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3503 ((cfg->pool_map[i].pools >> 32) \
3508 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3509 if (cfg->enable_loop_back) {
3510 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3511 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3512 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3515 IXGBE_WRITE_FLUSH(hw);
3519 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3520 * @hw: pointer to hardware structure
3523 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3528 PMD_INIT_FUNC_TRACE();
3529 /*PF VF Transmit Enable*/
3530 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3531 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3533 /* Disable the Tx desc arbiter so that MTQC can be changed */
3534 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3535 reg |= IXGBE_RTTDCS_ARBDIS;
3536 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3538 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3539 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3541 /* Disable drop for all queues */
3542 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3543 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3544 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3546 /* Enable the Tx desc arbiter */
3547 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3548 reg &= ~IXGBE_RTTDCS_ARBDIS;
3549 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3551 IXGBE_WRITE_FLUSH(hw);
3556 static int __attribute__((cold))
3557 ixgbe_alloc_rx_queue_mbufs(struct ixgbe_rx_queue *rxq)
3559 struct ixgbe_rx_entry *rxe = rxq->sw_ring;
3563 /* Initialize software ring entries */
3564 for (i = 0; i < rxq->nb_rx_desc; i++) {
3565 volatile union ixgbe_adv_rx_desc *rxd;
3566 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3568 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
3569 (unsigned) rxq->queue_id);
3573 rte_mbuf_refcnt_set(mbuf, 1);
3575 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
3577 mbuf->port = rxq->port_id;
3580 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3581 rxd = &rxq->rx_ring[i];
3582 rxd->read.hdr_addr = 0;
3583 rxd->read.pkt_addr = dma_addr;
3591 ixgbe_config_vf_rss(struct rte_eth_dev *dev)
3593 struct ixgbe_hw *hw;
3596 ixgbe_rss_configure(dev);
3598 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3600 /* MRQC: enable VF RSS */
3601 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
3602 mrqc &= ~IXGBE_MRQC_MRQE_MASK;
3603 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3605 mrqc |= IXGBE_MRQC_VMDQRSS64EN;
3609 mrqc |= IXGBE_MRQC_VMDQRSS32EN;
3613 PMD_INIT_LOG(ERR, "Invalid pool number in IOV mode with VMDQ RSS");
3617 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3623 ixgbe_config_vf_default(struct rte_eth_dev *dev)
3625 struct ixgbe_hw *hw =
3626 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3628 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3630 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3635 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3636 IXGBE_MRQC_VMDQRT4TCEN);
3640 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3641 IXGBE_MRQC_VMDQRT8TCEN);
3645 "invalid pool number in IOV mode");
3652 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3654 struct ixgbe_hw *hw =
3655 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3657 if (hw->mac.type == ixgbe_mac_82598EB)
3660 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3662 * SRIOV inactive scheme
3663 * any DCB/RSS w/o VMDq multi-queue setting
3665 switch (dev->data->dev_conf.rxmode.mq_mode) {
3667 ixgbe_rss_configure(dev);
3670 case ETH_MQ_RX_VMDQ_DCB:
3671 ixgbe_vmdq_dcb_configure(dev);
3674 case ETH_MQ_RX_VMDQ_ONLY:
3675 ixgbe_vmdq_rx_hw_configure(dev);
3678 case ETH_MQ_RX_NONE:
3679 /* if mq_mode is none, disable rss mode.*/
3680 default: ixgbe_rss_disable(dev);
3684 * SRIOV active scheme
3685 * Support RSS together with VMDq & SRIOV
3687 switch (dev->data->dev_conf.rxmode.mq_mode) {
3689 case ETH_MQ_RX_VMDQ_RSS:
3690 ixgbe_config_vf_rss(dev);
3693 /* FIXME if support DCB/RSS together with VMDq & SRIOV */
3694 case ETH_MQ_RX_VMDQ_DCB:
3695 case ETH_MQ_RX_VMDQ_DCB_RSS:
3697 "Could not support DCB with VMDq & SRIOV");
3700 ixgbe_config_vf_default(dev);
3709 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3711 struct ixgbe_hw *hw =
3712 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3716 if (hw->mac.type == ixgbe_mac_82598EB)
3719 /* disable arbiter before setting MTQC */
3720 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3721 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3722 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3724 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3726 * SRIOV inactive scheme
3727 * any DCB w/o VMDq multi-queue setting
3729 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3730 ixgbe_vmdq_tx_hw_configure(hw);
3732 mtqc = IXGBE_MTQC_64Q_1PB;
3733 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3736 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3739 * SRIOV active scheme
3740 * FIXME if support DCB together with VMDq & SRIOV
3743 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3746 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3749 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3753 mtqc = IXGBE_MTQC_64Q_1PB;
3754 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
3756 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3759 /* re-enable arbiter */
3760 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3761 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3767 * ixgbe_get_rscctl_maxdesc - Calculate the RSCCTL[n].MAXDESC for PF
3769 * Return the RSCCTL[n].MAXDESC for 82599 and x540 PF devices according to the
3770 * spec rev. 3.0 chapter 8.2.3.8.13.
3772 * @pool Memory pool of the Rx queue
3774 static inline uint32_t
3775 ixgbe_get_rscctl_maxdesc(struct rte_mempool *pool)
3777 struct rte_pktmbuf_pool_private *mp_priv = rte_mempool_get_priv(pool);
3779 /* MAXDESC * SRRCTL.BSIZEPKT must not exceed 64 KB minus one */
3782 (mp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM);
3785 return IXGBE_RSCCTL_MAXDESC_16;
3786 else if (maxdesc >= 8)
3787 return IXGBE_RSCCTL_MAXDESC_8;
3788 else if (maxdesc >= 4)
3789 return IXGBE_RSCCTL_MAXDESC_4;
3791 return IXGBE_RSCCTL_MAXDESC_1;
3795 * ixgbe_set_ivar - Setup the correct IVAR register for a particular MSIX
3798 * (Taken from FreeBSD tree)
3799 * (yes this is all very magic and confusing :)
3802 * @entry the register array entry
3803 * @vector the MSIX vector for this queue
3807 ixgbe_set_ivar(struct rte_eth_dev *dev, u8 entry, u8 vector, s8 type)
3809 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3812 vector |= IXGBE_IVAR_ALLOC_VAL;
3814 switch (hw->mac.type) {
3816 case ixgbe_mac_82598EB:
3818 entry = IXGBE_IVAR_OTHER_CAUSES_INDEX;
3820 entry += (type * 64);
3821 index = (entry >> 2) & 0x1F;
3822 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
3823 ivar &= ~(0xFF << (8 * (entry & 0x3)));
3824 ivar |= (vector << (8 * (entry & 0x3)));
3825 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
3828 case ixgbe_mac_82599EB:
3829 case ixgbe_mac_X540:
3830 if (type == -1) { /* MISC IVAR */
3831 index = (entry & 1) * 8;
3832 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
3833 ivar &= ~(0xFF << index);
3834 ivar |= (vector << index);
3835 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
3836 } else { /* RX/TX IVARS */
3837 index = (16 * (entry & 1)) + (8 * type);
3838 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1));
3839 ivar &= ~(0xFF << index);
3840 ivar |= (vector << index);
3841 IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar);
3851 void __attribute__((cold))
3852 ixgbe_set_rx_function(struct rte_eth_dev *dev)
3854 uint16_t i, rx_using_sse;
3855 struct ixgbe_adapter *adapter =
3856 (struct ixgbe_adapter *)dev->data->dev_private;
3859 * In order to allow Vector Rx there are a few configuration
3860 * conditions to be met and Rx Bulk Allocation should be allowed.
3862 if (ixgbe_rx_vec_dev_conf_condition_check(dev) ||
3863 !adapter->rx_bulk_alloc_allowed) {
3864 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx "
3865 "preconditions or RTE_IXGBE_INC_VECTOR is "
3867 dev->data->port_id);
3869 adapter->rx_vec_allowed = false;
3873 * Initialize the appropriate LRO callback.
3875 * If all queues satisfy the bulk allocation preconditions
3876 * (hw->rx_bulk_alloc_allowed is TRUE) then we may use bulk allocation.
3877 * Otherwise use a single allocation version.
3879 if (dev->data->lro) {
3880 if (adapter->rx_bulk_alloc_allowed) {
3881 PMD_INIT_LOG(DEBUG, "LRO is requested. Using a bulk "
3882 "allocation version");
3883 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
3885 PMD_INIT_LOG(DEBUG, "LRO is requested. Using a single "
3886 "allocation version");
3887 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
3889 } else if (dev->data->scattered_rx) {
3891 * Set the non-LRO scattered callback: there are Vector and
3892 * single allocation versions.
3894 if (adapter->rx_vec_allowed) {
3895 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
3896 "callback (port=%d).",
3897 dev->data->port_id);
3899 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3900 } else if (adapter->rx_bulk_alloc_allowed) {
3901 PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
3902 "allocation callback (port=%d).",
3903 dev->data->port_id);
3904 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
3906 PMD_INIT_LOG(DEBUG, "Using Regualr (non-vector, "
3907 "single allocation) "
3908 "Scattered Rx callback "
3910 dev->data->port_id);
3912 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
3915 * Below we set "simple" callbacks according to port/queues parameters.
3916 * If parameters allow we are going to choose between the following
3920 * - Single buffer allocation (the simplest one)
3922 } else if (adapter->rx_vec_allowed) {
3923 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
3924 "burst size no less than 32.");
3926 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
3927 } else if (adapter->rx_bulk_alloc_allowed) {
3928 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3929 "satisfied. Rx Burst Bulk Alloc function "
3930 "will be used on port=%d.",
3931 dev->data->port_id);
3933 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
3935 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
3936 "satisfied, or Scattered Rx is requested "
3938 dev->data->port_id);
3940 dev->rx_pkt_burst = ixgbe_recv_pkts;
3943 /* Propagate information about RX function choice through all queues. */
3946 (dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec ||
3947 dev->rx_pkt_burst == ixgbe_recv_pkts_vec);
3949 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3950 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
3951 rxq->rx_using_sse = rx_using_sse;
3956 * ixgbe_set_rsc - configure RSC related port HW registers
3958 * Configures the port's RSC related registers according to the 4.6.7.2 chapter
3959 * of 82599 Spec (x540 configuration is virtually the same).
3963 * Returns 0 in case of success or a non-zero error code
3966 ixgbe_set_rsc(struct rte_eth_dev *dev)
3968 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
3969 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3970 struct rte_eth_dev_info dev_info = { 0 };
3971 bool rsc_capable = false;
3976 dev->dev_ops->dev_infos_get(dev, &dev_info);
3977 if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_TCP_LRO)
3980 if (!rsc_capable && rx_conf->enable_lro) {
3981 PMD_INIT_LOG(CRIT, "LRO is requested on HW that doesn't "
3986 /* RSC global configuration (chapter 4.6.7.2.1 of 82599 Spec) */
3988 if (!rx_conf->hw_strip_crc && rx_conf->enable_lro) {
3990 * According to chapter of 4.6.7.2.1 of the Spec Rev.
3991 * 3.0 RSC configuration requires HW CRC stripping being
3992 * enabled. If user requested both HW CRC stripping off
3993 * and RSC on - return an error.
3995 PMD_INIT_LOG(CRIT, "LRO can't be enabled when HW CRC "
4000 /* RFCTL configuration */
4002 uint32_t rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4003 if (rx_conf->enable_lro)
4005 * Since NFS packets coalescing is not supported - clear
4006 * RFCTL.NFSW_DIS and RFCTL.NFSR_DIS when RSC is
4009 rfctl &= ~(IXGBE_RFCTL_RSC_DIS | IXGBE_RFCTL_NFSW_DIS |
4010 IXGBE_RFCTL_NFSR_DIS);
4012 rfctl |= IXGBE_RFCTL_RSC_DIS;
4014 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4017 /* If LRO hasn't been requested - we are done here. */
4018 if (!rx_conf->enable_lro)
4021 /* Set RDRXCTL.RSCACKC bit */
4022 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4023 rdrxctl |= IXGBE_RDRXCTL_RSCACKC;
4024 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4026 /* Per-queue RSC configuration (chapter 4.6.7.2.2 of 82599 Spec) */
4027 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4028 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4030 IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxq->reg_idx));
4032 IXGBE_READ_REG(hw, IXGBE_RSCCTL(rxq->reg_idx));
4034 IXGBE_READ_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx));
4036 IXGBE_READ_REG(hw, IXGBE_EITR(rxq->reg_idx));
4039 * ixgbe PMD doesn't support header-split at the moment.
4041 * Following the 4.6.7.2.1 chapter of the 82599/x540
4042 * Spec if RSC is enabled the SRRCTL[n].BSIZEHEADER
4043 * should be configured even if header split is not
4044 * enabled. We will configure it 128 bytes following the
4045 * recommendation in the spec.
4047 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
4048 srrctl |= (128 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4049 IXGBE_SRRCTL_BSIZEHDR_MASK;
4052 * TODO: Consider setting the Receive Descriptor Minimum
4053 * Threshold Size for an RSC case. This is not an obviously
4054 * beneficiary option but the one worth considering...
4057 rscctl |= IXGBE_RSCCTL_RSCEN;
4058 rscctl |= ixgbe_get_rscctl_maxdesc(rxq->mb_pool);
4059 psrtype |= IXGBE_PSRTYPE_TCPHDR;
4062 * RSC: Set ITR interval corresponding to 2K ints/s.
4064 * Full-sized RSC aggregations for a 10Gb/s link will
4065 * arrive at about 20K aggregation/s rate.
4067 * 2K inst/s rate will make only 10% of the
4068 * aggregations to be closed due to the interrupt timer
4069 * expiration for a streaming at wire-speed case.
4071 * For a sparse streaming case this setting will yield
4072 * at most 500us latency for a single RSC aggregation.
4074 eitr &= ~IXGBE_EITR_ITR_INT_MASK;
4075 eitr |= IXGBE_EITR_INTERVAL_US(500) | IXGBE_EITR_CNT_WDIS;
4077 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4078 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(rxq->reg_idx), rscctl);
4079 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
4080 IXGBE_WRITE_REG(hw, IXGBE_EITR(rxq->reg_idx), eitr);
4083 * RSC requires the mapping of the queue to the
4086 ixgbe_set_ivar(dev, rxq->reg_idx, i, 0);
4091 PMD_INIT_LOG(DEBUG, "enabling LRO mode");
4097 * Initializes Receive Unit.
4099 int __attribute__((cold))
4100 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
4102 struct ixgbe_hw *hw;
4103 struct ixgbe_rx_queue *rxq;
4114 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4117 PMD_INIT_FUNC_TRACE();
4118 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4121 * Make sure receives are disabled while setting
4122 * up the RX context (registers, descriptor rings, etc.).
4124 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4125 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4127 /* Enable receipt of broadcasted frames */
4128 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4129 fctrl |= IXGBE_FCTRL_BAM;
4130 fctrl |= IXGBE_FCTRL_DPF;
4131 fctrl |= IXGBE_FCTRL_PMCF;
4132 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4135 * Configure CRC stripping, if any.
4137 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4138 if (rx_conf->hw_strip_crc)
4139 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
4141 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
4144 * Configure jumbo frame support, if any.
4146 if (rx_conf->jumbo_frame == 1) {
4147 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4148 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4149 maxfrs &= 0x0000FFFF;
4150 maxfrs |= (rx_conf->max_rx_pkt_len << 16);
4151 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4153 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4156 * If loopback mode is configured for 82599, set LPBK bit.
4158 if (hw->mac.type == ixgbe_mac_82599EB &&
4159 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
4160 hlreg0 |= IXGBE_HLREG0_LPBK;
4162 hlreg0 &= ~IXGBE_HLREG0_LPBK;
4164 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4166 /* Setup RX queues */
4167 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4168 rxq = dev->data->rx_queues[i];
4171 * Reset crc_len in case it was changed after queue setup by a
4172 * call to configure.
4174 rxq->crc_len = rx_conf->hw_strip_crc ? 0 : ETHER_CRC_LEN;
4176 /* Setup the Base and Length of the Rx Descriptor Rings */
4177 bus_addr = rxq->rx_ring_phys_addr;
4178 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
4179 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4180 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
4181 (uint32_t)(bus_addr >> 32));
4182 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
4183 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4184 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
4185 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
4187 /* Configure the SRRCTL register */
4188 #ifdef RTE_HEADER_SPLIT_ENABLE
4190 * Configure Header Split
4192 if (rx_conf->header_split) {
4193 if (hw->mac.type == ixgbe_mac_82599EB) {
4194 /* Must setup the PSRTYPE register */
4196 psrtype = IXGBE_PSRTYPE_TCPHDR |
4197 IXGBE_PSRTYPE_UDPHDR |
4198 IXGBE_PSRTYPE_IPV4HDR |
4199 IXGBE_PSRTYPE_IPV6HDR;
4200 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
4202 srrctl = ((rx_conf->split_hdr_size <<
4203 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4204 IXGBE_SRRCTL_BSIZEHDR_MASK);
4205 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4208 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4210 /* Set if packets are dropped when no descriptors available */
4212 srrctl |= IXGBE_SRRCTL_DROP_EN;
4215 * Configure the RX buffer size in the BSIZEPACKET field of
4216 * the SRRCTL register of the queue.
4217 * The value is in 1 KB resolution. Valid values can be from
4220 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
4221 RTE_PKTMBUF_HEADROOM);
4222 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4223 IXGBE_SRRCTL_BSIZEPKT_MASK);
4225 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4227 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4228 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4230 /* It adds dual VLAN length for supporting dual VLAN */
4231 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4232 2 * IXGBE_VLAN_TAG_SIZE > buf_size)
4233 dev->data->scattered_rx = 1;
4236 if (rx_conf->enable_scatter)
4237 dev->data->scattered_rx = 1;
4240 * Device configured with multiple RX queues.
4242 ixgbe_dev_mq_rx_configure(dev);
4245 * Setup the Checksum Register.
4246 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
4247 * Enable IP/L4 checkum computation by hardware if requested to do so.
4249 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
4250 rxcsum |= IXGBE_RXCSUM_PCSD;
4251 if (rx_conf->hw_ip_checksum)
4252 rxcsum |= IXGBE_RXCSUM_IPPCSE;
4254 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
4256 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
4258 if (hw->mac.type == ixgbe_mac_82599EB ||
4259 hw->mac.type == ixgbe_mac_X540) {
4260 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4261 if (rx_conf->hw_strip_crc)
4262 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4264 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
4265 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4266 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4269 rc = ixgbe_set_rsc(dev);
4273 ixgbe_set_rx_function(dev);
4279 * Initializes Transmit Unit.
4281 void __attribute__((cold))
4282 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
4284 struct ixgbe_hw *hw;
4285 struct ixgbe_tx_queue *txq;
4291 PMD_INIT_FUNC_TRACE();
4292 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4294 /* Enable TX CRC (checksum offload requirement) and hw padding
4295 * (TSO requirement) */
4296 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4297 hlreg0 |= (IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);
4298 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4300 /* Setup the Base and Length of the Tx Descriptor Rings */
4301 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4302 txq = dev->data->tx_queues[i];
4304 bus_addr = txq->tx_ring_phys_addr;
4305 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
4306 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4307 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
4308 (uint32_t)(bus_addr >> 32));
4309 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
4310 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4311 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4312 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
4313 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
4316 * Disable Tx Head Writeback RO bit, since this hoses
4317 * bookkeeping if things aren't delivered in order.
4319 switch (hw->mac.type) {
4320 case ixgbe_mac_82598EB:
4321 txctrl = IXGBE_READ_REG(hw,
4322 IXGBE_DCA_TXCTRL(txq->reg_idx));
4323 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4324 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
4328 case ixgbe_mac_82599EB:
4329 case ixgbe_mac_X540:
4330 case ixgbe_mac_X550:
4331 case ixgbe_mac_X550EM_x:
4333 txctrl = IXGBE_READ_REG(hw,
4334 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
4335 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4336 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
4342 /* Device configured with multiple TX queues. */
4343 ixgbe_dev_mq_tx_configure(dev);
4347 * Set up link for 82599 loopback mode Tx->Rx.
4349 static inline void __attribute__((cold))
4350 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
4352 PMD_INIT_FUNC_TRACE();
4354 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
4355 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
4357 PMD_INIT_LOG(ERR, "Could not enable loopback mode");
4366 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
4367 ixgbe_reset_pipeline_82599(hw);
4369 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
4375 * Start Transmit and Receive Units.
4377 int __attribute__((cold))
4378 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
4380 struct ixgbe_hw *hw;
4381 struct ixgbe_tx_queue *txq;
4382 struct ixgbe_rx_queue *rxq;
4389 PMD_INIT_FUNC_TRACE();
4390 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4392 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4393 txq = dev->data->tx_queues[i];
4394 /* Setup Transmit Threshold Registers */
4395 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4396 txdctl |= txq->pthresh & 0x7F;
4397 txdctl |= ((txq->hthresh & 0x7F) << 8);
4398 txdctl |= ((txq->wthresh & 0x7F) << 16);
4399 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4402 if (hw->mac.type != ixgbe_mac_82598EB) {
4403 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
4404 dmatxctl |= IXGBE_DMATXCTL_TE;
4405 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
4408 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4409 txq = dev->data->tx_queues[i];
4410 if (!txq->tx_deferred_start) {
4411 ret = ixgbe_dev_tx_queue_start(dev, i);
4417 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4418 rxq = dev->data->rx_queues[i];
4419 if (!rxq->rx_deferred_start) {
4420 ret = ixgbe_dev_rx_queue_start(dev, i);
4426 /* Enable Receive engine */
4427 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4428 if (hw->mac.type == ixgbe_mac_82598EB)
4429 rxctrl |= IXGBE_RXCTRL_DMBYPS;
4430 rxctrl |= IXGBE_RXCTRL_RXEN;
4431 hw->mac.ops.enable_rx_dma(hw, rxctrl);
4433 /* If loopback mode is enabled for 82599, set up the link accordingly */
4434 if (hw->mac.type == ixgbe_mac_82599EB &&
4435 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
4436 ixgbe_setup_loopback_link_82599(hw);
4442 * Start Receive Units for specified queue.
4444 int __attribute__((cold))
4445 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4447 struct ixgbe_hw *hw;
4448 struct ixgbe_rx_queue *rxq;
4452 PMD_INIT_FUNC_TRACE();
4453 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4455 if (rx_queue_id < dev->data->nb_rx_queues) {
4456 rxq = dev->data->rx_queues[rx_queue_id];
4458 /* Allocate buffers for descriptor rings */
4459 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
4460 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
4464 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4465 rxdctl |= IXGBE_RXDCTL_ENABLE;
4466 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
4468 /* Wait until RX Enable ready */
4469 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4472 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4473 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4475 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d",
4478 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
4479 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
4487 * Stop Receive Units for specified queue.
4489 int __attribute__((cold))
4490 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4492 struct ixgbe_hw *hw;
4493 struct ixgbe_adapter *adapter =
4494 (struct ixgbe_adapter *)dev->data->dev_private;
4495 struct ixgbe_rx_queue *rxq;
4499 PMD_INIT_FUNC_TRACE();
4500 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4502 if (rx_queue_id < dev->data->nb_rx_queues) {
4503 rxq = dev->data->rx_queues[rx_queue_id];
4505 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4506 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
4507 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
4509 /* Wait until RX Enable ready */
4510 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4513 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4514 } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));
4516 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d",
4519 rte_delay_us(RTE_IXGBE_WAIT_100_US);
4521 ixgbe_rx_queue_release_mbufs(rxq);
4522 ixgbe_reset_rx_queue(adapter, rxq);
4531 * Start Transmit Units for specified queue.
4533 int __attribute__((cold))
4534 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4536 struct ixgbe_hw *hw;
4537 struct ixgbe_tx_queue *txq;
4541 PMD_INIT_FUNC_TRACE();
4542 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4544 if (tx_queue_id < dev->data->nb_tx_queues) {
4545 txq = dev->data->tx_queues[tx_queue_id];
4546 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4547 txdctl |= IXGBE_TXDCTL_ENABLE;
4548 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4550 /* Wait until TX Enable ready */
4551 if (hw->mac.type == ixgbe_mac_82599EB) {
4552 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4555 txdctl = IXGBE_READ_REG(hw,
4556 IXGBE_TXDCTL(txq->reg_idx));
4557 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4559 PMD_INIT_LOG(ERR, "Could not enable "
4560 "Tx Queue %d", tx_queue_id);
4563 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
4564 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
4572 * Stop Transmit Units for specified queue.
4574 int __attribute__((cold))
4575 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4577 struct ixgbe_hw *hw;
4578 struct ixgbe_tx_queue *txq;
4580 uint32_t txtdh, txtdt;
4583 PMD_INIT_FUNC_TRACE();
4584 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4586 if (tx_queue_id < dev->data->nb_tx_queues) {
4587 txq = dev->data->tx_queues[tx_queue_id];
4589 /* Wait until TX queue is empty */
4590 if (hw->mac.type == ixgbe_mac_82599EB) {
4591 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4593 rte_delay_us(RTE_IXGBE_WAIT_100_US);
4594 txtdh = IXGBE_READ_REG(hw,
4595 IXGBE_TDH(txq->reg_idx));
4596 txtdt = IXGBE_READ_REG(hw,
4597 IXGBE_TDT(txq->reg_idx));
4598 } while (--poll_ms && (txtdh != txtdt));
4600 PMD_INIT_LOG(ERR, "Tx Queue %d is not empty "
4601 "when stopping.", tx_queue_id);
4604 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4605 txdctl &= ~IXGBE_TXDCTL_ENABLE;
4606 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4608 /* Wait until TX Enable ready */
4609 if (hw->mac.type == ixgbe_mac_82599EB) {
4610 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4613 txdctl = IXGBE_READ_REG(hw,
4614 IXGBE_TXDCTL(txq->reg_idx));
4615 } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));
4617 PMD_INIT_LOG(ERR, "Could not disable "
4618 "Tx Queue %d", tx_queue_id);
4621 if (txq->ops != NULL) {
4622 txq->ops->release_mbufs(txq);
4623 txq->ops->reset(txq);
4632 * [VF] Initializes Receive Unit.
4634 int __attribute__((cold))
4635 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
4637 struct ixgbe_hw *hw;
4638 struct ixgbe_rx_queue *rxq;
4640 uint32_t srrctl, psrtype = 0;
4645 PMD_INIT_FUNC_TRACE();
4646 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4648 if (rte_is_power_of_2(dev->data->nb_rx_queues) == 0) {
4649 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4650 "it should be power of 2");
4654 if (dev->data->nb_rx_queues > hw->mac.max_rx_queues) {
4655 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4656 "it should be equal to or less than %d",
4657 hw->mac.max_rx_queues);
4662 * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
4663 * disables the VF receipt of packets if the PF MTU is > 1500.
4664 * This is done to deal with 82599 limitations that imposes
4665 * the PF and all VFs to share the same MTU.
4666 * Then, the PF driver enables again the VF receipt of packet when
4667 * the VF driver issues a IXGBE_VF_SET_LPE request.
4668 * In the meantime, the VF device cannot be used, even if the VF driver
4669 * and the Guest VM network stack are ready to accept packets with a
4670 * size up to the PF MTU.
4671 * As a work-around to this PF behaviour, force the call to
4672 * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
4673 * VF packets received can work in all cases.
4675 ixgbevf_rlpml_set_vf(hw,
4676 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
4678 /* Setup RX queues */
4679 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4680 rxq = dev->data->rx_queues[i];
4682 /* Allocate buffers for descriptor rings */
4683 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
4687 /* Setup the Base and Length of the Rx Descriptor Rings */
4688 bus_addr = rxq->rx_ring_phys_addr;
4690 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
4691 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4692 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
4693 (uint32_t)(bus_addr >> 32));
4694 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
4695 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4696 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
4697 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
4700 /* Configure the SRRCTL register */
4701 #ifdef RTE_HEADER_SPLIT_ENABLE
4703 * Configure Header Split
4705 if (dev->data->dev_conf.rxmode.header_split) {
4706 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
4707 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4708 IXGBE_SRRCTL_BSIZEHDR_MASK);
4709 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4712 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4714 /* Set if packets are dropped when no descriptors available */
4716 srrctl |= IXGBE_SRRCTL_DROP_EN;
4719 * Configure the RX buffer size in the BSIZEPACKET field of
4720 * the SRRCTL register of the queue.
4721 * The value is in 1 KB resolution. Valid values can be from
4724 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
4725 RTE_PKTMBUF_HEADROOM);
4726 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4727 IXGBE_SRRCTL_BSIZEPKT_MASK);
4730 * VF modification to write virtual function SRRCTL register
4732 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
4734 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4735 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4737 if (dev->data->dev_conf.rxmode.enable_scatter ||
4738 /* It adds dual VLAN length for supporting dual VLAN */
4739 (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4740 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
4741 if (!dev->data->scattered_rx)
4742 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
4743 dev->data->scattered_rx = 1;
4747 #ifdef RTE_HEADER_SPLIT_ENABLE
4748 if (dev->data->dev_conf.rxmode.header_split)
4749 /* Must setup the PSRTYPE register */
4750 psrtype = IXGBE_PSRTYPE_TCPHDR |
4751 IXGBE_PSRTYPE_UDPHDR |
4752 IXGBE_PSRTYPE_IPV4HDR |
4753 IXGBE_PSRTYPE_IPV6HDR;
4756 /* Set RQPL for VF RSS according to max Rx queue */
4757 psrtype |= (dev->data->nb_rx_queues >> 1) <<
4758 IXGBE_PSRTYPE_RQPL_SHIFT;
4759 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
4761 ixgbe_set_rx_function(dev);
4767 * [VF] Initializes Transmit Unit.
4769 void __attribute__((cold))
4770 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
4772 struct ixgbe_hw *hw;
4773 struct ixgbe_tx_queue *txq;
4778 PMD_INIT_FUNC_TRACE();
4779 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4781 /* Setup the Base and Length of the Tx Descriptor Rings */
4782 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4783 txq = dev->data->tx_queues[i];
4784 bus_addr = txq->tx_ring_phys_addr;
4785 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
4786 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4787 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
4788 (uint32_t)(bus_addr >> 32));
4789 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
4790 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4791 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4792 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
4793 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
4796 * Disable Tx Head Writeback RO bit, since this hoses
4797 * bookkeeping if things aren't delivered in order.
4799 txctrl = IXGBE_READ_REG(hw,
4800 IXGBE_VFDCA_TXCTRL(i));
4801 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4802 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
4808 * [VF] Start Transmit and Receive Units.
4810 void __attribute__((cold))
4811 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
4813 struct ixgbe_hw *hw;
4814 struct ixgbe_tx_queue *txq;
4815 struct ixgbe_rx_queue *rxq;
4821 PMD_INIT_FUNC_TRACE();
4822 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4824 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4825 txq = dev->data->tx_queues[i];
4826 /* Setup Transmit Threshold Registers */
4827 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4828 txdctl |= txq->pthresh & 0x7F;
4829 txdctl |= ((txq->hthresh & 0x7F) << 8);
4830 txdctl |= ((txq->wthresh & 0x7F) << 16);
4831 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4834 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4836 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4837 txdctl |= IXGBE_TXDCTL_ENABLE;
4838 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4841 /* Wait until TX Enable ready */
4844 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4845 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4847 PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
4849 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4851 rxq = dev->data->rx_queues[i];
4853 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4854 rxdctl |= IXGBE_RXDCTL_ENABLE;
4855 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
4857 /* Wait until RX Enable ready */
4861 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4862 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4864 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
4866 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);
4871 /* Stubs needed for linkage when CONFIG_RTE_IXGBE_INC_VECTOR is set to 'n' */
4872 int __attribute__((weak))
4873 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
4878 uint16_t __attribute__((weak))
4879 ixgbe_recv_pkts_vec(
4880 void __rte_unused *rx_queue,
4881 struct rte_mbuf __rte_unused **rx_pkts,
4882 uint16_t __rte_unused nb_pkts)
4887 uint16_t __attribute__((weak))
4888 ixgbe_recv_scattered_pkts_vec(
4889 void __rte_unused *rx_queue,
4890 struct rte_mbuf __rte_unused **rx_pkts,
4891 uint16_t __rte_unused nb_pkts)
4896 int __attribute__((weak))
4897 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue __rte_unused *rxq)