1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation.
3 * Copyright 2014 6WIND S.A.
17 #include <rte_byteorder.h>
18 #include <rte_common.h>
19 #include <rte_cycles.h>
21 #include <rte_debug.h>
22 #include <rte_interrupts.h>
24 #include <rte_memory.h>
25 #include <rte_memzone.h>
26 #include <rte_launch.h>
28 #include <rte_per_lcore.h>
29 #include <rte_lcore.h>
30 #include <rte_atomic.h>
31 #include <rte_branch_prediction.h>
32 #include <rte_mempool.h>
33 #include <rte_malloc.h>
35 #include <rte_ether.h>
36 #include <rte_ethdev_driver.h>
37 #include <rte_prefetch.h>
41 #include <rte_string_fns.h>
42 #include <rte_errno.h>
46 #include "ixgbe_logs.h"
47 #include "base/ixgbe_api.h"
48 #include "base/ixgbe_vf.h"
49 #include "ixgbe_ethdev.h"
50 #include "base/ixgbe_dcb.h"
51 #include "base/ixgbe_common.h"
52 #include "ixgbe_rxtx.h"
54 #ifdef RTE_LIBRTE_IEEE1588
55 #define IXGBE_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
57 #define IXGBE_TX_IEEE1588_TMST 0
59 /* Bit Mask to indicate what bits required for building TX context */
60 #define IXGBE_TX_OFFLOAD_MASK ( \
66 PKT_TX_OUTER_IP_CKSUM | \
67 PKT_TX_SEC_OFFLOAD | \
68 IXGBE_TX_IEEE1588_TMST)
70 #define IXGBE_TX_OFFLOAD_NOTSUP_MASK \
71 (PKT_TX_OFFLOAD_MASK ^ IXGBE_TX_OFFLOAD_MASK)
74 #define RTE_PMD_USE_PREFETCH
77 #ifdef RTE_PMD_USE_PREFETCH
79 * Prefetch a cache line into all cache levels.
81 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
83 #define rte_ixgbe_prefetch(p) do {} while (0)
86 #ifdef RTE_IXGBE_INC_VECTOR
87 uint16_t ixgbe_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
91 /*********************************************************************
95 **********************************************************************/
98 * Check for descriptors with their DD bit set and free mbufs.
99 * Return the total number of buffers freed.
101 static __rte_always_inline int
102 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
104 struct ixgbe_tx_entry *txep;
107 struct rte_mbuf *m, *free[RTE_IXGBE_TX_MAX_FREE_BUF_SZ];
109 /* check DD bit on threshold descriptor */
110 status = txq->tx_ring[txq->tx_next_dd].wb.status;
111 if (!(status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD)))
115 * first buffer to free from S/W ring is at index
116 * tx_next_dd - (tx_rs_thresh-1)
118 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
120 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
121 /* free buffers one at a time */
122 m = rte_pktmbuf_prefree_seg(txep->mbuf);
125 if (unlikely(m == NULL))
128 if (nb_free >= RTE_IXGBE_TX_MAX_FREE_BUF_SZ ||
129 (nb_free > 0 && m->pool != free[0]->pool)) {
130 rte_mempool_put_bulk(free[0]->pool,
131 (void **)free, nb_free);
139 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
141 /* buffers were freed, update counters */
142 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
143 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
144 if (txq->tx_next_dd >= txq->nb_tx_desc)
145 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
147 return txq->tx_rs_thresh;
150 /* Populate 4 descriptors with data from 4 mbufs */
152 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
154 uint64_t buf_dma_addr;
158 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
159 buf_dma_addr = rte_mbuf_data_iova(*pkts);
160 pkt_len = (*pkts)->data_len;
162 /* write data to descriptor */
163 txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
165 txdp->read.cmd_type_len =
166 rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
168 txdp->read.olinfo_status =
169 rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
171 rte_prefetch0(&(*pkts)->pool);
175 /* Populate 1 descriptor with data from 1 mbuf */
177 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
179 uint64_t buf_dma_addr;
182 buf_dma_addr = rte_mbuf_data_iova(*pkts);
183 pkt_len = (*pkts)->data_len;
185 /* write data to descriptor */
186 txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
187 txdp->read.cmd_type_len =
188 rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
189 txdp->read.olinfo_status =
190 rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
191 rte_prefetch0(&(*pkts)->pool);
195 * Fill H/W descriptor ring with mbuf data.
196 * Copy mbuf pointers to the S/W ring.
199 ixgbe_tx_fill_hw_ring(struct ixgbe_tx_queue *txq, struct rte_mbuf **pkts,
202 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
203 struct ixgbe_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
204 const int N_PER_LOOP = 4;
205 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
206 int mainpart, leftover;
210 * Process most of the packets in chunks of N pkts. Any
211 * leftover packets will get processed one at a time.
213 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
214 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
215 for (i = 0; i < mainpart; i += N_PER_LOOP) {
216 /* Copy N mbuf pointers to the S/W ring */
217 for (j = 0; j < N_PER_LOOP; ++j) {
218 (txep + i + j)->mbuf = *(pkts + i + j);
220 tx4(txdp + i, pkts + i);
223 if (unlikely(leftover > 0)) {
224 for (i = 0; i < leftover; ++i) {
225 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
226 tx1(txdp + mainpart + i, pkts + mainpart + i);
231 static inline uint16_t
232 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
235 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
236 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
240 * Begin scanning the H/W ring for done descriptors when the
241 * number of available descriptors drops below tx_free_thresh. For
242 * each done descriptor, free the associated buffer.
244 if (txq->nb_tx_free < txq->tx_free_thresh)
245 ixgbe_tx_free_bufs(txq);
247 /* Only use descriptors that are available */
248 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
249 if (unlikely(nb_pkts == 0))
252 /* Use exactly nb_pkts descriptors */
253 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
256 * At this point, we know there are enough descriptors in the
257 * ring to transmit all the packets. This assumes that each
258 * mbuf contains a single segment, and that no new offloads
259 * are expected, which would require a new context descriptor.
263 * See if we're going to wrap-around. If so, handle the top
264 * of the descriptor ring first, then do the bottom. If not,
265 * the processing looks just like the "bottom" part anyway...
267 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
268 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
269 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
272 * We know that the last descriptor in the ring will need to
273 * have its RS bit set because tx_rs_thresh has to be
274 * a divisor of the ring size
276 tx_r[txq->tx_next_rs].read.cmd_type_len |=
277 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
278 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
283 /* Fill H/W descriptor ring with mbuf data */
284 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
285 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
288 * Determine if RS bit should be set
289 * This is what we actually want:
290 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
291 * but instead of subtracting 1 and doing >=, we can just do
292 * greater than without subtracting.
294 if (txq->tx_tail > txq->tx_next_rs) {
295 tx_r[txq->tx_next_rs].read.cmd_type_len |=
296 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
297 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
299 if (txq->tx_next_rs >= txq->nb_tx_desc)
300 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
304 * Check for wrap-around. This would only happen if we used
305 * up to the last descriptor in the ring, no more, no less.
307 if (txq->tx_tail >= txq->nb_tx_desc)
310 /* update tail pointer */
312 IXGBE_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, txq->tx_tail);
318 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
323 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
324 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
325 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
327 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
332 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
333 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
334 nb_tx = (uint16_t)(nb_tx + ret);
335 nb_pkts = (uint16_t)(nb_pkts - ret);
343 #ifdef RTE_IXGBE_INC_VECTOR
345 ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
349 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
354 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
355 ret = ixgbe_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
368 ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,
369 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
370 uint64_t ol_flags, union ixgbe_tx_offload tx_offload,
371 __rte_unused uint64_t *mdata)
373 uint32_t type_tucmd_mlhl;
374 uint32_t mss_l4len_idx = 0;
376 uint32_t vlan_macip_lens;
377 union ixgbe_tx_offload tx_offload_mask;
378 uint32_t seqnum_seed = 0;
380 ctx_idx = txq->ctx_curr;
381 tx_offload_mask.data[0] = 0;
382 tx_offload_mask.data[1] = 0;
385 /* Specify which HW CTX to upload. */
386 mss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
388 if (ol_flags & PKT_TX_VLAN_PKT) {
389 tx_offload_mask.vlan_tci |= ~0;
392 /* check if TCP segmentation required for this packet */
393 if (ol_flags & PKT_TX_TCP_SEG) {
394 /* implies IP cksum in IPv4 */
395 if (ol_flags & PKT_TX_IP_CKSUM)
396 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |
397 IXGBE_ADVTXD_TUCMD_L4T_TCP |
398 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
400 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV6 |
401 IXGBE_ADVTXD_TUCMD_L4T_TCP |
402 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
404 tx_offload_mask.l2_len |= ~0;
405 tx_offload_mask.l3_len |= ~0;
406 tx_offload_mask.l4_len |= ~0;
407 tx_offload_mask.tso_segsz |= ~0;
408 mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
409 mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;
410 } else { /* no TSO, check if hardware checksum is needed */
411 if (ol_flags & PKT_TX_IP_CKSUM) {
412 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
413 tx_offload_mask.l2_len |= ~0;
414 tx_offload_mask.l3_len |= ~0;
417 switch (ol_flags & PKT_TX_L4_MASK) {
418 case PKT_TX_UDP_CKSUM:
419 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
420 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
421 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
422 tx_offload_mask.l2_len |= ~0;
423 tx_offload_mask.l3_len |= ~0;
425 case PKT_TX_TCP_CKSUM:
426 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
427 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
428 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
429 tx_offload_mask.l2_len |= ~0;
430 tx_offload_mask.l3_len |= ~0;
432 case PKT_TX_SCTP_CKSUM:
433 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
434 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
435 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
436 tx_offload_mask.l2_len |= ~0;
437 tx_offload_mask.l3_len |= ~0;
440 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
441 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
446 if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
447 tx_offload_mask.outer_l2_len |= ~0;
448 tx_offload_mask.outer_l3_len |= ~0;
449 tx_offload_mask.l2_len |= ~0;
450 seqnum_seed |= tx_offload.outer_l3_len
451 << IXGBE_ADVTXD_OUTER_IPLEN;
452 seqnum_seed |= tx_offload.l2_len
453 << IXGBE_ADVTXD_TUNNEL_LEN;
455 #ifdef RTE_LIBRTE_SECURITY
456 if (ol_flags & PKT_TX_SEC_OFFLOAD) {
457 union ixgbe_crypto_tx_desc_md *md =
458 (union ixgbe_crypto_tx_desc_md *)mdata;
460 (IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK & md->sa_idx);
461 type_tucmd_mlhl |= md->enc ?
462 (IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP |
463 IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN) : 0;
465 (md->pad_len & IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK);
466 tx_offload_mask.sa_idx |= ~0;
467 tx_offload_mask.sec_pad_len |= ~0;
471 txq->ctx_cache[ctx_idx].flags = ol_flags;
472 txq->ctx_cache[ctx_idx].tx_offload.data[0] =
473 tx_offload_mask.data[0] & tx_offload.data[0];
474 txq->ctx_cache[ctx_idx].tx_offload.data[1] =
475 tx_offload_mask.data[1] & tx_offload.data[1];
476 txq->ctx_cache[ctx_idx].tx_offload_mask = tx_offload_mask;
478 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
479 vlan_macip_lens = tx_offload.l3_len;
480 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
481 vlan_macip_lens |= (tx_offload.outer_l2_len <<
482 IXGBE_ADVTXD_MACLEN_SHIFT);
484 vlan_macip_lens |= (tx_offload.l2_len <<
485 IXGBE_ADVTXD_MACLEN_SHIFT);
486 vlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);
487 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
488 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
489 ctx_txd->seqnum_seed = seqnum_seed;
493 * Check which hardware context can be used. Use the existing match
494 * or create a new context descriptor.
496 static inline uint32_t
497 what_advctx_update(struct ixgbe_tx_queue *txq, uint64_t flags,
498 union ixgbe_tx_offload tx_offload)
500 /* If match with the current used context */
501 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
502 (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] ==
503 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0]
504 & tx_offload.data[0])) &&
505 (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] ==
506 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1]
507 & tx_offload.data[1]))))
508 return txq->ctx_curr;
510 /* What if match with the next context */
512 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
513 (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] ==
514 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0]
515 & tx_offload.data[0])) &&
516 (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] ==
517 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1]
518 & tx_offload.data[1]))))
519 return txq->ctx_curr;
521 /* Mismatch, use the previous context */
522 return IXGBE_CTX_NUM;
525 static inline uint32_t
526 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
530 if ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM)
531 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
532 if (ol_flags & PKT_TX_IP_CKSUM)
533 tmp |= IXGBE_ADVTXD_POPTS_IXSM;
534 if (ol_flags & PKT_TX_TCP_SEG)
535 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
539 static inline uint32_t
540 tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)
542 uint32_t cmdtype = 0;
544 if (ol_flags & PKT_TX_VLAN_PKT)
545 cmdtype |= IXGBE_ADVTXD_DCMD_VLE;
546 if (ol_flags & PKT_TX_TCP_SEG)
547 cmdtype |= IXGBE_ADVTXD_DCMD_TSE;
548 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
549 cmdtype |= (1 << IXGBE_ADVTXD_OUTERIPCS_SHIFT);
550 if (ol_flags & PKT_TX_MACSEC)
551 cmdtype |= IXGBE_ADVTXD_MAC_LINKSEC;
555 /* Default RS bit threshold values */
556 #ifndef DEFAULT_TX_RS_THRESH
557 #define DEFAULT_TX_RS_THRESH 32
559 #ifndef DEFAULT_TX_FREE_THRESH
560 #define DEFAULT_TX_FREE_THRESH 32
563 /* Reset transmit descriptors after they have been used */
565 ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)
567 struct ixgbe_tx_entry *sw_ring = txq->sw_ring;
568 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
569 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
570 uint16_t nb_tx_desc = txq->nb_tx_desc;
571 uint16_t desc_to_clean_to;
572 uint16_t nb_tx_to_clean;
575 /* Determine the last descriptor needing to be cleaned */
576 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
577 if (desc_to_clean_to >= nb_tx_desc)
578 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
580 /* Check to make sure the last descriptor to clean is done */
581 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
582 status = txr[desc_to_clean_to].wb.status;
583 if (!(status & rte_cpu_to_le_32(IXGBE_TXD_STAT_DD))) {
584 PMD_TX_FREE_LOG(DEBUG,
585 "TX descriptor %4u is not done"
586 "(port=%d queue=%d)",
588 txq->port_id, txq->queue_id);
589 /* Failed to clean any descriptors, better luck next time */
593 /* Figure out how many descriptors will be cleaned */
594 if (last_desc_cleaned > desc_to_clean_to)
595 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
598 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
601 PMD_TX_FREE_LOG(DEBUG,
602 "Cleaning %4u TX descriptors: %4u to %4u "
603 "(port=%d queue=%d)",
604 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
605 txq->port_id, txq->queue_id);
608 * The last descriptor to clean is done, so that means all the
609 * descriptors from the last descriptor that was cleaned
610 * up to the last descriptor with the RS bit set
611 * are done. Only reset the threshold descriptor.
613 txr[desc_to_clean_to].wb.status = 0;
615 /* Update the txq to reflect the last descriptor that was cleaned */
616 txq->last_desc_cleaned = desc_to_clean_to;
617 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
624 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
627 struct ixgbe_tx_queue *txq;
628 struct ixgbe_tx_entry *sw_ring;
629 struct ixgbe_tx_entry *txe, *txn;
630 volatile union ixgbe_adv_tx_desc *txr;
631 volatile union ixgbe_adv_tx_desc *txd, *txp;
632 struct rte_mbuf *tx_pkt;
633 struct rte_mbuf *m_seg;
634 uint64_t buf_dma_addr;
635 uint32_t olinfo_status;
636 uint32_t cmd_type_len;
647 union ixgbe_tx_offload tx_offload;
648 #ifdef RTE_LIBRTE_SECURITY
652 tx_offload.data[0] = 0;
653 tx_offload.data[1] = 0;
655 sw_ring = txq->sw_ring;
657 tx_id = txq->tx_tail;
658 txe = &sw_ring[tx_id];
661 /* Determine if the descriptor ring needs to be cleaned. */
662 if (txq->nb_tx_free < txq->tx_free_thresh)
663 ixgbe_xmit_cleanup(txq);
665 rte_prefetch0(&txe->mbuf->pool);
668 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
671 pkt_len = tx_pkt->pkt_len;
674 * Determine how many (if any) context descriptors
675 * are needed for offload functionality.
677 ol_flags = tx_pkt->ol_flags;
678 #ifdef RTE_LIBRTE_SECURITY
679 use_ipsec = txq->using_ipsec && (ol_flags & PKT_TX_SEC_OFFLOAD);
682 /* If hardware offload required */
683 tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
685 tx_offload.l2_len = tx_pkt->l2_len;
686 tx_offload.l3_len = tx_pkt->l3_len;
687 tx_offload.l4_len = tx_pkt->l4_len;
688 tx_offload.vlan_tci = tx_pkt->vlan_tci;
689 tx_offload.tso_segsz = tx_pkt->tso_segsz;
690 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
691 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
692 #ifdef RTE_LIBRTE_SECURITY
694 union ixgbe_crypto_tx_desc_md *ipsec_mdata =
695 (union ixgbe_crypto_tx_desc_md *)
697 tx_offload.sa_idx = ipsec_mdata->sa_idx;
698 tx_offload.sec_pad_len = ipsec_mdata->pad_len;
702 /* If new context need be built or reuse the exist ctx. */
703 ctx = what_advctx_update(txq, tx_ol_req,
705 /* Only allocate context descriptor if required*/
706 new_ctx = (ctx == IXGBE_CTX_NUM);
711 * Keep track of how many descriptors are used this loop
712 * This will always be the number of segments + the number of
713 * Context descriptors required to transmit the packet
715 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
718 nb_used + txq->nb_tx_used >= txq->tx_rs_thresh)
719 /* set RS on the previous packet in the burst */
720 txp->read.cmd_type_len |=
721 rte_cpu_to_le_32(IXGBE_TXD_CMD_RS);
724 * The number of descriptors that must be allocated for a
725 * packet is the number of segments of that packet, plus 1
726 * Context Descriptor for the hardware offload, if any.
727 * Determine the last TX descriptor to allocate in the TX ring
728 * for the packet, starting from the current position (tx_id)
731 tx_last = (uint16_t) (tx_id + nb_used - 1);
734 if (tx_last >= txq->nb_tx_desc)
735 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
737 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
738 " tx_first=%u tx_last=%u",
739 (unsigned) txq->port_id,
740 (unsigned) txq->queue_id,
746 * Make sure there are enough TX descriptors available to
747 * transmit the entire packet.
748 * nb_used better be less than or equal to txq->tx_rs_thresh
750 if (nb_used > txq->nb_tx_free) {
751 PMD_TX_FREE_LOG(DEBUG,
752 "Not enough free TX descriptors "
753 "nb_used=%4u nb_free=%4u "
754 "(port=%d queue=%d)",
755 nb_used, txq->nb_tx_free,
756 txq->port_id, txq->queue_id);
758 if (ixgbe_xmit_cleanup(txq) != 0) {
759 /* Could not clean any descriptors */
765 /* nb_used better be <= txq->tx_rs_thresh */
766 if (unlikely(nb_used > txq->tx_rs_thresh)) {
767 PMD_TX_FREE_LOG(DEBUG,
768 "The number of descriptors needed to "
769 "transmit the packet exceeds the "
770 "RS bit threshold. This will impact "
772 "nb_used=%4u nb_free=%4u "
774 "(port=%d queue=%d)",
775 nb_used, txq->nb_tx_free,
777 txq->port_id, txq->queue_id);
779 * Loop here until there are enough TX
780 * descriptors or until the ring cannot be
783 while (nb_used > txq->nb_tx_free) {
784 if (ixgbe_xmit_cleanup(txq) != 0) {
786 * Could not clean any
798 * By now there are enough free TX descriptors to transmit
803 * Set common flags of all TX Data Descriptors.
805 * The following bits must be set in all Data Descriptors:
806 * - IXGBE_ADVTXD_DTYP_DATA
807 * - IXGBE_ADVTXD_DCMD_DEXT
809 * The following bits must be set in the first Data Descriptor
810 * and are ignored in the other ones:
811 * - IXGBE_ADVTXD_DCMD_IFCS
812 * - IXGBE_ADVTXD_MAC_1588
813 * - IXGBE_ADVTXD_DCMD_VLE
815 * The following bits must only be set in the last Data
817 * - IXGBE_TXD_CMD_EOP
819 * The following bits can be set in any Data Descriptor, but
820 * are only set in the last Data Descriptor:
823 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
824 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
826 #ifdef RTE_LIBRTE_IEEE1588
827 if (ol_flags & PKT_TX_IEEE1588_TMST)
828 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
834 if (ol_flags & PKT_TX_TCP_SEG) {
835 /* when TSO is on, paylen in descriptor is the
836 * not the packet len but the tcp payload len */
837 pkt_len -= (tx_offload.l2_len +
838 tx_offload.l3_len + tx_offload.l4_len);
842 * Setup the TX Advanced Context Descriptor if required
845 volatile struct ixgbe_adv_tx_context_desc *
848 ctx_txd = (volatile struct
849 ixgbe_adv_tx_context_desc *)
852 txn = &sw_ring[txe->next_id];
853 rte_prefetch0(&txn->mbuf->pool);
855 if (txe->mbuf != NULL) {
856 rte_pktmbuf_free_seg(txe->mbuf);
860 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
861 tx_offload, &tx_pkt->udata64);
863 txe->last_id = tx_last;
864 tx_id = txe->next_id;
869 * Setup the TX Advanced Data Descriptor,
870 * This path will go through
871 * whatever new/reuse the context descriptor
873 cmd_type_len |= tx_desc_ol_flags_to_cmdtype(ol_flags);
874 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
875 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
878 olinfo_status |= (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
879 #ifdef RTE_LIBRTE_SECURITY
881 olinfo_status |= IXGBE_ADVTXD_POPTS_IPSEC;
887 txn = &sw_ring[txe->next_id];
888 rte_prefetch0(&txn->mbuf->pool);
890 if (txe->mbuf != NULL)
891 rte_pktmbuf_free_seg(txe->mbuf);
895 * Set up Transmit Data Descriptor.
897 slen = m_seg->data_len;
898 buf_dma_addr = rte_mbuf_data_iova(m_seg);
899 txd->read.buffer_addr =
900 rte_cpu_to_le_64(buf_dma_addr);
901 txd->read.cmd_type_len =
902 rte_cpu_to_le_32(cmd_type_len | slen);
903 txd->read.olinfo_status =
904 rte_cpu_to_le_32(olinfo_status);
905 txe->last_id = tx_last;
906 tx_id = txe->next_id;
909 } while (m_seg != NULL);
912 * The last packet data descriptor needs End Of Packet (EOP)
914 cmd_type_len |= IXGBE_TXD_CMD_EOP;
915 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
916 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
918 /* Set RS bit only on threshold packets' last descriptor */
919 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
920 PMD_TX_FREE_LOG(DEBUG,
921 "Setting RS bit on TXD id="
922 "%4u (port=%d queue=%d)",
923 tx_last, txq->port_id, txq->queue_id);
925 cmd_type_len |= IXGBE_TXD_CMD_RS;
927 /* Update txq RS bit counters */
933 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
937 /* set RS on last packet in the burst */
939 txp->read.cmd_type_len |= rte_cpu_to_le_32(IXGBE_TXD_CMD_RS);
944 * Set the Transmit Descriptor Tail (TDT)
946 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
947 (unsigned) txq->port_id, (unsigned) txq->queue_id,
948 (unsigned) tx_id, (unsigned) nb_tx);
949 IXGBE_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, tx_id);
950 txq->tx_tail = tx_id;
955 /*********************************************************************
959 **********************************************************************/
961 ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
966 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
968 for (i = 0; i < nb_pkts; i++) {
970 ol_flags = m->ol_flags;
973 * Check if packet meets requirements for number of segments
975 * NOTE: for ixgbe it's always (40 - WTHRESH) for both TSO and
979 if (m->nb_segs > IXGBE_TX_MAX_SEG - txq->wthresh) {
984 if (ol_flags & IXGBE_TX_OFFLOAD_NOTSUP_MASK) {
985 rte_errno = -ENOTSUP;
989 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
990 ret = rte_validate_tx_offload(m);
996 ret = rte_net_intel_cksum_prepare(m);
1006 /*********************************************************************
1010 **********************************************************************/
1012 #define IXGBE_PACKET_TYPE_ETHER 0X00
1013 #define IXGBE_PACKET_TYPE_IPV4 0X01
1014 #define IXGBE_PACKET_TYPE_IPV4_TCP 0X11
1015 #define IXGBE_PACKET_TYPE_IPV4_UDP 0X21
1016 #define IXGBE_PACKET_TYPE_IPV4_SCTP 0X41
1017 #define IXGBE_PACKET_TYPE_IPV4_EXT 0X03
1018 #define IXGBE_PACKET_TYPE_IPV4_EXT_TCP 0X13
1019 #define IXGBE_PACKET_TYPE_IPV4_EXT_UDP 0X23
1020 #define IXGBE_PACKET_TYPE_IPV4_EXT_SCTP 0X43
1021 #define IXGBE_PACKET_TYPE_IPV6 0X04
1022 #define IXGBE_PACKET_TYPE_IPV6_TCP 0X14
1023 #define IXGBE_PACKET_TYPE_IPV6_UDP 0X24
1024 #define IXGBE_PACKET_TYPE_IPV6_SCTP 0X44
1025 #define IXGBE_PACKET_TYPE_IPV6_EXT 0X0C
1026 #define IXGBE_PACKET_TYPE_IPV6_EXT_TCP 0X1C
1027 #define IXGBE_PACKET_TYPE_IPV6_EXT_UDP 0X2C
1028 #define IXGBE_PACKET_TYPE_IPV6_EXT_SCTP 0X4C
1029 #define IXGBE_PACKET_TYPE_IPV4_IPV6 0X05
1030 #define IXGBE_PACKET_TYPE_IPV4_IPV6_TCP 0X15
1031 #define IXGBE_PACKET_TYPE_IPV4_IPV6_UDP 0X25
1032 #define IXGBE_PACKET_TYPE_IPV4_IPV6_SCTP 0X45
1033 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6 0X07
1034 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_TCP 0X17
1035 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_UDP 0X27
1036 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_SCTP 0X47
1037 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT 0X0D
1038 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP 0X1D
1039 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP 0X2D
1040 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_SCTP 0X4D
1041 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT 0X0F
1042 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_TCP 0X1F
1043 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_UDP 0X2F
1044 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_SCTP 0X4F
1046 #define IXGBE_PACKET_TYPE_NVGRE 0X00
1047 #define IXGBE_PACKET_TYPE_NVGRE_IPV4 0X01
1048 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_TCP 0X11
1049 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_UDP 0X21
1050 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_SCTP 0X41
1051 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT 0X03
1052 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_TCP 0X13
1053 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_UDP 0X23
1054 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_SCTP 0X43
1055 #define IXGBE_PACKET_TYPE_NVGRE_IPV6 0X04
1056 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_TCP 0X14
1057 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_UDP 0X24
1058 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_SCTP 0X44
1059 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT 0X0C
1060 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_TCP 0X1C
1061 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_UDP 0X2C
1062 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_SCTP 0X4C
1063 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6 0X05
1064 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_TCP 0X15
1065 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_UDP 0X25
1066 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT 0X0D
1067 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_TCP 0X1D
1068 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_UDP 0X2D
1070 #define IXGBE_PACKET_TYPE_VXLAN 0X80
1071 #define IXGBE_PACKET_TYPE_VXLAN_IPV4 0X81
1072 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_TCP 0x91
1073 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_UDP 0xA1
1074 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_SCTP 0xC1
1075 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT 0x83
1076 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_TCP 0X93
1077 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_UDP 0XA3
1078 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_SCTP 0XC3
1079 #define IXGBE_PACKET_TYPE_VXLAN_IPV6 0X84
1080 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_TCP 0X94
1081 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_UDP 0XA4
1082 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_SCTP 0XC4
1083 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT 0X8C
1084 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_TCP 0X9C
1085 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_UDP 0XAC
1086 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_SCTP 0XCC
1087 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6 0X85
1088 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_TCP 0X95
1089 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_UDP 0XA5
1090 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT 0X8D
1091 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_TCP 0X9D
1092 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_UDP 0XAD
1095 * Use 2 different table for normal packet and tunnel packet
1096 * to save the space.
1099 ptype_table[IXGBE_PACKET_TYPE_MAX] __rte_cache_aligned = {
1100 [IXGBE_PACKET_TYPE_ETHER] = RTE_PTYPE_L2_ETHER,
1101 [IXGBE_PACKET_TYPE_IPV4] = RTE_PTYPE_L2_ETHER |
1103 [IXGBE_PACKET_TYPE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1104 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
1105 [IXGBE_PACKET_TYPE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1106 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
1107 [IXGBE_PACKET_TYPE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1108 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP,
1109 [IXGBE_PACKET_TYPE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1110 RTE_PTYPE_L3_IPV4_EXT,
1111 [IXGBE_PACKET_TYPE_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1112 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_TCP,
1113 [IXGBE_PACKET_TYPE_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1114 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_UDP,
1115 [IXGBE_PACKET_TYPE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1116 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_SCTP,
1117 [IXGBE_PACKET_TYPE_IPV6] = RTE_PTYPE_L2_ETHER |
1119 [IXGBE_PACKET_TYPE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1120 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
1121 [IXGBE_PACKET_TYPE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1122 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
1123 [IXGBE_PACKET_TYPE_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1124 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_SCTP,
1125 [IXGBE_PACKET_TYPE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1126 RTE_PTYPE_L3_IPV6_EXT,
1127 [IXGBE_PACKET_TYPE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1128 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,
1129 [IXGBE_PACKET_TYPE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1130 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
1131 [IXGBE_PACKET_TYPE_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1132 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_SCTP,
1133 [IXGBE_PACKET_TYPE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1134 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1135 RTE_PTYPE_INNER_L3_IPV6,
1136 [IXGBE_PACKET_TYPE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1137 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1138 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1139 [IXGBE_PACKET_TYPE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1140 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1141 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1142 [IXGBE_PACKET_TYPE_IPV4_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1143 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1144 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
1145 [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6] = RTE_PTYPE_L2_ETHER |
1146 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1147 RTE_PTYPE_INNER_L3_IPV6,
1148 [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1149 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1150 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1151 [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1152 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1153 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1154 [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1155 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1156 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
1157 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1158 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1159 RTE_PTYPE_INNER_L3_IPV6_EXT,
1160 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1161 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1162 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1163 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1164 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1165 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1166 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1167 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1168 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
1169 [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1170 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1171 RTE_PTYPE_INNER_L3_IPV6_EXT,
1172 [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1173 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1174 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1175 [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1176 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1177 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1178 [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_SCTP] =
1179 RTE_PTYPE_L2_ETHER |
1180 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1181 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
1185 ptype_table_tn[IXGBE_PACKET_TYPE_TN_MAX] __rte_cache_aligned = {
1186 [IXGBE_PACKET_TYPE_NVGRE] = RTE_PTYPE_L2_ETHER |
1187 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1188 RTE_PTYPE_INNER_L2_ETHER,
1189 [IXGBE_PACKET_TYPE_NVGRE_IPV4] = RTE_PTYPE_L2_ETHER |
1190 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1191 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1192 [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1193 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1194 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT,
1195 [IXGBE_PACKET_TYPE_NVGRE_IPV6] = RTE_PTYPE_L2_ETHER |
1196 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1197 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6,
1198 [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1199 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1200 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1201 [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1202 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1203 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT,
1204 [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1205 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1206 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1207 [IXGBE_PACKET_TYPE_NVGRE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1208 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1209 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1210 RTE_PTYPE_INNER_L4_TCP,
1211 [IXGBE_PACKET_TYPE_NVGRE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1212 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1213 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1214 RTE_PTYPE_INNER_L4_TCP,
1215 [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1216 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1217 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1218 [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1219 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1220 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1221 RTE_PTYPE_INNER_L4_TCP,
1222 [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_TCP] =
1223 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1224 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_INNER_L2_ETHER |
1225 RTE_PTYPE_INNER_L3_IPV4,
1226 [IXGBE_PACKET_TYPE_NVGRE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1227 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1228 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1229 RTE_PTYPE_INNER_L4_UDP,
1230 [IXGBE_PACKET_TYPE_NVGRE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1231 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1232 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1233 RTE_PTYPE_INNER_L4_UDP,
1234 [IXGBE_PACKET_TYPE_NVGRE_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1235 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1236 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1237 RTE_PTYPE_INNER_L4_SCTP,
1238 [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1239 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1240 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1241 [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1242 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1243 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1244 RTE_PTYPE_INNER_L4_UDP,
1245 [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1246 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1247 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1248 RTE_PTYPE_INNER_L4_SCTP,
1249 [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_UDP] =
1250 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1251 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_INNER_L2_ETHER |
1252 RTE_PTYPE_INNER_L3_IPV4,
1253 [IXGBE_PACKET_TYPE_NVGRE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1254 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1255 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1256 RTE_PTYPE_INNER_L4_SCTP,
1257 [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1258 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1259 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
1260 RTE_PTYPE_INNER_L4_SCTP,
1261 [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1262 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1263 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
1264 RTE_PTYPE_INNER_L4_TCP,
1265 [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1266 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1267 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
1268 RTE_PTYPE_INNER_L4_UDP,
1270 [IXGBE_PACKET_TYPE_VXLAN] = RTE_PTYPE_L2_ETHER |
1271 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1272 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER,
1273 [IXGBE_PACKET_TYPE_VXLAN_IPV4] = RTE_PTYPE_L2_ETHER |
1274 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1275 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1276 RTE_PTYPE_INNER_L3_IPV4,
1277 [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1278 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1279 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1280 RTE_PTYPE_INNER_L3_IPV4_EXT,
1281 [IXGBE_PACKET_TYPE_VXLAN_IPV6] = RTE_PTYPE_L2_ETHER |
1282 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1283 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1284 RTE_PTYPE_INNER_L3_IPV6,
1285 [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1286 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1287 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1288 RTE_PTYPE_INNER_L3_IPV4,
1289 [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1290 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1291 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1292 RTE_PTYPE_INNER_L3_IPV6_EXT,
1293 [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1294 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1295 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1296 RTE_PTYPE_INNER_L3_IPV4,
1297 [IXGBE_PACKET_TYPE_VXLAN_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1298 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1299 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1300 RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_TCP,
1301 [IXGBE_PACKET_TYPE_VXLAN_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1302 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1303 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1304 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1305 [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1306 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1307 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1308 RTE_PTYPE_INNER_L3_IPV4,
1309 [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1310 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1311 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1312 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1313 [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_TCP] =
1314 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1315 RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN |
1316 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1317 [IXGBE_PACKET_TYPE_VXLAN_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1318 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1319 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1320 RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_UDP,
1321 [IXGBE_PACKET_TYPE_VXLAN_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1322 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1323 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1324 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1325 [IXGBE_PACKET_TYPE_VXLAN_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1326 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1327 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1328 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
1329 [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1330 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1331 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1332 RTE_PTYPE_INNER_L3_IPV4,
1333 [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1334 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1335 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1336 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1337 [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1338 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1339 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1340 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
1341 [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_UDP] =
1342 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1343 RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN |
1344 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1345 [IXGBE_PACKET_TYPE_VXLAN_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1346 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1347 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1348 RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_SCTP,
1349 [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1350 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1351 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1352 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_SCTP,
1353 [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1354 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1355 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1356 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_TCP,
1357 [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1358 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1359 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1360 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
1363 /* @note: fix ixgbe_dev_supported_ptypes_get() if any change here. */
1364 static inline uint32_t
1365 ixgbe_rxd_pkt_info_to_pkt_type(uint32_t pkt_info, uint16_t ptype_mask)
1368 if (unlikely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
1369 return RTE_PTYPE_UNKNOWN;
1371 pkt_info = (pkt_info >> IXGBE_PACKET_TYPE_SHIFT) & ptype_mask;
1373 /* For tunnel packet */
1374 if (pkt_info & IXGBE_PACKET_TYPE_TUNNEL_BIT) {
1375 /* Remove the tunnel bit to save the space. */
1376 pkt_info &= IXGBE_PACKET_TYPE_MASK_TUNNEL;
1377 return ptype_table_tn[pkt_info];
1381 * For x550, if it's not tunnel,
1382 * tunnel type bit should be set to 0.
1383 * Reuse 82599's mask.
1385 pkt_info &= IXGBE_PACKET_TYPE_MASK_82599;
1387 return ptype_table[pkt_info];
1390 static inline uint64_t
1391 ixgbe_rxd_pkt_info_to_pkt_flags(uint16_t pkt_info)
1393 static uint64_t ip_rss_types_map[16] __rte_cache_aligned = {
1394 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
1395 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
1396 PKT_RX_RSS_HASH, 0, 0, 0,
1397 0, 0, 0, PKT_RX_FDIR,
1399 #ifdef RTE_LIBRTE_IEEE1588
1400 static uint64_t ip_pkt_etqf_map[8] = {
1401 0, 0, 0, PKT_RX_IEEE1588_PTP,
1405 if (likely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
1406 return ip_pkt_etqf_map[(pkt_info >> 4) & 0X07] |
1407 ip_rss_types_map[pkt_info & 0XF];
1409 return ip_rss_types_map[pkt_info & 0XF];
1411 return ip_rss_types_map[pkt_info & 0XF];
1415 static inline uint64_t
1416 rx_desc_status_to_pkt_flags(uint32_t rx_status, uint64_t vlan_flags)
1421 * Check if VLAN present only.
1422 * Do not check whether L3/L4 rx checksum done by NIC or not,
1423 * That can be found from rte_eth_rxmode.offloads flag
1425 pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ? vlan_flags : 0;
1427 #ifdef RTE_LIBRTE_IEEE1588
1428 if (rx_status & IXGBE_RXD_STAT_TMST)
1429 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
1434 static inline uint64_t
1435 rx_desc_error_to_pkt_flags(uint32_t rx_status)
1440 * Bit 31: IPE, IPv4 checksum error
1441 * Bit 30: L4I, L4I integrity error
1443 static uint64_t error_to_pkt_flags_map[4] = {
1444 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD,
1445 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
1446 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD,
1447 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
1449 pkt_flags = error_to_pkt_flags_map[(rx_status >>
1450 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
1452 if ((rx_status & IXGBE_RXD_STAT_OUTERIPCS) &&
1453 (rx_status & IXGBE_RXDADV_ERR_OUTERIPER)) {
1454 pkt_flags |= PKT_RX_EIP_CKSUM_BAD;
1457 #ifdef RTE_LIBRTE_SECURITY
1458 if (rx_status & IXGBE_RXD_STAT_SECP) {
1459 pkt_flags |= PKT_RX_SEC_OFFLOAD;
1460 if (rx_status & IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG)
1461 pkt_flags |= PKT_RX_SEC_OFFLOAD_FAILED;
1469 * LOOK_AHEAD defines how many desc statuses to check beyond the
1470 * current descriptor.
1471 * It must be a pound define for optimal performance.
1472 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
1473 * function only works with LOOK_AHEAD=8.
1475 #define LOOK_AHEAD 8
1476 #if (LOOK_AHEAD != 8)
1477 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
1480 ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
1482 volatile union ixgbe_adv_rx_desc *rxdp;
1483 struct ixgbe_rx_entry *rxep;
1484 struct rte_mbuf *mb;
1488 uint32_t s[LOOK_AHEAD];
1489 uint32_t pkt_info[LOOK_AHEAD];
1490 int i, j, nb_rx = 0;
1492 uint64_t vlan_flags = rxq->vlan_flags;
1494 /* get references to current descriptor and S/W ring entry */
1495 rxdp = &rxq->rx_ring[rxq->rx_tail];
1496 rxep = &rxq->sw_ring[rxq->rx_tail];
1498 status = rxdp->wb.upper.status_error;
1499 /* check to make sure there is at least 1 packet to receive */
1500 if (!(status & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1504 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
1505 * reference packets that are ready to be received.
1507 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
1508 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD) {
1509 /* Read desc statuses backwards to avoid race condition */
1510 for (j = 0; j < LOOK_AHEAD; j++)
1511 s[j] = rte_le_to_cpu_32(rxdp[j].wb.upper.status_error);
1515 /* Compute how many status bits were set */
1516 for (nb_dd = 0; nb_dd < LOOK_AHEAD &&
1517 (s[nb_dd] & IXGBE_RXDADV_STAT_DD); nb_dd++)
1520 for (j = 0; j < nb_dd; j++)
1521 pkt_info[j] = rte_le_to_cpu_32(rxdp[j].wb.lower.
1526 /* Translate descriptor info to mbuf format */
1527 for (j = 0; j < nb_dd; ++j) {
1529 pkt_len = rte_le_to_cpu_16(rxdp[j].wb.upper.length) -
1531 mb->data_len = pkt_len;
1532 mb->pkt_len = pkt_len;
1533 mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
1535 /* convert descriptor fields to rte mbuf flags */
1536 pkt_flags = rx_desc_status_to_pkt_flags(s[j],
1538 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
1539 pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags
1540 ((uint16_t)pkt_info[j]);
1541 mb->ol_flags = pkt_flags;
1543 ixgbe_rxd_pkt_info_to_pkt_type
1544 (pkt_info[j], rxq->pkt_type_mask);
1546 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1547 mb->hash.rss = rte_le_to_cpu_32(
1548 rxdp[j].wb.lower.hi_dword.rss);
1549 else if (pkt_flags & PKT_RX_FDIR) {
1550 mb->hash.fdir.hash = rte_le_to_cpu_16(
1551 rxdp[j].wb.lower.hi_dword.csum_ip.csum) &
1552 IXGBE_ATR_HASH_MASK;
1553 mb->hash.fdir.id = rte_le_to_cpu_16(
1554 rxdp[j].wb.lower.hi_dword.csum_ip.ip_id);
1558 /* Move mbuf pointers from the S/W ring to the stage */
1559 for (j = 0; j < LOOK_AHEAD; ++j) {
1560 rxq->rx_stage[i + j] = rxep[j].mbuf;
1563 /* stop if all requested packets could not be received */
1564 if (nb_dd != LOOK_AHEAD)
1568 /* clear software ring entries so we can cleanup correctly */
1569 for (i = 0; i < nb_rx; ++i) {
1570 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1578 ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq, bool reset_mbuf)
1580 volatile union ixgbe_adv_rx_desc *rxdp;
1581 struct ixgbe_rx_entry *rxep;
1582 struct rte_mbuf *mb;
1587 /* allocate buffers in bulk directly into the S/W ring */
1588 alloc_idx = rxq->rx_free_trigger - (rxq->rx_free_thresh - 1);
1589 rxep = &rxq->sw_ring[alloc_idx];
1590 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1591 rxq->rx_free_thresh);
1592 if (unlikely(diag != 0))
1595 rxdp = &rxq->rx_ring[alloc_idx];
1596 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1597 /* populate the static rte mbuf fields */
1600 mb->port = rxq->port_id;
1603 rte_mbuf_refcnt_set(mb, 1);
1604 mb->data_off = RTE_PKTMBUF_HEADROOM;
1606 /* populate the descriptors */
1607 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1608 rxdp[i].read.hdr_addr = 0;
1609 rxdp[i].read.pkt_addr = dma_addr;
1612 /* update state of internal queue structure */
1613 rxq->rx_free_trigger = rxq->rx_free_trigger + rxq->rx_free_thresh;
1614 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1615 rxq->rx_free_trigger = rxq->rx_free_thresh - 1;
1621 static inline uint16_t
1622 ixgbe_rx_fill_from_stage(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1625 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1628 /* how many packets are ready to return? */
1629 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1631 /* copy mbuf pointers to the application's packet list */
1632 for (i = 0; i < nb_pkts; ++i)
1633 rx_pkts[i] = stage[i];
1635 /* update internal queue state */
1636 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1637 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1642 static inline uint16_t
1643 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1646 struct ixgbe_rx_queue *rxq = (struct ixgbe_rx_queue *)rx_queue;
1649 /* Any previously recv'd pkts will be returned from the Rx stage */
1650 if (rxq->rx_nb_avail)
1651 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1653 /* Scan the H/W ring for packets to receive */
1654 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1656 /* update internal queue state */
1657 rxq->rx_next_avail = 0;
1658 rxq->rx_nb_avail = nb_rx;
1659 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1661 /* if required, allocate new buffers to replenish descriptors */
1662 if (rxq->rx_tail > rxq->rx_free_trigger) {
1663 uint16_t cur_free_trigger = rxq->rx_free_trigger;
1665 if (ixgbe_rx_alloc_bufs(rxq, true) != 0) {
1668 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1669 "queue_id=%u", (unsigned) rxq->port_id,
1670 (unsigned) rxq->queue_id);
1672 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1673 rxq->rx_free_thresh;
1676 * Need to rewind any previous receives if we cannot
1677 * allocate new buffers to replenish the old ones.
1679 rxq->rx_nb_avail = 0;
1680 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1681 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1682 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1687 /* update tail pointer */
1689 IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr,
1693 if (rxq->rx_tail >= rxq->nb_rx_desc)
1696 /* received any packets this loop? */
1697 if (rxq->rx_nb_avail)
1698 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1703 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1705 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1710 if (unlikely(nb_pkts == 0))
1713 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1714 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1716 /* request is relatively large, chunk it up */
1721 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1722 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1723 nb_rx = (uint16_t)(nb_rx + ret);
1724 nb_pkts = (uint16_t)(nb_pkts - ret);
1733 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1736 struct ixgbe_rx_queue *rxq;
1737 volatile union ixgbe_adv_rx_desc *rx_ring;
1738 volatile union ixgbe_adv_rx_desc *rxdp;
1739 struct ixgbe_rx_entry *sw_ring;
1740 struct ixgbe_rx_entry *rxe;
1741 struct rte_mbuf *rxm;
1742 struct rte_mbuf *nmb;
1743 union ixgbe_adv_rx_desc rxd;
1752 uint64_t vlan_flags;
1757 rx_id = rxq->rx_tail;
1758 rx_ring = rxq->rx_ring;
1759 sw_ring = rxq->sw_ring;
1760 vlan_flags = rxq->vlan_flags;
1761 while (nb_rx < nb_pkts) {
1763 * The order of operations here is important as the DD status
1764 * bit must not be read after any other descriptor fields.
1765 * rx_ring and rxdp are pointing to volatile data so the order
1766 * of accesses cannot be reordered by the compiler. If they were
1767 * not volatile, they could be reordered which could lead to
1768 * using invalid descriptor fields when read from rxd.
1770 rxdp = &rx_ring[rx_id];
1771 staterr = rxdp->wb.upper.status_error;
1772 if (!(staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1779 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1780 * is likely to be invalid and to be dropped by the various
1781 * validation checks performed by the network stack.
1783 * Allocate a new mbuf to replenish the RX ring descriptor.
1784 * If the allocation fails:
1785 * - arrange for that RX descriptor to be the first one
1786 * being parsed the next time the receive function is
1787 * invoked [on the same queue].
1789 * - Stop parsing the RX ring and return immediately.
1791 * This policy do not drop the packet received in the RX
1792 * descriptor for which the allocation of a new mbuf failed.
1793 * Thus, it allows that packet to be later retrieved if
1794 * mbuf have been freed in the mean time.
1795 * As a side effect, holding RX descriptors instead of
1796 * systematically giving them back to the NIC may lead to
1797 * RX ring exhaustion situations.
1798 * However, the NIC can gracefully prevent such situations
1799 * to happen by sending specific "back-pressure" flow control
1800 * frames to its peer(s).
1802 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1803 "ext_err_stat=0x%08x pkt_len=%u",
1804 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1805 (unsigned) rx_id, (unsigned) staterr,
1806 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1808 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
1810 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1811 "queue_id=%u", (unsigned) rxq->port_id,
1812 (unsigned) rxq->queue_id);
1813 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1818 rxe = &sw_ring[rx_id];
1820 if (rx_id == rxq->nb_rx_desc)
1823 /* Prefetch next mbuf while processing current one. */
1824 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1827 * When next RX descriptor is on a cache-line boundary,
1828 * prefetch the next 4 RX descriptors and the next 8 pointers
1831 if ((rx_id & 0x3) == 0) {
1832 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1833 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1839 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1840 rxdp->read.hdr_addr = 0;
1841 rxdp->read.pkt_addr = dma_addr;
1844 * Initialize the returned mbuf.
1845 * 1) setup generic mbuf fields:
1846 * - number of segments,
1849 * - RX port identifier.
1850 * 2) integrate hardware offload data, if any:
1851 * - RSS flag & hash,
1852 * - IP checksum flag,
1853 * - VLAN TCI, if any,
1856 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1858 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1859 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1862 rxm->pkt_len = pkt_len;
1863 rxm->data_len = pkt_len;
1864 rxm->port = rxq->port_id;
1866 pkt_info = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1867 /* Only valid if PKT_RX_VLAN set in pkt_flags */
1868 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1870 pkt_flags = rx_desc_status_to_pkt_flags(staterr, vlan_flags);
1871 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1872 pkt_flags = pkt_flags |
1873 ixgbe_rxd_pkt_info_to_pkt_flags((uint16_t)pkt_info);
1874 rxm->ol_flags = pkt_flags;
1876 ixgbe_rxd_pkt_info_to_pkt_type(pkt_info,
1877 rxq->pkt_type_mask);
1879 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1880 rxm->hash.rss = rte_le_to_cpu_32(
1881 rxd.wb.lower.hi_dword.rss);
1882 else if (pkt_flags & PKT_RX_FDIR) {
1883 rxm->hash.fdir.hash = rte_le_to_cpu_16(
1884 rxd.wb.lower.hi_dword.csum_ip.csum) &
1885 IXGBE_ATR_HASH_MASK;
1886 rxm->hash.fdir.id = rte_le_to_cpu_16(
1887 rxd.wb.lower.hi_dword.csum_ip.ip_id);
1890 * Store the mbuf address into the next entry of the array
1891 * of returned packets.
1893 rx_pkts[nb_rx++] = rxm;
1895 rxq->rx_tail = rx_id;
1898 * If the number of free RX descriptors is greater than the RX free
1899 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1901 * Update the RDT with the value of the last processed RX descriptor
1902 * minus 1, to guarantee that the RDT register is never equal to the
1903 * RDH register, which creates a "full" ring situtation from the
1904 * hardware point of view...
1906 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1907 if (nb_hold > rxq->rx_free_thresh) {
1908 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1909 "nb_hold=%u nb_rx=%u",
1910 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1911 (unsigned) rx_id, (unsigned) nb_hold,
1913 rx_id = (uint16_t) ((rx_id == 0) ?
1914 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1915 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1918 rxq->nb_rx_hold = nb_hold;
1923 * Detect an RSC descriptor.
1925 static inline uint32_t
1926 ixgbe_rsc_count(union ixgbe_adv_rx_desc *rx)
1928 return (rte_le_to_cpu_32(rx->wb.lower.lo_dword.data) &
1929 IXGBE_RXDADV_RSCCNT_MASK) >> IXGBE_RXDADV_RSCCNT_SHIFT;
1933 * ixgbe_fill_cluster_head_buf - fill the first mbuf of the returned packet
1935 * Fill the following info in the HEAD buffer of the Rx cluster:
1936 * - RX port identifier
1937 * - hardware offload data, if any:
1939 * - IP checksum flag
1940 * - VLAN TCI, if any
1942 * @head HEAD of the packet cluster
1943 * @desc HW descriptor to get data from
1944 * @rxq Pointer to the Rx queue
1947 ixgbe_fill_cluster_head_buf(
1948 struct rte_mbuf *head,
1949 union ixgbe_adv_rx_desc *desc,
1950 struct ixgbe_rx_queue *rxq,
1956 head->port = rxq->port_id;
1958 /* The vlan_tci field is only valid when PKT_RX_VLAN is
1959 * set in the pkt_flags field.
1961 head->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);
1962 pkt_info = rte_le_to_cpu_32(desc->wb.lower.lo_dword.data);
1963 pkt_flags = rx_desc_status_to_pkt_flags(staterr, rxq->vlan_flags);
1964 pkt_flags |= rx_desc_error_to_pkt_flags(staterr);
1965 pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags((uint16_t)pkt_info);
1966 head->ol_flags = pkt_flags;
1968 ixgbe_rxd_pkt_info_to_pkt_type(pkt_info, rxq->pkt_type_mask);
1970 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1971 head->hash.rss = rte_le_to_cpu_32(desc->wb.lower.hi_dword.rss);
1972 else if (pkt_flags & PKT_RX_FDIR) {
1973 head->hash.fdir.hash =
1974 rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.csum)
1975 & IXGBE_ATR_HASH_MASK;
1976 head->hash.fdir.id =
1977 rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.ip_id);
1982 * ixgbe_recv_pkts_lro - receive handler for and LRO case.
1984 * @rx_queue Rx queue handle
1985 * @rx_pkts table of received packets
1986 * @nb_pkts size of rx_pkts table
1987 * @bulk_alloc if TRUE bulk allocation is used for a HW ring refilling
1989 * Handles the Rx HW ring completions when RSC feature is configured. Uses an
1990 * additional ring of ixgbe_rsc_entry's that will hold the relevant RSC info.
1992 * We use the same logic as in Linux and in FreeBSD ixgbe drivers:
1993 * 1) When non-EOP RSC completion arrives:
1994 * a) Update the HEAD of the current RSC aggregation cluster with the new
1995 * segment's data length.
1996 * b) Set the "next" pointer of the current segment to point to the segment
1997 * at the NEXTP index.
1998 * c) Pass the HEAD of RSC aggregation cluster on to the next NEXTP entry
1999 * in the sw_rsc_ring.
2000 * 2) When EOP arrives we just update the cluster's total length and offload
2001 * flags and deliver the cluster up to the upper layers. In our case - put it
2002 * in the rx_pkts table.
2004 * Returns the number of received packets/clusters (according to the "bulk
2005 * receive" interface).
2007 static inline uint16_t
2008 ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
2011 struct ixgbe_rx_queue *rxq = rx_queue;
2012 volatile union ixgbe_adv_rx_desc *rx_ring = rxq->rx_ring;
2013 struct ixgbe_rx_entry *sw_ring = rxq->sw_ring;
2014 struct ixgbe_scattered_rx_entry *sw_sc_ring = rxq->sw_sc_ring;
2015 uint16_t rx_id = rxq->rx_tail;
2017 uint16_t nb_hold = rxq->nb_rx_hold;
2018 uint16_t prev_id = rxq->rx_tail;
2020 while (nb_rx < nb_pkts) {
2022 struct ixgbe_rx_entry *rxe;
2023 struct ixgbe_scattered_rx_entry *sc_entry;
2024 struct ixgbe_scattered_rx_entry *next_sc_entry;
2025 struct ixgbe_rx_entry *next_rxe = NULL;
2026 struct rte_mbuf *first_seg;
2027 struct rte_mbuf *rxm;
2028 struct rte_mbuf *nmb;
2029 union ixgbe_adv_rx_desc rxd;
2032 volatile union ixgbe_adv_rx_desc *rxdp;
2037 * The code in this whole file uses the volatile pointer to
2038 * ensure the read ordering of the status and the rest of the
2039 * descriptor fields (on the compiler level only!!!). This is so
2040 * UGLY - why not to just use the compiler barrier instead? DPDK
2041 * even has the rte_compiler_barrier() for that.
2043 * But most importantly this is just wrong because this doesn't
2044 * ensure memory ordering in a general case at all. For
2045 * instance, DPDK is supposed to work on Power CPUs where
2046 * compiler barrier may just not be enough!
2048 * I tried to write only this function properly to have a
2049 * starting point (as a part of an LRO/RSC series) but the
2050 * compiler cursed at me when I tried to cast away the
2051 * "volatile" from rx_ring (yes, it's volatile too!!!). So, I'm
2052 * keeping it the way it is for now.
2054 * The code in this file is broken in so many other places and
2055 * will just not work on a big endian CPU anyway therefore the
2056 * lines below will have to be revisited together with the rest
2060 * - Get rid of "volatile" crap and let the compiler do its
2062 * - Use the proper memory barrier (rte_rmb()) to ensure the
2063 * memory ordering below.
2065 rxdp = &rx_ring[rx_id];
2066 staterr = rte_le_to_cpu_32(rxdp->wb.upper.status_error);
2068 if (!(staterr & IXGBE_RXDADV_STAT_DD))
2073 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
2074 "staterr=0x%x data_len=%u",
2075 rxq->port_id, rxq->queue_id, rx_id, staterr,
2076 rte_le_to_cpu_16(rxd.wb.upper.length));
2079 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
2081 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed "
2082 "port_id=%u queue_id=%u",
2083 rxq->port_id, rxq->queue_id);
2085 rte_eth_devices[rxq->port_id].data->
2086 rx_mbuf_alloc_failed++;
2089 } else if (nb_hold > rxq->rx_free_thresh) {
2090 uint16_t next_rdt = rxq->rx_free_trigger;
2092 if (!ixgbe_rx_alloc_bufs(rxq, false)) {
2094 IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr,
2096 nb_hold -= rxq->rx_free_thresh;
2098 PMD_RX_LOG(DEBUG, "RX bulk alloc failed "
2099 "port_id=%u queue_id=%u",
2100 rxq->port_id, rxq->queue_id);
2102 rte_eth_devices[rxq->port_id].data->
2103 rx_mbuf_alloc_failed++;
2109 rxe = &sw_ring[rx_id];
2110 eop = staterr & IXGBE_RXDADV_STAT_EOP;
2112 next_id = rx_id + 1;
2113 if (next_id == rxq->nb_rx_desc)
2116 /* Prefetch next mbuf while processing current one. */
2117 rte_ixgbe_prefetch(sw_ring[next_id].mbuf);
2120 * When next RX descriptor is on a cache-line boundary,
2121 * prefetch the next 4 RX descriptors and the next 4 pointers
2124 if ((next_id & 0x3) == 0) {
2125 rte_ixgbe_prefetch(&rx_ring[next_id]);
2126 rte_ixgbe_prefetch(&sw_ring[next_id]);
2133 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2135 * Update RX descriptor with the physical address of the
2136 * new data buffer of the new allocated mbuf.
2140 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2141 rxdp->read.hdr_addr = 0;
2142 rxdp->read.pkt_addr = dma;
2147 * Set data length & data buffer address of mbuf.
2149 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
2150 rxm->data_len = data_len;
2155 * Get next descriptor index:
2156 * - For RSC it's in the NEXTP field.
2157 * - For a scattered packet - it's just a following
2160 if (ixgbe_rsc_count(&rxd))
2162 (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
2163 IXGBE_RXDADV_NEXTP_SHIFT;
2167 next_sc_entry = &sw_sc_ring[nextp_id];
2168 next_rxe = &sw_ring[nextp_id];
2169 rte_ixgbe_prefetch(next_rxe);
2172 sc_entry = &sw_sc_ring[rx_id];
2173 first_seg = sc_entry->fbuf;
2174 sc_entry->fbuf = NULL;
2177 * If this is the first buffer of the received packet,
2178 * set the pointer to the first mbuf of the packet and
2179 * initialize its context.
2180 * Otherwise, update the total length and the number of segments
2181 * of the current scattered packet, and update the pointer to
2182 * the last mbuf of the current packet.
2184 if (first_seg == NULL) {
2186 first_seg->pkt_len = data_len;
2187 first_seg->nb_segs = 1;
2189 first_seg->pkt_len += data_len;
2190 first_seg->nb_segs++;
2197 * If this is not the last buffer of the received packet, update
2198 * the pointer to the first mbuf at the NEXTP entry in the
2199 * sw_sc_ring and continue to parse the RX ring.
2201 if (!eop && next_rxe) {
2202 rxm->next = next_rxe->mbuf;
2203 next_sc_entry->fbuf = first_seg;
2207 /* Initialize the first mbuf of the returned packet */
2208 ixgbe_fill_cluster_head_buf(first_seg, &rxd, rxq, staterr);
2211 * Deal with the case, when HW CRC srip is disabled.
2212 * That can't happen when LRO is enabled, but still could
2213 * happen for scattered RX mode.
2215 first_seg->pkt_len -= rxq->crc_len;
2216 if (unlikely(rxm->data_len <= rxq->crc_len)) {
2217 struct rte_mbuf *lp;
2219 for (lp = first_seg; lp->next != rxm; lp = lp->next)
2222 first_seg->nb_segs--;
2223 lp->data_len -= rxq->crc_len - rxm->data_len;
2225 rte_pktmbuf_free_seg(rxm);
2227 rxm->data_len -= rxq->crc_len;
2229 /* Prefetch data of first segment, if configured to do so. */
2230 rte_packet_prefetch((char *)first_seg->buf_addr +
2231 first_seg->data_off);
2234 * Store the mbuf address into the next entry of the array
2235 * of returned packets.
2237 rx_pkts[nb_rx++] = first_seg;
2241 * Record index of the next RX descriptor to probe.
2243 rxq->rx_tail = rx_id;
2246 * If the number of free RX descriptors is greater than the RX free
2247 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
2249 * Update the RDT with the value of the last processed RX descriptor
2250 * minus 1, to guarantee that the RDT register is never equal to the
2251 * RDH register, which creates a "full" ring situtation from the
2252 * hardware point of view...
2254 if (!bulk_alloc && nb_hold > rxq->rx_free_thresh) {
2255 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
2256 "nb_hold=%u nb_rx=%u",
2257 rxq->port_id, rxq->queue_id, rx_id, nb_hold, nb_rx);
2260 IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr, prev_id);
2264 rxq->nb_rx_hold = nb_hold;
2269 ixgbe_recv_pkts_lro_single_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
2272 return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, false);
2276 ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
2279 return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, true);
2282 /*********************************************************************
2284 * Queue management functions
2286 **********************************************************************/
2288 static void __attribute__((cold))
2289 ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)
2293 if (txq->sw_ring != NULL) {
2294 for (i = 0; i < txq->nb_tx_desc; i++) {
2295 if (txq->sw_ring[i].mbuf != NULL) {
2296 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2297 txq->sw_ring[i].mbuf = NULL;
2303 static void __attribute__((cold))
2304 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
2307 txq->sw_ring != NULL)
2308 rte_free(txq->sw_ring);
2311 static void __attribute__((cold))
2312 ixgbe_tx_queue_release(struct ixgbe_tx_queue *txq)
2314 if (txq != NULL && txq->ops != NULL) {
2315 txq->ops->release_mbufs(txq);
2316 txq->ops->free_swring(txq);
2321 void __attribute__((cold))
2322 ixgbe_dev_tx_queue_release(void *txq)
2324 ixgbe_tx_queue_release(txq);
2327 /* (Re)set dynamic ixgbe_tx_queue fields to defaults */
2328 static void __attribute__((cold))
2329 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
2331 static const union ixgbe_adv_tx_desc zeroed_desc = {{0}};
2332 struct ixgbe_tx_entry *txe = txq->sw_ring;
2335 /* Zero out HW ring memory */
2336 for (i = 0; i < txq->nb_tx_desc; i++) {
2337 txq->tx_ring[i] = zeroed_desc;
2340 /* Initialize SW ring entries */
2341 prev = (uint16_t) (txq->nb_tx_desc - 1);
2342 for (i = 0; i < txq->nb_tx_desc; i++) {
2343 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
2345 txd->wb.status = rte_cpu_to_le_32(IXGBE_TXD_STAT_DD);
2348 txe[prev].next_id = i;
2352 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2353 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2356 txq->nb_tx_used = 0;
2358 * Always allow 1 descriptor to be un-allocated to avoid
2359 * a H/W race condition
2361 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2362 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2364 memset((void *)&txq->ctx_cache, 0,
2365 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
2368 static const struct ixgbe_txq_ops def_txq_ops = {
2369 .release_mbufs = ixgbe_tx_queue_release_mbufs,
2370 .free_swring = ixgbe_tx_free_swring,
2371 .reset = ixgbe_reset_tx_queue,
2374 /* Takes an ethdev and a queue and sets up the tx function to be used based on
2375 * the queue parameters. Used in tx_queue_setup by primary process and then
2376 * in dev_init by secondary process when attaching to an existing ethdev.
2378 void __attribute__((cold))
2379 ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)
2381 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2382 if ((txq->offloads == 0) &&
2383 #ifdef RTE_LIBRTE_SECURITY
2384 !(txq->using_ipsec) &&
2386 (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
2387 PMD_INIT_LOG(DEBUG, "Using simple tx code path");
2388 dev->tx_pkt_prepare = NULL;
2389 #ifdef RTE_IXGBE_INC_VECTOR
2390 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
2391 (rte_eal_process_type() != RTE_PROC_PRIMARY ||
2392 ixgbe_txq_vec_setup(txq) == 0)) {
2393 PMD_INIT_LOG(DEBUG, "Vector tx enabled.");
2394 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
2397 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
2399 PMD_INIT_LOG(DEBUG, "Using full-featured tx code path");
2401 " - offloads = 0x%" PRIx64,
2404 " - tx_rs_thresh = %lu " "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
2405 (unsigned long)txq->tx_rs_thresh,
2406 (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST);
2407 dev->tx_pkt_burst = ixgbe_xmit_pkts;
2408 dev->tx_pkt_prepare = ixgbe_prep_pkts;
2413 ixgbe_get_tx_queue_offloads(struct rte_eth_dev *dev)
2421 ixgbe_get_tx_port_offloads(struct rte_eth_dev *dev)
2423 uint64_t tx_offload_capa;
2424 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2427 DEV_TX_OFFLOAD_VLAN_INSERT |
2428 DEV_TX_OFFLOAD_IPV4_CKSUM |
2429 DEV_TX_OFFLOAD_UDP_CKSUM |
2430 DEV_TX_OFFLOAD_TCP_CKSUM |
2431 DEV_TX_OFFLOAD_SCTP_CKSUM |
2432 DEV_TX_OFFLOAD_TCP_TSO |
2433 DEV_TX_OFFLOAD_MULTI_SEGS;
2435 if (hw->mac.type == ixgbe_mac_82599EB ||
2436 hw->mac.type == ixgbe_mac_X540)
2437 tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
2439 if (hw->mac.type == ixgbe_mac_X550 ||
2440 hw->mac.type == ixgbe_mac_X550EM_x ||
2441 hw->mac.type == ixgbe_mac_X550EM_a)
2442 tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2444 #ifdef RTE_LIBRTE_SECURITY
2445 if (dev->security_ctx)
2446 tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
2448 return tx_offload_capa;
2451 int __attribute__((cold))
2452 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
2455 unsigned int socket_id,
2456 const struct rte_eth_txconf *tx_conf)
2458 const struct rte_memzone *tz;
2459 struct ixgbe_tx_queue *txq;
2460 struct ixgbe_hw *hw;
2461 uint16_t tx_rs_thresh, tx_free_thresh;
2464 PMD_INIT_FUNC_TRACE();
2465 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2467 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2470 * Validate number of transmit descriptors.
2471 * It must not exceed hardware maximum, and must be multiple
2474 if (nb_desc % IXGBE_TXD_ALIGN != 0 ||
2475 (nb_desc > IXGBE_MAX_RING_DESC) ||
2476 (nb_desc < IXGBE_MIN_RING_DESC)) {
2481 * The following two parameters control the setting of the RS bit on
2482 * transmit descriptors.
2483 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
2484 * descriptors have been used.
2485 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
2486 * descriptors are used or if the number of descriptors required
2487 * to transmit a packet is greater than the number of free TX
2489 * The following constraints must be satisfied:
2490 * tx_rs_thresh must be greater than 0.
2491 * tx_rs_thresh must be less than the size of the ring minus 2.
2492 * tx_rs_thresh must be less than or equal to tx_free_thresh.
2493 * tx_rs_thresh must be a divisor of the ring size.
2494 * tx_free_thresh must be greater than 0.
2495 * tx_free_thresh must be less than the size of the ring minus 3.
2496 * One descriptor in the TX ring is used as a sentinel to avoid a
2497 * H/W race condition, hence the maximum threshold constraints.
2498 * When set to zero use default values.
2500 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2501 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2502 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2503 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2504 if (tx_rs_thresh >= (nb_desc - 2)) {
2505 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
2506 "of TX descriptors minus 2. (tx_rs_thresh=%u "
2507 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2508 (int)dev->data->port_id, (int)queue_idx);
2511 if (tx_rs_thresh > DEFAULT_TX_RS_THRESH) {
2512 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less or equal than %u. "
2513 "(tx_rs_thresh=%u port=%d queue=%d)",
2514 DEFAULT_TX_RS_THRESH, (unsigned int)tx_rs_thresh,
2515 (int)dev->data->port_id, (int)queue_idx);
2518 if (tx_free_thresh >= (nb_desc - 3)) {
2519 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2520 "tx_free_thresh must be less than the number of "
2521 "TX descriptors minus 3. (tx_free_thresh=%u "
2522 "port=%d queue=%d)",
2523 (unsigned int)tx_free_thresh,
2524 (int)dev->data->port_id, (int)queue_idx);
2527 if (tx_rs_thresh > tx_free_thresh) {
2528 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
2529 "tx_free_thresh. (tx_free_thresh=%u "
2530 "tx_rs_thresh=%u port=%d queue=%d)",
2531 (unsigned int)tx_free_thresh,
2532 (unsigned int)tx_rs_thresh,
2533 (int)dev->data->port_id,
2537 if ((nb_desc % tx_rs_thresh) != 0) {
2538 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2539 "number of TX descriptors. (tx_rs_thresh=%u "
2540 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2541 (int)dev->data->port_id, (int)queue_idx);
2546 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
2547 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
2548 * by the NIC and all descriptors are written back after the NIC
2549 * accumulates WTHRESH descriptors.
2551 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2552 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2553 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
2554 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2555 (int)dev->data->port_id, (int)queue_idx);
2559 /* Free memory prior to re-allocation if needed... */
2560 if (dev->data->tx_queues[queue_idx] != NULL) {
2561 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
2562 dev->data->tx_queues[queue_idx] = NULL;
2565 /* First allocate the tx queue data structure */
2566 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct ixgbe_tx_queue),
2567 RTE_CACHE_LINE_SIZE, socket_id);
2572 * Allocate TX ring hardware descriptors. A memzone large enough to
2573 * handle the maximum ring size is allocated in order to allow for
2574 * resizing in later calls to the queue setup function.
2576 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2577 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
2578 IXGBE_ALIGN, socket_id);
2580 ixgbe_tx_queue_release(txq);
2584 txq->nb_tx_desc = nb_desc;
2585 txq->tx_rs_thresh = tx_rs_thresh;
2586 txq->tx_free_thresh = tx_free_thresh;
2587 txq->pthresh = tx_conf->tx_thresh.pthresh;
2588 txq->hthresh = tx_conf->tx_thresh.hthresh;
2589 txq->wthresh = tx_conf->tx_thresh.wthresh;
2590 txq->queue_id = queue_idx;
2591 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2592 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2593 txq->port_id = dev->data->port_id;
2594 txq->offloads = offloads;
2595 txq->ops = &def_txq_ops;
2596 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2597 #ifdef RTE_LIBRTE_SECURITY
2598 txq->using_ipsec = !!(dev->data->dev_conf.txmode.offloads &
2599 DEV_TX_OFFLOAD_SECURITY);
2603 * Modification to set VFTDT for virtual function if vf is detected
2605 if (hw->mac.type == ixgbe_mac_82599_vf ||
2606 hw->mac.type == ixgbe_mac_X540_vf ||
2607 hw->mac.type == ixgbe_mac_X550_vf ||
2608 hw->mac.type == ixgbe_mac_X550EM_x_vf ||
2609 hw->mac.type == ixgbe_mac_X550EM_a_vf)
2610 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
2612 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
2614 txq->tx_ring_phys_addr = tz->iova;
2615 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
2617 /* Allocate software ring */
2618 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
2619 sizeof(struct ixgbe_tx_entry) * nb_desc,
2620 RTE_CACHE_LINE_SIZE, socket_id);
2621 if (txq->sw_ring == NULL) {
2622 ixgbe_tx_queue_release(txq);
2625 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2626 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
2628 /* set up vector or scalar TX function as appropriate */
2629 ixgbe_set_tx_function(dev, txq);
2631 txq->ops->reset(txq);
2633 dev->data->tx_queues[queue_idx] = txq;
2640 * ixgbe_free_sc_cluster - free the not-yet-completed scattered cluster
2642 * The "next" pointer of the last segment of (not-yet-completed) RSC clusters
2643 * in the sw_rsc_ring is not set to NULL but rather points to the next
2644 * mbuf of this RSC aggregation (that has not been completed yet and still
2645 * resides on the HW ring). So, instead of calling for rte_pktmbuf_free() we
2646 * will just free first "nb_segs" segments of the cluster explicitly by calling
2647 * an rte_pktmbuf_free_seg().
2649 * @m scattered cluster head
2651 static void __attribute__((cold))
2652 ixgbe_free_sc_cluster(struct rte_mbuf *m)
2654 uint16_t i, nb_segs = m->nb_segs;
2655 struct rte_mbuf *next_seg;
2657 for (i = 0; i < nb_segs; i++) {
2659 rte_pktmbuf_free_seg(m);
2664 static void __attribute__((cold))
2665 ixgbe_rx_queue_release_mbufs(struct ixgbe_rx_queue *rxq)
2669 #ifdef RTE_IXGBE_INC_VECTOR
2670 /* SSE Vector driver has a different way of releasing mbufs. */
2671 if (rxq->rx_using_sse) {
2672 ixgbe_rx_queue_release_mbufs_vec(rxq);
2677 if (rxq->sw_ring != NULL) {
2678 for (i = 0; i < rxq->nb_rx_desc; i++) {
2679 if (rxq->sw_ring[i].mbuf != NULL) {
2680 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2681 rxq->sw_ring[i].mbuf = NULL;
2684 if (rxq->rx_nb_avail) {
2685 for (i = 0; i < rxq->rx_nb_avail; ++i) {
2686 struct rte_mbuf *mb;
2688 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2689 rte_pktmbuf_free_seg(mb);
2691 rxq->rx_nb_avail = 0;
2695 if (rxq->sw_sc_ring)
2696 for (i = 0; i < rxq->nb_rx_desc; i++)
2697 if (rxq->sw_sc_ring[i].fbuf) {
2698 ixgbe_free_sc_cluster(rxq->sw_sc_ring[i].fbuf);
2699 rxq->sw_sc_ring[i].fbuf = NULL;
2703 static void __attribute__((cold))
2704 ixgbe_rx_queue_release(struct ixgbe_rx_queue *rxq)
2707 ixgbe_rx_queue_release_mbufs(rxq);
2708 rte_free(rxq->sw_ring);
2709 rte_free(rxq->sw_sc_ring);
2714 void __attribute__((cold))
2715 ixgbe_dev_rx_queue_release(void *rxq)
2717 ixgbe_rx_queue_release(rxq);
2721 * Check if Rx Burst Bulk Alloc function can be used.
2723 * 0: the preconditions are satisfied and the bulk allocation function
2725 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2726 * function must be used.
2728 static inline int __attribute__((cold))
2729 check_rx_burst_bulk_alloc_preconditions(struct ixgbe_rx_queue *rxq)
2734 * Make sure the following pre-conditions are satisfied:
2735 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2736 * rxq->rx_free_thresh < rxq->nb_rx_desc
2737 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2738 * Scattered packets are not supported. This should be checked
2739 * outside of this function.
2741 if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
2742 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2743 "rxq->rx_free_thresh=%d, "
2744 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2745 rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
2747 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
2748 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2749 "rxq->rx_free_thresh=%d, "
2750 "rxq->nb_rx_desc=%d",
2751 rxq->rx_free_thresh, rxq->nb_rx_desc);
2753 } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
2754 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2755 "rxq->nb_rx_desc=%d, "
2756 "rxq->rx_free_thresh=%d",
2757 rxq->nb_rx_desc, rxq->rx_free_thresh);
2764 /* Reset dynamic ixgbe_rx_queue fields back to defaults */
2765 static void __attribute__((cold))
2766 ixgbe_reset_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_rx_queue *rxq)
2768 static const union ixgbe_adv_rx_desc zeroed_desc = {{0}};
2770 uint16_t len = rxq->nb_rx_desc;
2773 * By default, the Rx queue setup function allocates enough memory for
2774 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2775 * extra memory at the end of the descriptor ring to be zero'd out.
2777 if (adapter->rx_bulk_alloc_allowed)
2778 /* zero out extra memory */
2779 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2782 * Zero out HW ring memory. Zero out extra memory at the end of
2783 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2784 * reads extra memory as zeros.
2786 for (i = 0; i < len; i++) {
2787 rxq->rx_ring[i] = zeroed_desc;
2791 * initialize extra software ring entries. Space for these extra
2792 * entries is always allocated
2794 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2795 for (i = rxq->nb_rx_desc; i < len; ++i) {
2796 rxq->sw_ring[i].mbuf = &rxq->fake_mbuf;
2799 rxq->rx_nb_avail = 0;
2800 rxq->rx_next_avail = 0;
2801 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2803 rxq->nb_rx_hold = 0;
2804 rxq->pkt_first_seg = NULL;
2805 rxq->pkt_last_seg = NULL;
2807 #ifdef RTE_IXGBE_INC_VECTOR
2808 rxq->rxrearm_start = 0;
2809 rxq->rxrearm_nb = 0;
2814 ixgbe_is_vf(struct rte_eth_dev *dev)
2816 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2818 switch (hw->mac.type) {
2819 case ixgbe_mac_82599_vf:
2820 case ixgbe_mac_X540_vf:
2821 case ixgbe_mac_X550_vf:
2822 case ixgbe_mac_X550EM_x_vf:
2823 case ixgbe_mac_X550EM_a_vf:
2831 ixgbe_get_rx_queue_offloads(struct rte_eth_dev *dev)
2833 uint64_t offloads = 0;
2834 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2836 if (hw->mac.type != ixgbe_mac_82598EB)
2837 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2843 ixgbe_get_rx_port_offloads(struct rte_eth_dev *dev)
2846 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2848 offloads = DEV_RX_OFFLOAD_IPV4_CKSUM |
2849 DEV_RX_OFFLOAD_UDP_CKSUM |
2850 DEV_RX_OFFLOAD_TCP_CKSUM |
2851 DEV_RX_OFFLOAD_KEEP_CRC |
2852 DEV_RX_OFFLOAD_JUMBO_FRAME |
2853 DEV_RX_OFFLOAD_SCATTER;
2855 if (hw->mac.type == ixgbe_mac_82598EB)
2856 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2858 if (ixgbe_is_vf(dev) == 0)
2859 offloads |= (DEV_RX_OFFLOAD_VLAN_FILTER |
2860 DEV_RX_OFFLOAD_VLAN_EXTEND);
2863 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2866 if ((hw->mac.type == ixgbe_mac_82599EB ||
2867 hw->mac.type == ixgbe_mac_X540) &&
2868 !RTE_ETH_DEV_SRIOV(dev).active)
2869 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
2871 if (hw->mac.type == ixgbe_mac_82599EB ||
2872 hw->mac.type == ixgbe_mac_X540)
2873 offloads |= DEV_RX_OFFLOAD_MACSEC_STRIP;
2875 if (hw->mac.type == ixgbe_mac_X550 ||
2876 hw->mac.type == ixgbe_mac_X550EM_x ||
2877 hw->mac.type == ixgbe_mac_X550EM_a)
2878 offloads |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2880 #ifdef RTE_LIBRTE_SECURITY
2881 if (dev->security_ctx)
2882 offloads |= DEV_RX_OFFLOAD_SECURITY;
2888 int __attribute__((cold))
2889 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2892 unsigned int socket_id,
2893 const struct rte_eth_rxconf *rx_conf,
2894 struct rte_mempool *mp)
2896 const struct rte_memzone *rz;
2897 struct ixgbe_rx_queue *rxq;
2898 struct ixgbe_hw *hw;
2900 struct ixgbe_adapter *adapter =
2901 (struct ixgbe_adapter *)dev->data->dev_private;
2904 PMD_INIT_FUNC_TRACE();
2905 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2907 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
2910 * Validate number of receive descriptors.
2911 * It must not exceed hardware maximum, and must be multiple
2914 if (nb_desc % IXGBE_RXD_ALIGN != 0 ||
2915 (nb_desc > IXGBE_MAX_RING_DESC) ||
2916 (nb_desc < IXGBE_MIN_RING_DESC)) {
2920 /* Free memory prior to re-allocation if needed... */
2921 if (dev->data->rx_queues[queue_idx] != NULL) {
2922 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2923 dev->data->rx_queues[queue_idx] = NULL;
2926 /* First allocate the rx queue data structure */
2927 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct ixgbe_rx_queue),
2928 RTE_CACHE_LINE_SIZE, socket_id);
2932 rxq->nb_rx_desc = nb_desc;
2933 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2934 rxq->queue_id = queue_idx;
2935 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2936 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2937 rxq->port_id = dev->data->port_id;
2938 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
2939 rxq->crc_len = ETHER_CRC_LEN;
2942 rxq->drop_en = rx_conf->rx_drop_en;
2943 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2944 rxq->offloads = offloads;
2947 * The packet type in RX descriptor is different for different NICs.
2948 * Some bits are used for x550 but reserved for other NICS.
2949 * So set different masks for different NICs.
2951 if (hw->mac.type == ixgbe_mac_X550 ||
2952 hw->mac.type == ixgbe_mac_X550EM_x ||
2953 hw->mac.type == ixgbe_mac_X550EM_a ||
2954 hw->mac.type == ixgbe_mac_X550_vf ||
2955 hw->mac.type == ixgbe_mac_X550EM_x_vf ||
2956 hw->mac.type == ixgbe_mac_X550EM_a_vf)
2957 rxq->pkt_type_mask = IXGBE_PACKET_TYPE_MASK_X550;
2959 rxq->pkt_type_mask = IXGBE_PACKET_TYPE_MASK_82599;
2962 * Allocate RX ring hardware descriptors. A memzone large enough to
2963 * handle the maximum ring size is allocated in order to allow for
2964 * resizing in later calls to the queue setup function.
2966 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2967 RX_RING_SZ, IXGBE_ALIGN, socket_id);
2969 ixgbe_rx_queue_release(rxq);
2974 * Zero init all the descriptors in the ring.
2976 memset(rz->addr, 0, RX_RING_SZ);
2979 * Modified to setup VFRDT for Virtual Function
2981 if (hw->mac.type == ixgbe_mac_82599_vf ||
2982 hw->mac.type == ixgbe_mac_X540_vf ||
2983 hw->mac.type == ixgbe_mac_X550_vf ||
2984 hw->mac.type == ixgbe_mac_X550EM_x_vf ||
2985 hw->mac.type == ixgbe_mac_X550EM_a_vf) {
2987 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2989 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2992 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2994 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2997 rxq->rx_ring_phys_addr = rz->iova;
2998 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
3001 * Certain constraints must be met in order to use the bulk buffer
3002 * allocation Rx burst function. If any of Rx queues doesn't meet them
3003 * the feature should be disabled for the whole port.
3005 if (check_rx_burst_bulk_alloc_preconditions(rxq)) {
3006 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Rx Bulk Alloc "
3007 "preconditions - canceling the feature for "
3008 "the whole port[%d]",
3009 rxq->queue_id, rxq->port_id);
3010 adapter->rx_bulk_alloc_allowed = false;
3014 * Allocate software ring. Allow for space at the end of the
3015 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
3016 * function does not access an invalid memory region.
3019 if (adapter->rx_bulk_alloc_allowed)
3020 len += RTE_PMD_IXGBE_RX_MAX_BURST;
3022 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
3023 sizeof(struct ixgbe_rx_entry) * len,
3024 RTE_CACHE_LINE_SIZE, socket_id);
3025 if (!rxq->sw_ring) {
3026 ixgbe_rx_queue_release(rxq);
3031 * Always allocate even if it's not going to be needed in order to
3032 * simplify the code.
3034 * This ring is used in LRO and Scattered Rx cases and Scattered Rx may
3035 * be requested in ixgbe_dev_rx_init(), which is called later from
3039 rte_zmalloc_socket("rxq->sw_sc_ring",
3040 sizeof(struct ixgbe_scattered_rx_entry) * len,
3041 RTE_CACHE_LINE_SIZE, socket_id);
3042 if (!rxq->sw_sc_ring) {
3043 ixgbe_rx_queue_release(rxq);
3047 PMD_INIT_LOG(DEBUG, "sw_ring=%p sw_sc_ring=%p hw_ring=%p "
3048 "dma_addr=0x%"PRIx64,
3049 rxq->sw_ring, rxq->sw_sc_ring, rxq->rx_ring,
3050 rxq->rx_ring_phys_addr);
3052 if (!rte_is_power_of_2(nb_desc)) {
3053 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
3054 "preconditions - canceling the feature for "
3055 "the whole port[%d]",
3056 rxq->queue_id, rxq->port_id);
3057 adapter->rx_vec_allowed = false;
3059 ixgbe_rxq_vec_setup(rxq);
3061 dev->data->rx_queues[queue_idx] = rxq;
3063 ixgbe_reset_rx_queue(adapter, rxq);
3069 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3071 #define IXGBE_RXQ_SCAN_INTERVAL 4
3072 volatile union ixgbe_adv_rx_desc *rxdp;
3073 struct ixgbe_rx_queue *rxq;
3076 rxq = dev->data->rx_queues[rx_queue_id];
3077 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
3079 while ((desc < rxq->nb_rx_desc) &&
3080 (rxdp->wb.upper.status_error &
3081 rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))) {
3082 desc += IXGBE_RXQ_SCAN_INTERVAL;
3083 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
3084 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
3085 rxdp = &(rxq->rx_ring[rxq->rx_tail +
3086 desc - rxq->nb_rx_desc]);
3093 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
3095 volatile union ixgbe_adv_rx_desc *rxdp;
3096 struct ixgbe_rx_queue *rxq = rx_queue;
3099 if (unlikely(offset >= rxq->nb_rx_desc))
3101 desc = rxq->rx_tail + offset;
3102 if (desc >= rxq->nb_rx_desc)
3103 desc -= rxq->nb_rx_desc;
3105 rxdp = &rxq->rx_ring[desc];
3106 return !!(rxdp->wb.upper.status_error &
3107 rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD));
3111 ixgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
3113 struct ixgbe_rx_queue *rxq = rx_queue;
3114 volatile uint32_t *status;
3115 uint32_t nb_hold, desc;
3117 if (unlikely(offset >= rxq->nb_rx_desc))
3120 #ifdef RTE_IXGBE_INC_VECTOR
3121 if (rxq->rx_using_sse)
3122 nb_hold = rxq->rxrearm_nb;
3125 nb_hold = rxq->nb_rx_hold;
3126 if (offset >= rxq->nb_rx_desc - nb_hold)
3127 return RTE_ETH_RX_DESC_UNAVAIL;
3129 desc = rxq->rx_tail + offset;
3130 if (desc >= rxq->nb_rx_desc)
3131 desc -= rxq->nb_rx_desc;
3133 status = &rxq->rx_ring[desc].wb.upper.status_error;
3134 if (*status & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))
3135 return RTE_ETH_RX_DESC_DONE;
3137 return RTE_ETH_RX_DESC_AVAIL;
3141 ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
3143 struct ixgbe_tx_queue *txq = tx_queue;
3144 volatile uint32_t *status;
3147 if (unlikely(offset >= txq->nb_tx_desc))
3150 desc = txq->tx_tail + offset;
3151 /* go to next desc that has the RS bit */
3152 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
3154 if (desc >= txq->nb_tx_desc) {
3155 desc -= txq->nb_tx_desc;
3156 if (desc >= txq->nb_tx_desc)
3157 desc -= txq->nb_tx_desc;
3160 status = &txq->tx_ring[desc].wb.status;
3161 if (*status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD))
3162 return RTE_ETH_TX_DESC_DONE;
3164 return RTE_ETH_TX_DESC_FULL;
3167 void __attribute__((cold))
3168 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
3171 struct ixgbe_adapter *adapter =
3172 (struct ixgbe_adapter *)dev->data->dev_private;
3174 PMD_INIT_FUNC_TRACE();
3176 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3177 struct ixgbe_tx_queue *txq = dev->data->tx_queues[i];
3180 txq->ops->release_mbufs(txq);
3181 txq->ops->reset(txq);
3185 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3186 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
3189 ixgbe_rx_queue_release_mbufs(rxq);
3190 ixgbe_reset_rx_queue(adapter, rxq);
3196 ixgbe_dev_free_queues(struct rte_eth_dev *dev)
3200 PMD_INIT_FUNC_TRACE();
3202 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3203 ixgbe_dev_rx_queue_release(dev->data->rx_queues[i]);
3204 dev->data->rx_queues[i] = NULL;
3206 dev->data->nb_rx_queues = 0;
3208 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3209 ixgbe_dev_tx_queue_release(dev->data->tx_queues[i]);
3210 dev->data->tx_queues[i] = NULL;
3212 dev->data->nb_tx_queues = 0;
3215 /*********************************************************************
3217 * Device RX/TX init functions
3219 **********************************************************************/
3222 * Receive Side Scaling (RSS)
3223 * See section 7.1.2.8 in the following document:
3224 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
3227 * The source and destination IP addresses of the IP header and the source
3228 * and destination ports of TCP/UDP headers, if any, of received packets are
3229 * hashed against a configurable random key to compute a 32-bit RSS hash result.
3230 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
3231 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
3232 * RSS output index which is used as the RX queue index where to store the
3234 * The following output is supplied in the RX write-back descriptor:
3235 * - 32-bit result of the Microsoft RSS hash function,
3236 * - 4-bit RSS type field.
3240 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
3241 * Used as the default key.
3243 static uint8_t rss_intel_key[40] = {
3244 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
3245 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
3246 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
3247 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
3248 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
3252 ixgbe_rss_disable(struct rte_eth_dev *dev)
3254 struct ixgbe_hw *hw;
3258 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3259 mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3260 mrqc = IXGBE_READ_REG(hw, mrqc_reg);
3261 mrqc &= ~IXGBE_MRQC_RSSEN;
3262 IXGBE_WRITE_REG(hw, mrqc_reg, mrqc);
3266 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
3276 mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3277 rssrk_reg = ixgbe_rssrk_reg_get(hw->mac.type, 0);
3279 hash_key = rss_conf->rss_key;
3280 if (hash_key != NULL) {
3281 /* Fill in RSS hash key */
3282 for (i = 0; i < 10; i++) {
3283 rss_key = hash_key[(i * 4)];
3284 rss_key |= hash_key[(i * 4) + 1] << 8;
3285 rss_key |= hash_key[(i * 4) + 2] << 16;
3286 rss_key |= hash_key[(i * 4) + 3] << 24;
3287 IXGBE_WRITE_REG_ARRAY(hw, rssrk_reg, i, rss_key);
3291 /* Set configured hashing protocols in MRQC register */
3292 rss_hf = rss_conf->rss_hf;
3293 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
3294 if (rss_hf & ETH_RSS_IPV4)
3295 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
3296 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
3297 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
3298 if (rss_hf & ETH_RSS_IPV6)
3299 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
3300 if (rss_hf & ETH_RSS_IPV6_EX)
3301 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
3302 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
3303 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3304 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
3305 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
3306 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
3307 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3308 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
3309 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3310 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
3311 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
3312 IXGBE_WRITE_REG(hw, mrqc_reg, mrqc);
3316 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
3317 struct rte_eth_rss_conf *rss_conf)
3319 struct ixgbe_hw *hw;
3324 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3326 if (!ixgbe_rss_update_sp(hw->mac.type)) {
3327 PMD_DRV_LOG(ERR, "RSS hash update is not supported on this "
3331 mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3334 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
3335 * "RSS enabling cannot be done dynamically while it must be
3336 * preceded by a software reset"
3337 * Before changing anything, first check that the update RSS operation
3338 * does not attempt to disable RSS, if RSS was enabled at
3339 * initialization time, or does not attempt to enable RSS, if RSS was
3340 * disabled at initialization time.
3342 rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
3343 mrqc = IXGBE_READ_REG(hw, mrqc_reg);
3344 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
3345 if (rss_hf != 0) /* Enable RSS */
3347 return 0; /* Nothing to do */
3350 if (rss_hf == 0) /* Disable RSS */
3352 ixgbe_hw_rss_hash_set(hw, rss_conf);
3357 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
3358 struct rte_eth_rss_conf *rss_conf)
3360 struct ixgbe_hw *hw;
3369 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3370 mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3371 rssrk_reg = ixgbe_rssrk_reg_get(hw->mac.type, 0);
3372 hash_key = rss_conf->rss_key;
3373 if (hash_key != NULL) {
3374 /* Return RSS hash key */
3375 for (i = 0; i < 10; i++) {
3376 rss_key = IXGBE_READ_REG_ARRAY(hw, rssrk_reg, i);
3377 hash_key[(i * 4)] = rss_key & 0x000000FF;
3378 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
3379 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
3380 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
3384 /* Get RSS functions configured in MRQC register */
3385 mrqc = IXGBE_READ_REG(hw, mrqc_reg);
3386 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
3387 rss_conf->rss_hf = 0;
3391 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
3392 rss_hf |= ETH_RSS_IPV4;
3393 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
3394 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
3395 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
3396 rss_hf |= ETH_RSS_IPV6;
3397 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
3398 rss_hf |= ETH_RSS_IPV6_EX;
3399 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
3400 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
3401 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
3402 rss_hf |= ETH_RSS_IPV6_TCP_EX;
3403 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
3404 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
3405 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
3406 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
3407 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
3408 rss_hf |= ETH_RSS_IPV6_UDP_EX;
3409 rss_conf->rss_hf = rss_hf;
3414 ixgbe_rss_configure(struct rte_eth_dev *dev)
3416 struct rte_eth_rss_conf rss_conf;
3417 struct ixgbe_hw *hw;
3421 uint16_t sp_reta_size;
3424 PMD_INIT_FUNC_TRACE();
3425 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3427 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3430 * Fill in redirection table
3431 * The byte-swap is needed because NIC registers are in
3432 * little-endian order.
3435 for (i = 0, j = 0; i < sp_reta_size; i++, j++) {
3436 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3438 if (j == dev->data->nb_rx_queues)
3440 reta = (reta << 8) | j;
3442 IXGBE_WRITE_REG(hw, reta_reg,
3447 * Configure the RSS key and the RSS protocols used to compute
3448 * the RSS hash of input packets.
3450 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
3451 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
3452 ixgbe_rss_disable(dev);
3455 if (rss_conf.rss_key == NULL)
3456 rss_conf.rss_key = rss_intel_key; /* Default hash key */
3457 ixgbe_hw_rss_hash_set(hw, &rss_conf);
3460 #define NUM_VFTA_REGISTERS 128
3461 #define NIC_RX_BUFFER_SIZE 0x200
3462 #define X550_RX_BUFFER_SIZE 0x180
3465 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
3467 struct rte_eth_vmdq_dcb_conf *cfg;
3468 struct ixgbe_hw *hw;
3469 enum rte_eth_nb_pools num_pools;
3470 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
3472 uint8_t nb_tcs; /* number of traffic classes */
3475 PMD_INIT_FUNC_TRACE();
3476 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3477 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3478 num_pools = cfg->nb_queue_pools;
3479 /* Check we have a valid number of pools */
3480 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
3481 ixgbe_rss_disable(dev);
3484 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
3485 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
3489 * split rx buffer up into sections, each for 1 traffic class
3491 switch (hw->mac.type) {
3492 case ixgbe_mac_X550:
3493 case ixgbe_mac_X550EM_x:
3494 case ixgbe_mac_X550EM_a:
3495 pbsize = (uint16_t)(X550_RX_BUFFER_SIZE / nb_tcs);
3498 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3501 for (i = 0; i < nb_tcs; i++) {
3502 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
3504 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
3505 /* clear 10 bits. */
3506 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
3507 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3509 /* zero alloc all unused TCs */
3510 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3511 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
3513 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
3514 /* clear 10 bits. */
3515 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3518 /* MRQC: enable vmdq and dcb */
3519 mrqc = (num_pools == ETH_16_POOLS) ?
3520 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN;
3521 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3523 /* PFVTCTL: turn on virtualisation and set the default pool */
3524 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3525 if (cfg->enable_default_pool) {
3526 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3528 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3531 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3533 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
3535 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
3537 * mapping is done with 3 bits per priority,
3538 * so shift by i*3 each time
3540 queue_mapping |= ((cfg->dcb_tc[i] & 0x07) << (i * 3));
3542 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
3544 /* RTRPCS: DCB related */
3545 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
3547 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3548 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3549 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
3550 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3552 /* VFTA - enable all vlan filters */
3553 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3554 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3557 /* VFRE: pool enabling for receive - 16 or 32 */
3558 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0),
3559 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3562 * MPSAR - allow pools to read specific mac addresses
3563 * In this case, all pools should be able to read from mac addr 0
3565 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
3566 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
3568 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3569 for (i = 0; i < cfg->nb_pool_maps; i++) {
3570 /* set vlan id in VF register and set the valid bit */
3571 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN |
3572 (cfg->pool_map[i].vlan_id & 0xFFF)));
3574 * Put the allowed pools in VFB reg. As we only have 16 or 32
3575 * pools, we only need to use the first half of the register
3578 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
3583 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
3584 * @dev: pointer to eth_dev structure
3585 * @dcb_config: pointer to ixgbe_dcb_config structure
3588 ixgbe_dcb_tx_hw_config(struct rte_eth_dev *dev,
3589 struct ixgbe_dcb_config *dcb_config)
3592 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3594 PMD_INIT_FUNC_TRACE();
3595 if (hw->mac.type != ixgbe_mac_82598EB) {
3596 /* Disable the Tx desc arbiter so that MTQC can be changed */
3597 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3598 reg |= IXGBE_RTTDCS_ARBDIS;
3599 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3601 /* Enable DCB for Tx with 8 TCs */
3602 if (dcb_config->num_tcs.pg_tcs == 8) {
3603 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3605 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3607 if (dcb_config->vt_mode)
3608 reg |= IXGBE_MTQC_VT_ENA;
3609 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3611 /* Enable the Tx desc arbiter */
3612 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3613 reg &= ~IXGBE_RTTDCS_ARBDIS;
3614 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3616 /* Enable Security TX Buffer IFG for DCB */
3617 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3618 reg |= IXGBE_SECTX_DCB;
3619 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
3624 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
3625 * @dev: pointer to rte_eth_dev structure
3626 * @dcb_config: pointer to ixgbe_dcb_config structure
3629 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
3630 struct ixgbe_dcb_config *dcb_config)
3632 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3633 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3634 struct ixgbe_hw *hw =
3635 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3637 PMD_INIT_FUNC_TRACE();
3638 if (hw->mac.type != ixgbe_mac_82598EB)
3639 /*PF VF Transmit Enable*/
3640 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
3641 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3643 /*Configure general DCB TX parameters*/
3644 ixgbe_dcb_tx_hw_config(dev, dcb_config);
3648 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
3649 struct ixgbe_dcb_config *dcb_config)
3651 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
3652 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3653 struct ixgbe_dcb_tc_config *tc;
3656 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3657 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS) {
3658 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3659 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3661 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3662 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3665 /* Initialize User Priority to Traffic Class mapping */
3666 for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3667 tc = &dcb_config->tc_config[j];
3668 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0;
3671 /* User Priority to Traffic Class mapping */
3672 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3673 j = vmdq_rx_conf->dcb_tc[i];
3674 tc = &dcb_config->tc_config[j];
3675 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap |=
3681 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
3682 struct ixgbe_dcb_config *dcb_config)
3684 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3685 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3686 struct ixgbe_dcb_tc_config *tc;
3689 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3690 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS) {
3691 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3692 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3694 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3695 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3698 /* Initialize User Priority to Traffic Class mapping */
3699 for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3700 tc = &dcb_config->tc_config[j];
3701 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0;
3704 /* User Priority to Traffic Class mapping */
3705 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3706 j = vmdq_tx_conf->dcb_tc[i];
3707 tc = &dcb_config->tc_config[j];
3708 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap |=
3714 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
3715 struct ixgbe_dcb_config *dcb_config)
3717 struct rte_eth_dcb_rx_conf *rx_conf =
3718 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
3719 struct ixgbe_dcb_tc_config *tc;
3722 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
3723 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
3725 /* Initialize User Priority to Traffic Class mapping */
3726 for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3727 tc = &dcb_config->tc_config[j];
3728 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0;
3731 /* User Priority to Traffic Class mapping */
3732 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3733 j = rx_conf->dcb_tc[i];
3734 tc = &dcb_config->tc_config[j];
3735 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap |=
3741 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
3742 struct ixgbe_dcb_config *dcb_config)
3744 struct rte_eth_dcb_tx_conf *tx_conf =
3745 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
3746 struct ixgbe_dcb_tc_config *tc;
3749 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
3750 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
3752 /* Initialize User Priority to Traffic Class mapping */
3753 for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3754 tc = &dcb_config->tc_config[j];
3755 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0;
3758 /* User Priority to Traffic Class mapping */
3759 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3760 j = tx_conf->dcb_tc[i];
3761 tc = &dcb_config->tc_config[j];
3762 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap |=
3768 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
3769 * @dev: pointer to eth_dev structure
3770 * @dcb_config: pointer to ixgbe_dcb_config structure
3773 ixgbe_dcb_rx_hw_config(struct rte_eth_dev *dev,
3774 struct ixgbe_dcb_config *dcb_config)
3780 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3782 PMD_INIT_FUNC_TRACE();
3784 * Disable the arbiter before changing parameters
3785 * (always enable recycle mode; WSP)
3787 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
3788 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3790 if (hw->mac.type != ixgbe_mac_82598EB) {
3791 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
3792 if (dcb_config->num_tcs.pg_tcs == 4) {
3793 if (dcb_config->vt_mode)
3794 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3795 IXGBE_MRQC_VMDQRT4TCEN;
3797 /* no matter the mode is DCB or DCB_RSS, just
3798 * set the MRQE to RSSXTCEN. RSS is controlled
3801 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3802 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3803 IXGBE_MRQC_RTRSS4TCEN;
3806 if (dcb_config->num_tcs.pg_tcs == 8) {
3807 if (dcb_config->vt_mode)
3808 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3809 IXGBE_MRQC_VMDQRT8TCEN;
3811 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3812 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3813 IXGBE_MRQC_RTRSS8TCEN;
3817 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
3819 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3820 /* Disable drop for all queues in VMDQ mode*/
3821 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3822 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3824 (q << IXGBE_QDE_IDX_SHIFT)));
3826 /* Enable drop for all queues in SRIOV mode */
3827 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3828 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3830 (q << IXGBE_QDE_IDX_SHIFT) |
3835 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3836 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3837 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
3838 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3840 /* VFTA - enable all vlan filters */
3841 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3842 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3846 * Configure Rx packet plane (recycle mode; WSP) and
3849 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
3850 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3854 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
3855 uint16_t *max, uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3857 switch (hw->mac.type) {
3858 case ixgbe_mac_82598EB:
3859 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
3861 case ixgbe_mac_82599EB:
3862 case ixgbe_mac_X540:
3863 case ixgbe_mac_X550:
3864 case ixgbe_mac_X550EM_x:
3865 case ixgbe_mac_X550EM_a:
3866 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
3875 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
3876 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3878 switch (hw->mac.type) {
3879 case ixgbe_mac_82598EB:
3880 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id, tsa);
3881 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id, tsa);
3883 case ixgbe_mac_82599EB:
3884 case ixgbe_mac_X540:
3885 case ixgbe_mac_X550:
3886 case ixgbe_mac_X550EM_x:
3887 case ixgbe_mac_X550EM_a:
3888 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id, tsa);
3889 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id, tsa, map);
3896 #define DCB_RX_CONFIG 1
3897 #define DCB_TX_CONFIG 1
3898 #define DCB_TX_PB 1024
3900 * ixgbe_dcb_hw_configure - Enable DCB and configure
3901 * general DCB in VT mode and non-VT mode parameters
3902 * @dev: pointer to rte_eth_dev structure
3903 * @dcb_config: pointer to ixgbe_dcb_config structure
3906 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
3907 struct ixgbe_dcb_config *dcb_config)
3910 uint8_t i, pfc_en, nb_tcs;
3911 uint16_t pbsize, rx_buffer_size;
3912 uint8_t config_dcb_rx = 0;
3913 uint8_t config_dcb_tx = 0;
3914 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3915 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3916 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3917 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3918 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3919 struct ixgbe_dcb_tc_config *tc;
3920 uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3921 struct ixgbe_hw *hw =
3922 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3923 struct ixgbe_bw_conf *bw_conf =
3924 IXGBE_DEV_PRIVATE_TO_BW_CONF(dev->data->dev_private);
3926 switch (dev->data->dev_conf.rxmode.mq_mode) {
3927 case ETH_MQ_RX_VMDQ_DCB:
3928 dcb_config->vt_mode = true;
3929 if (hw->mac.type != ixgbe_mac_82598EB) {
3930 config_dcb_rx = DCB_RX_CONFIG;
3932 *get dcb and VT rx configuration parameters
3935 ixgbe_vmdq_dcb_rx_config(dev, dcb_config);
3936 /*Configure general VMDQ and DCB RX parameters*/
3937 ixgbe_vmdq_dcb_configure(dev);
3941 case ETH_MQ_RX_DCB_RSS:
3942 dcb_config->vt_mode = false;
3943 config_dcb_rx = DCB_RX_CONFIG;
3944 /* Get dcb TX configuration parameters from rte_eth_conf */
3945 ixgbe_dcb_rx_config(dev, dcb_config);
3946 /*Configure general DCB RX parameters*/
3947 ixgbe_dcb_rx_hw_config(dev, dcb_config);
3950 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
3953 switch (dev->data->dev_conf.txmode.mq_mode) {
3954 case ETH_MQ_TX_VMDQ_DCB:
3955 dcb_config->vt_mode = true;
3956 config_dcb_tx = DCB_TX_CONFIG;
3957 /* get DCB and VT TX configuration parameters
3960 ixgbe_dcb_vt_tx_config(dev, dcb_config);
3961 /*Configure general VMDQ and DCB TX parameters*/
3962 ixgbe_vmdq_dcb_hw_tx_config(dev, dcb_config);
3966 dcb_config->vt_mode = false;
3967 config_dcb_tx = DCB_TX_CONFIG;
3968 /*get DCB TX configuration parameters from rte_eth_conf*/
3969 ixgbe_dcb_tx_config(dev, dcb_config);
3970 /*Configure general DCB TX parameters*/
3971 ixgbe_dcb_tx_hw_config(dev, dcb_config);
3974 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
3978 nb_tcs = dcb_config->num_tcs.pfc_tcs;
3980 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3981 if (nb_tcs == ETH_4_TCS) {
3982 /* Avoid un-configured priority mapping to TC0 */
3984 uint8_t mask = 0xFF;
3986 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
3987 mask = (uint8_t)(mask & (~(1 << map[i])));
3988 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
3989 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
3993 /* Re-configure 4 TCs BW */
3994 for (i = 0; i < nb_tcs; i++) {
3995 tc = &dcb_config->tc_config[i];
3996 if (bw_conf->tc_num != nb_tcs)
3997 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
3998 (uint8_t)(100 / nb_tcs);
3999 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
4000 (uint8_t)(100 / nb_tcs);
4002 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4003 tc = &dcb_config->tc_config[i];
4004 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
4005 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
4008 /* Re-configure 8 TCs BW */
4009 for (i = 0; i < nb_tcs; i++) {
4010 tc = &dcb_config->tc_config[i];
4011 if (bw_conf->tc_num != nb_tcs)
4012 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
4013 (uint8_t)(100 / nb_tcs + (i & 1));
4014 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
4015 (uint8_t)(100 / nb_tcs + (i & 1));
4019 switch (hw->mac.type) {
4020 case ixgbe_mac_X550:
4021 case ixgbe_mac_X550EM_x:
4022 case ixgbe_mac_X550EM_a:
4023 rx_buffer_size = X550_RX_BUFFER_SIZE;
4026 rx_buffer_size = NIC_RX_BUFFER_SIZE;
4030 if (config_dcb_rx) {
4031 /* Set RX buffer size */
4032 pbsize = (uint16_t)(rx_buffer_size / nb_tcs);
4033 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
4035 for (i = 0; i < nb_tcs; i++) {
4036 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
4038 /* zero alloc all unused TCs */
4039 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
4040 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4043 if (config_dcb_tx) {
4044 /* Only support an equally distributed
4045 * Tx packet buffer strategy.
4047 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
4048 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
4050 for (i = 0; i < nb_tcs; i++) {
4051 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4052 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4054 /* Clear unused TCs, if any, to zero buffer size*/
4055 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
4056 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4057 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4061 /*Calculates traffic class credits*/
4062 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config, max_frame,
4063 IXGBE_DCB_TX_CONFIG);
4064 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config, max_frame,
4065 IXGBE_DCB_RX_CONFIG);
4067 if (config_dcb_rx) {
4068 /* Unpack CEE standard containers */
4069 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
4070 ixgbe_dcb_unpack_max_cee(dcb_config, max);
4071 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
4072 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
4073 /* Configure PG(ETS) RX */
4074 ixgbe_dcb_hw_arbite_rx_config(hw, refill, max, bwgid, tsa, map);
4077 if (config_dcb_tx) {
4078 /* Unpack CEE standard containers */
4079 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
4080 ixgbe_dcb_unpack_max_cee(dcb_config, max);
4081 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
4082 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
4083 /* Configure PG(ETS) TX */
4084 ixgbe_dcb_hw_arbite_tx_config(hw, refill, max, bwgid, tsa, map);
4087 /*Configure queue statistics registers*/
4088 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
4090 /* Check if the PFC is supported */
4091 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
4092 pbsize = (uint16_t)(rx_buffer_size / nb_tcs);
4093 for (i = 0; i < nb_tcs; i++) {
4095 * If the TC count is 8,and the default high_water is 48,
4096 * the low_water is 16 as default.
4098 hw->fc.high_water[i] = (pbsize * 3) / 4;
4099 hw->fc.low_water[i] = pbsize / 4;
4100 /* Enable pfc for this TC */
4101 tc = &dcb_config->tc_config[i];
4102 tc->pfc = ixgbe_dcb_pfc_enabled;
4104 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
4105 if (dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
4107 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
4114 * ixgbe_configure_dcb - Configure DCB Hardware
4115 * @dev: pointer to rte_eth_dev
4117 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
4119 struct ixgbe_dcb_config *dcb_cfg =
4120 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4121 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
4123 PMD_INIT_FUNC_TRACE();
4125 /* check support mq_mode for DCB */
4126 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
4127 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB) &&
4128 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB_RSS))
4131 if (dev->data->nb_rx_queues > ETH_DCB_NUM_QUEUES)
4134 /** Configure DCB hardware **/
4135 ixgbe_dcb_hw_configure(dev, dcb_cfg);
4139 * VMDq only support for 10 GbE NIC.
4142 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
4144 struct rte_eth_vmdq_rx_conf *cfg;
4145 struct ixgbe_hw *hw;
4146 enum rte_eth_nb_pools num_pools;
4147 uint32_t mrqc, vt_ctl, vlanctrl;
4151 PMD_INIT_FUNC_TRACE();
4152 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4153 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
4154 num_pools = cfg->nb_queue_pools;
4156 ixgbe_rss_disable(dev);
4158 /* MRQC: enable vmdq */
4159 mrqc = IXGBE_MRQC_VMDQEN;
4160 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
4162 /* PFVTCTL: turn on virtualisation and set the default pool */
4163 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
4164 if (cfg->enable_default_pool)
4165 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
4167 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
4169 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
4171 for (i = 0; i < (int)num_pools; i++) {
4172 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
4173 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
4176 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
4177 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4178 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
4179 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
4181 /* VFTA - enable all vlan filters */
4182 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
4183 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
4185 /* VFRE: pool enabling for receive - 64 */
4186 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
4187 if (num_pools == ETH_64_POOLS)
4188 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
4191 * MPSAR - allow pools to read specific mac addresses
4192 * In this case, all pools should be able to read from mac addr 0
4194 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
4195 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
4197 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
4198 for (i = 0; i < cfg->nb_pool_maps; i++) {
4199 /* set vlan id in VF register and set the valid bit */
4200 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN |
4201 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
4203 * Put the allowed pools in VFB reg. As we only have 16 or 64
4204 * pools, we only need to use the first half of the register
4207 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
4208 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i * 2),
4209 (cfg->pool_map[i].pools & UINT32_MAX));
4211 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i * 2 + 1)),
4212 ((cfg->pool_map[i].pools >> 32) & UINT32_MAX));
4216 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
4217 if (cfg->enable_loop_back) {
4218 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
4219 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
4220 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
4223 IXGBE_WRITE_FLUSH(hw);
4227 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
4228 * @hw: pointer to hardware structure
4231 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
4236 PMD_INIT_FUNC_TRACE();
4237 /*PF VF Transmit Enable*/
4238 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
4239 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
4241 /* Disable the Tx desc arbiter so that MTQC can be changed */
4242 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
4243 reg |= IXGBE_RTTDCS_ARBDIS;
4244 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
4246 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
4247 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
4249 /* Disable drop for all queues */
4250 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
4251 IXGBE_WRITE_REG(hw, IXGBE_QDE,
4252 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
4254 /* Enable the Tx desc arbiter */
4255 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
4256 reg &= ~IXGBE_RTTDCS_ARBDIS;
4257 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
4259 IXGBE_WRITE_FLUSH(hw);
4262 static int __attribute__((cold))
4263 ixgbe_alloc_rx_queue_mbufs(struct ixgbe_rx_queue *rxq)
4265 struct ixgbe_rx_entry *rxe = rxq->sw_ring;
4269 /* Initialize software ring entries */
4270 for (i = 0; i < rxq->nb_rx_desc; i++) {
4271 volatile union ixgbe_adv_rx_desc *rxd;
4272 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
4275 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
4276 (unsigned) rxq->queue_id);
4280 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
4281 mbuf->port = rxq->port_id;
4284 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
4285 rxd = &rxq->rx_ring[i];
4286 rxd->read.hdr_addr = 0;
4287 rxd->read.pkt_addr = dma_addr;
4295 ixgbe_config_vf_rss(struct rte_eth_dev *dev)
4297 struct ixgbe_hw *hw;
4300 ixgbe_rss_configure(dev);
4302 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4304 /* MRQC: enable VF RSS */
4305 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
4306 mrqc &= ~IXGBE_MRQC_MRQE_MASK;
4307 switch (RTE_ETH_DEV_SRIOV(dev).active) {
4309 mrqc |= IXGBE_MRQC_VMDQRSS64EN;
4313 mrqc |= IXGBE_MRQC_VMDQRSS32EN;
4317 PMD_INIT_LOG(ERR, "Invalid pool number in IOV mode with VMDQ RSS");
4321 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
4327 ixgbe_config_vf_default(struct rte_eth_dev *dev)
4329 struct ixgbe_hw *hw =
4330 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4332 switch (RTE_ETH_DEV_SRIOV(dev).active) {
4334 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
4339 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
4340 IXGBE_MRQC_VMDQRT4TCEN);
4344 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
4345 IXGBE_MRQC_VMDQRT8TCEN);
4349 "invalid pool number in IOV mode");
4356 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
4358 struct ixgbe_hw *hw =
4359 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4361 if (hw->mac.type == ixgbe_mac_82598EB)
4364 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
4366 * SRIOV inactive scheme
4367 * any DCB/RSS w/o VMDq multi-queue setting
4369 switch (dev->data->dev_conf.rxmode.mq_mode) {
4371 case ETH_MQ_RX_DCB_RSS:
4372 case ETH_MQ_RX_VMDQ_RSS:
4373 ixgbe_rss_configure(dev);
4376 case ETH_MQ_RX_VMDQ_DCB:
4377 ixgbe_vmdq_dcb_configure(dev);
4380 case ETH_MQ_RX_VMDQ_ONLY:
4381 ixgbe_vmdq_rx_hw_configure(dev);
4384 case ETH_MQ_RX_NONE:
4386 /* if mq_mode is none, disable rss mode.*/
4387 ixgbe_rss_disable(dev);
4391 /* SRIOV active scheme
4392 * Support RSS together with SRIOV.
4394 switch (dev->data->dev_conf.rxmode.mq_mode) {
4396 case ETH_MQ_RX_VMDQ_RSS:
4397 ixgbe_config_vf_rss(dev);
4399 case ETH_MQ_RX_VMDQ_DCB:
4401 /* In SRIOV, the configuration is the same as VMDq case */
4402 ixgbe_vmdq_dcb_configure(dev);
4404 /* DCB/RSS together with SRIOV is not supported */
4405 case ETH_MQ_RX_VMDQ_DCB_RSS:
4406 case ETH_MQ_RX_DCB_RSS:
4408 "Could not support DCB/RSS with VMDq & SRIOV");
4411 ixgbe_config_vf_default(dev);
4420 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
4422 struct ixgbe_hw *hw =
4423 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4427 if (hw->mac.type == ixgbe_mac_82598EB)
4430 /* disable arbiter before setting MTQC */
4431 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
4432 rttdcs |= IXGBE_RTTDCS_ARBDIS;
4433 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
4435 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
4437 * SRIOV inactive scheme
4438 * any DCB w/o VMDq multi-queue setting
4440 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
4441 ixgbe_vmdq_tx_hw_configure(hw);
4443 mtqc = IXGBE_MTQC_64Q_1PB;
4444 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
4447 switch (RTE_ETH_DEV_SRIOV(dev).active) {
4450 * SRIOV active scheme
4451 * FIXME if support DCB together with VMDq & SRIOV
4454 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
4457 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
4460 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
4464 mtqc = IXGBE_MTQC_64Q_1PB;
4465 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
4467 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
4470 /* re-enable arbiter */
4471 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
4472 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
4478 * ixgbe_get_rscctl_maxdesc - Calculate the RSCCTL[n].MAXDESC for PF
4480 * Return the RSCCTL[n].MAXDESC for 82599 and x540 PF devices according to the
4481 * spec rev. 3.0 chapter 8.2.3.8.13.
4483 * @pool Memory pool of the Rx queue
4485 static inline uint32_t
4486 ixgbe_get_rscctl_maxdesc(struct rte_mempool *pool)
4488 struct rte_pktmbuf_pool_private *mp_priv = rte_mempool_get_priv(pool);
4490 /* MAXDESC * SRRCTL.BSIZEPKT must not exceed 64 KB minus one */
4493 (mp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM);
4496 return IXGBE_RSCCTL_MAXDESC_16;
4497 else if (maxdesc >= 8)
4498 return IXGBE_RSCCTL_MAXDESC_8;
4499 else if (maxdesc >= 4)
4500 return IXGBE_RSCCTL_MAXDESC_4;
4502 return IXGBE_RSCCTL_MAXDESC_1;
4506 * ixgbe_set_ivar - Setup the correct IVAR register for a particular MSIX
4509 * (Taken from FreeBSD tree)
4510 * (yes this is all very magic and confusing :)
4513 * @entry the register array entry
4514 * @vector the MSIX vector for this queue
4518 ixgbe_set_ivar(struct rte_eth_dev *dev, u8 entry, u8 vector, s8 type)
4520 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4523 vector |= IXGBE_IVAR_ALLOC_VAL;
4525 switch (hw->mac.type) {
4527 case ixgbe_mac_82598EB:
4529 entry = IXGBE_IVAR_OTHER_CAUSES_INDEX;
4531 entry += (type * 64);
4532 index = (entry >> 2) & 0x1F;
4533 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
4534 ivar &= ~(0xFF << (8 * (entry & 0x3)));
4535 ivar |= (vector << (8 * (entry & 0x3)));
4536 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
4539 case ixgbe_mac_82599EB:
4540 case ixgbe_mac_X540:
4541 if (type == -1) { /* MISC IVAR */
4542 index = (entry & 1) * 8;
4543 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4544 ivar &= ~(0xFF << index);
4545 ivar |= (vector << index);
4546 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
4547 } else { /* RX/TX IVARS */
4548 index = (16 * (entry & 1)) + (8 * type);
4549 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1));
4550 ivar &= ~(0xFF << index);
4551 ivar |= (vector << index);
4552 IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar);
4562 void __attribute__((cold))
4563 ixgbe_set_rx_function(struct rte_eth_dev *dev)
4565 uint16_t i, rx_using_sse;
4566 struct ixgbe_adapter *adapter =
4567 (struct ixgbe_adapter *)dev->data->dev_private;
4570 * In order to allow Vector Rx there are a few configuration
4571 * conditions to be met and Rx Bulk Allocation should be allowed.
4573 if (ixgbe_rx_vec_dev_conf_condition_check(dev) ||
4574 !adapter->rx_bulk_alloc_allowed) {
4575 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx "
4576 "preconditions or RTE_IXGBE_INC_VECTOR is "
4578 dev->data->port_id);
4580 adapter->rx_vec_allowed = false;
4584 * Initialize the appropriate LRO callback.
4586 * If all queues satisfy the bulk allocation preconditions
4587 * (hw->rx_bulk_alloc_allowed is TRUE) then we may use bulk allocation.
4588 * Otherwise use a single allocation version.
4590 if (dev->data->lro) {
4591 if (adapter->rx_bulk_alloc_allowed) {
4592 PMD_INIT_LOG(DEBUG, "LRO is requested. Using a bulk "
4593 "allocation version");
4594 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
4596 PMD_INIT_LOG(DEBUG, "LRO is requested. Using a single "
4597 "allocation version");
4598 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
4600 } else if (dev->data->scattered_rx) {
4602 * Set the non-LRO scattered callback: there are Vector and
4603 * single allocation versions.
4605 if (adapter->rx_vec_allowed) {
4606 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
4607 "callback (port=%d).",
4608 dev->data->port_id);
4610 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
4611 } else if (adapter->rx_bulk_alloc_allowed) {
4612 PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
4613 "allocation callback (port=%d).",
4614 dev->data->port_id);
4615 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
4617 PMD_INIT_LOG(DEBUG, "Using Regualr (non-vector, "
4618 "single allocation) "
4619 "Scattered Rx callback "
4621 dev->data->port_id);
4623 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
4626 * Below we set "simple" callbacks according to port/queues parameters.
4627 * If parameters allow we are going to choose between the following
4631 * - Single buffer allocation (the simplest one)
4633 } else if (adapter->rx_vec_allowed) {
4634 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
4635 "burst size no less than %d (port=%d).",
4636 RTE_IXGBE_DESCS_PER_LOOP,
4637 dev->data->port_id);
4639 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
4640 } else if (adapter->rx_bulk_alloc_allowed) {
4641 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
4642 "satisfied. Rx Burst Bulk Alloc function "
4643 "will be used on port=%d.",
4644 dev->data->port_id);
4646 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
4648 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
4649 "satisfied, or Scattered Rx is requested "
4651 dev->data->port_id);
4653 dev->rx_pkt_burst = ixgbe_recv_pkts;
4656 /* Propagate information about RX function choice through all queues. */
4659 (dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec ||
4660 dev->rx_pkt_burst == ixgbe_recv_pkts_vec);
4662 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4663 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4665 rxq->rx_using_sse = rx_using_sse;
4666 #ifdef RTE_LIBRTE_SECURITY
4667 rxq->using_ipsec = !!(dev->data->dev_conf.rxmode.offloads &
4668 DEV_RX_OFFLOAD_SECURITY);
4674 * ixgbe_set_rsc - configure RSC related port HW registers
4676 * Configures the port's RSC related registers according to the 4.6.7.2 chapter
4677 * of 82599 Spec (x540 configuration is virtually the same).
4681 * Returns 0 in case of success or a non-zero error code
4684 ixgbe_set_rsc(struct rte_eth_dev *dev)
4686 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4687 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4688 struct rte_eth_dev_info dev_info = { 0 };
4689 bool rsc_capable = false;
4695 dev->dev_ops->dev_infos_get(dev, &dev_info);
4696 if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_TCP_LRO)
4699 if (!rsc_capable && (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO)) {
4700 PMD_INIT_LOG(CRIT, "LRO is requested on HW that doesn't "
4705 /* RSC global configuration (chapter 4.6.7.2.1 of 82599 Spec) */
4707 if ((rx_conf->offloads & DEV_RX_OFFLOAD_KEEP_CRC) &&
4708 (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO)) {
4710 * According to chapter of 4.6.7.2.1 of the Spec Rev.
4711 * 3.0 RSC configuration requires HW CRC stripping being
4712 * enabled. If user requested both HW CRC stripping off
4713 * and RSC on - return an error.
4715 PMD_INIT_LOG(CRIT, "LRO can't be enabled when HW CRC "
4720 /* RFCTL configuration */
4721 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4722 if ((rsc_capable) && (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO))
4724 * Since NFS packets coalescing is not supported - clear
4725 * RFCTL.NFSW_DIS and RFCTL.NFSR_DIS when RSC is
4728 rfctl &= ~(IXGBE_RFCTL_RSC_DIS | IXGBE_RFCTL_NFSW_DIS |
4729 IXGBE_RFCTL_NFSR_DIS);
4731 rfctl |= IXGBE_RFCTL_RSC_DIS;
4732 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4734 /* If LRO hasn't been requested - we are done here. */
4735 if (!(rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO))
4738 /* Set RDRXCTL.RSCACKC bit */
4739 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4740 rdrxctl |= IXGBE_RDRXCTL_RSCACKC;
4741 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4743 /* Per-queue RSC configuration (chapter 4.6.7.2.2 of 82599 Spec) */
4744 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4745 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4747 IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxq->reg_idx));
4749 IXGBE_READ_REG(hw, IXGBE_RSCCTL(rxq->reg_idx));
4751 IXGBE_READ_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx));
4753 IXGBE_READ_REG(hw, IXGBE_EITR(rxq->reg_idx));
4756 * ixgbe PMD doesn't support header-split at the moment.
4758 * Following the 4.6.7.2.1 chapter of the 82599/x540
4759 * Spec if RSC is enabled the SRRCTL[n].BSIZEHEADER
4760 * should be configured even if header split is not
4761 * enabled. We will configure it 128 bytes following the
4762 * recommendation in the spec.
4764 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
4765 srrctl |= (128 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4766 IXGBE_SRRCTL_BSIZEHDR_MASK;
4769 * TODO: Consider setting the Receive Descriptor Minimum
4770 * Threshold Size for an RSC case. This is not an obviously
4771 * beneficiary option but the one worth considering...
4774 rscctl |= IXGBE_RSCCTL_RSCEN;
4775 rscctl |= ixgbe_get_rscctl_maxdesc(rxq->mb_pool);
4776 psrtype |= IXGBE_PSRTYPE_TCPHDR;
4779 * RSC: Set ITR interval corresponding to 2K ints/s.
4781 * Full-sized RSC aggregations for a 10Gb/s link will
4782 * arrive at about 20K aggregation/s rate.
4784 * 2K inst/s rate will make only 10% of the
4785 * aggregations to be closed due to the interrupt timer
4786 * expiration for a streaming at wire-speed case.
4788 * For a sparse streaming case this setting will yield
4789 * at most 500us latency for a single RSC aggregation.
4791 eitr &= ~IXGBE_EITR_ITR_INT_MASK;
4792 eitr |= IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT);
4793 eitr |= IXGBE_EITR_CNT_WDIS;
4795 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4796 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(rxq->reg_idx), rscctl);
4797 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
4798 IXGBE_WRITE_REG(hw, IXGBE_EITR(rxq->reg_idx), eitr);
4801 * RSC requires the mapping of the queue to the
4804 ixgbe_set_ivar(dev, rxq->reg_idx, i, 0);
4809 PMD_INIT_LOG(DEBUG, "enabling LRO mode");
4815 * Initializes Receive Unit.
4817 int __attribute__((cold))
4818 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
4820 struct ixgbe_hw *hw;
4821 struct ixgbe_rx_queue *rxq;
4832 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4835 PMD_INIT_FUNC_TRACE();
4836 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4839 * Make sure receives are disabled while setting
4840 * up the RX context (registers, descriptor rings, etc.).
4842 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4843 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4845 /* Enable receipt of broadcasted frames */
4846 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4847 fctrl |= IXGBE_FCTRL_BAM;
4848 fctrl |= IXGBE_FCTRL_DPF;
4849 fctrl |= IXGBE_FCTRL_PMCF;
4850 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4853 * Configure CRC stripping, if any.
4855 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4856 if (rx_conf->offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4857 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
4859 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
4862 * Configure jumbo frame support, if any.
4864 if (rx_conf->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
4865 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4866 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4867 maxfrs &= 0x0000FFFF;
4868 maxfrs |= (rx_conf->max_rx_pkt_len << 16);
4869 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4871 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4874 * If loopback mode is configured for 82599, set LPBK bit.
4876 if (hw->mac.type == ixgbe_mac_82599EB &&
4877 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
4878 hlreg0 |= IXGBE_HLREG0_LPBK;
4880 hlreg0 &= ~IXGBE_HLREG0_LPBK;
4882 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4885 * Assume no header split and no VLAN strip support
4886 * on any Rx queue first .
4888 rx_conf->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
4889 /* Setup RX queues */
4890 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4891 rxq = dev->data->rx_queues[i];
4894 * Reset crc_len in case it was changed after queue setup by a
4895 * call to configure.
4897 if (rx_conf->offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4898 rxq->crc_len = ETHER_CRC_LEN;
4902 /* Setup the Base and Length of the Rx Descriptor Rings */
4903 bus_addr = rxq->rx_ring_phys_addr;
4904 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
4905 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4906 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
4907 (uint32_t)(bus_addr >> 32));
4908 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
4909 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4910 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
4911 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
4913 /* Configure the SRRCTL register */
4914 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4916 /* Set if packets are dropped when no descriptors available */
4918 srrctl |= IXGBE_SRRCTL_DROP_EN;
4921 * Configure the RX buffer size in the BSIZEPACKET field of
4922 * the SRRCTL register of the queue.
4923 * The value is in 1 KB resolution. Valid values can be from
4926 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
4927 RTE_PKTMBUF_HEADROOM);
4928 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4929 IXGBE_SRRCTL_BSIZEPKT_MASK);
4931 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4933 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4934 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4936 /* It adds dual VLAN length for supporting dual VLAN */
4937 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4938 2 * IXGBE_VLAN_TAG_SIZE > buf_size)
4939 dev->data->scattered_rx = 1;
4940 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4941 rx_conf->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
4944 if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)
4945 dev->data->scattered_rx = 1;
4948 * Device configured with multiple RX queues.
4950 ixgbe_dev_mq_rx_configure(dev);
4953 * Setup the Checksum Register.
4954 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
4955 * Enable IP/L4 checkum computation by hardware if requested to do so.
4957 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
4958 rxcsum |= IXGBE_RXCSUM_PCSD;
4959 if (rx_conf->offloads & DEV_RX_OFFLOAD_CHECKSUM)
4960 rxcsum |= IXGBE_RXCSUM_IPPCSE;
4962 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
4964 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
4966 if (hw->mac.type == ixgbe_mac_82599EB ||
4967 hw->mac.type == ixgbe_mac_X540) {
4968 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4969 if (rx_conf->offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4970 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
4972 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4973 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4974 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4977 rc = ixgbe_set_rsc(dev);
4981 ixgbe_set_rx_function(dev);
4987 * Initializes Transmit Unit.
4989 void __attribute__((cold))
4990 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
4992 struct ixgbe_hw *hw;
4993 struct ixgbe_tx_queue *txq;
4999 PMD_INIT_FUNC_TRACE();
5000 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5002 /* Enable TX CRC (checksum offload requirement) and hw padding
5005 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5006 hlreg0 |= (IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);
5007 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5009 /* Setup the Base and Length of the Tx Descriptor Rings */
5010 for (i = 0; i < dev->data->nb_tx_queues; i++) {
5011 txq = dev->data->tx_queues[i];
5013 bus_addr = txq->tx_ring_phys_addr;
5014 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
5015 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
5016 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
5017 (uint32_t)(bus_addr >> 32));
5018 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
5019 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
5020 /* Setup the HW Tx Head and TX Tail descriptor pointers */
5021 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
5022 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
5025 * Disable Tx Head Writeback RO bit, since this hoses
5026 * bookkeeping if things aren't delivered in order.
5028 switch (hw->mac.type) {
5029 case ixgbe_mac_82598EB:
5030 txctrl = IXGBE_READ_REG(hw,
5031 IXGBE_DCA_TXCTRL(txq->reg_idx));
5032 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
5033 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
5037 case ixgbe_mac_82599EB:
5038 case ixgbe_mac_X540:
5039 case ixgbe_mac_X550:
5040 case ixgbe_mac_X550EM_x:
5041 case ixgbe_mac_X550EM_a:
5043 txctrl = IXGBE_READ_REG(hw,
5044 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
5045 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
5046 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
5052 /* Device configured with multiple TX queues. */
5053 ixgbe_dev_mq_tx_configure(dev);
5057 * Set up link for 82599 loopback mode Tx->Rx.
5059 static inline void __attribute__((cold))
5060 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
5062 PMD_INIT_FUNC_TRACE();
5064 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
5065 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
5067 PMD_INIT_LOG(ERR, "Could not enable loopback mode");
5076 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
5077 ixgbe_reset_pipeline_82599(hw);
5079 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
5085 * Start Transmit and Receive Units.
5087 int __attribute__((cold))
5088 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
5090 struct ixgbe_hw *hw;
5091 struct ixgbe_tx_queue *txq;
5092 struct ixgbe_rx_queue *rxq;
5099 PMD_INIT_FUNC_TRACE();
5100 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5102 for (i = 0; i < dev->data->nb_tx_queues; i++) {
5103 txq = dev->data->tx_queues[i];
5104 /* Setup Transmit Threshold Registers */
5105 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
5106 txdctl |= txq->pthresh & 0x7F;
5107 txdctl |= ((txq->hthresh & 0x7F) << 8);
5108 txdctl |= ((txq->wthresh & 0x7F) << 16);
5109 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
5112 if (hw->mac.type != ixgbe_mac_82598EB) {
5113 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
5114 dmatxctl |= IXGBE_DMATXCTL_TE;
5115 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
5118 for (i = 0; i < dev->data->nb_tx_queues; i++) {
5119 txq = dev->data->tx_queues[i];
5120 if (!txq->tx_deferred_start) {
5121 ret = ixgbe_dev_tx_queue_start(dev, i);
5127 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5128 rxq = dev->data->rx_queues[i];
5129 if (!rxq->rx_deferred_start) {
5130 ret = ixgbe_dev_rx_queue_start(dev, i);
5136 /* Enable Receive engine */
5137 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5138 if (hw->mac.type == ixgbe_mac_82598EB)
5139 rxctrl |= IXGBE_RXCTRL_DMBYPS;
5140 rxctrl |= IXGBE_RXCTRL_RXEN;
5141 hw->mac.ops.enable_rx_dma(hw, rxctrl);
5143 /* If loopback mode is enabled for 82599, set up the link accordingly */
5144 if (hw->mac.type == ixgbe_mac_82599EB &&
5145 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
5146 ixgbe_setup_loopback_link_82599(hw);
5148 #ifdef RTE_LIBRTE_SECURITY
5149 if ((dev->data->dev_conf.rxmode.offloads &
5150 DEV_RX_OFFLOAD_SECURITY) ||
5151 (dev->data->dev_conf.txmode.offloads &
5152 DEV_TX_OFFLOAD_SECURITY)) {
5153 ret = ixgbe_crypto_enable_ipsec(dev);
5156 "ixgbe_crypto_enable_ipsec fails with %d.",
5167 * Start Receive Units for specified queue.
5169 int __attribute__((cold))
5170 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
5172 struct ixgbe_hw *hw;
5173 struct ixgbe_rx_queue *rxq;
5177 PMD_INIT_FUNC_TRACE();
5178 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5180 rxq = dev->data->rx_queues[rx_queue_id];
5182 /* Allocate buffers for descriptor rings */
5183 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
5184 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
5188 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5189 rxdctl |= IXGBE_RXDCTL_ENABLE;
5190 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
5192 /* Wait until RX Enable ready */
5193 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5196 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5197 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
5199 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", rx_queue_id);
5201 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
5202 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
5203 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
5209 * Stop Receive Units for specified queue.
5211 int __attribute__((cold))
5212 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
5214 struct ixgbe_hw *hw;
5215 struct ixgbe_adapter *adapter =
5216 (struct ixgbe_adapter *)dev->data->dev_private;
5217 struct ixgbe_rx_queue *rxq;
5221 PMD_INIT_FUNC_TRACE();
5222 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5224 rxq = dev->data->rx_queues[rx_queue_id];
5226 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5227 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
5228 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
5230 /* Wait until RX Enable bit clear */
5231 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5234 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5235 } while (--poll_ms && (rxdctl & IXGBE_RXDCTL_ENABLE));
5237 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d", rx_queue_id);
5239 rte_delay_us(RTE_IXGBE_WAIT_100_US);
5241 ixgbe_rx_queue_release_mbufs(rxq);
5242 ixgbe_reset_rx_queue(adapter, rxq);
5243 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
5250 * Start Transmit Units for specified queue.
5252 int __attribute__((cold))
5253 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
5255 struct ixgbe_hw *hw;
5256 struct ixgbe_tx_queue *txq;
5260 PMD_INIT_FUNC_TRACE();
5261 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5263 txq = dev->data->tx_queues[tx_queue_id];
5264 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
5265 txdctl |= IXGBE_TXDCTL_ENABLE;
5266 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
5268 /* Wait until TX Enable ready */
5269 if (hw->mac.type == ixgbe_mac_82599EB) {
5270 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5273 txdctl = IXGBE_READ_REG(hw,
5274 IXGBE_TXDCTL(txq->reg_idx));
5275 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
5277 PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d",
5281 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
5282 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
5283 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
5289 * Stop Transmit Units for specified queue.
5291 int __attribute__((cold))
5292 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
5294 struct ixgbe_hw *hw;
5295 struct ixgbe_tx_queue *txq;
5297 uint32_t txtdh, txtdt;
5300 PMD_INIT_FUNC_TRACE();
5301 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5303 txq = dev->data->tx_queues[tx_queue_id];
5305 /* Wait until TX queue is empty */
5306 if (hw->mac.type == ixgbe_mac_82599EB) {
5307 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5309 rte_delay_us(RTE_IXGBE_WAIT_100_US);
5310 txtdh = IXGBE_READ_REG(hw,
5311 IXGBE_TDH(txq->reg_idx));
5312 txtdt = IXGBE_READ_REG(hw,
5313 IXGBE_TDT(txq->reg_idx));
5314 } while (--poll_ms && (txtdh != txtdt));
5317 "Tx Queue %d is not empty when stopping.",
5321 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
5322 txdctl &= ~IXGBE_TXDCTL_ENABLE;
5323 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
5325 /* Wait until TX Enable bit clear */
5326 if (hw->mac.type == ixgbe_mac_82599EB) {
5327 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5330 txdctl = IXGBE_READ_REG(hw,
5331 IXGBE_TXDCTL(txq->reg_idx));
5332 } while (--poll_ms && (txdctl & IXGBE_TXDCTL_ENABLE));
5334 PMD_INIT_LOG(ERR, "Could not disable Tx Queue %d",
5338 if (txq->ops != NULL) {
5339 txq->ops->release_mbufs(txq);
5340 txq->ops->reset(txq);
5342 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
5348 ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
5349 struct rte_eth_rxq_info *qinfo)
5351 struct ixgbe_rx_queue *rxq;
5353 rxq = dev->data->rx_queues[queue_id];
5355 qinfo->mp = rxq->mb_pool;
5356 qinfo->scattered_rx = dev->data->scattered_rx;
5357 qinfo->nb_desc = rxq->nb_rx_desc;
5359 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
5360 qinfo->conf.rx_drop_en = rxq->drop_en;
5361 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
5362 qinfo->conf.offloads = rxq->offloads;
5366 ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
5367 struct rte_eth_txq_info *qinfo)
5369 struct ixgbe_tx_queue *txq;
5371 txq = dev->data->tx_queues[queue_id];
5373 qinfo->nb_desc = txq->nb_tx_desc;
5375 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
5376 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
5377 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
5379 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
5380 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
5381 qinfo->conf.offloads = txq->offloads;
5382 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
5386 * [VF] Initializes Receive Unit.
5388 int __attribute__((cold))
5389 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
5391 struct ixgbe_hw *hw;
5392 struct ixgbe_rx_queue *rxq;
5393 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
5395 uint32_t srrctl, psrtype = 0;
5400 PMD_INIT_FUNC_TRACE();
5401 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5403 if (rte_is_power_of_2(dev->data->nb_rx_queues) == 0) {
5404 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
5405 "it should be power of 2");
5409 if (dev->data->nb_rx_queues > hw->mac.max_rx_queues) {
5410 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
5411 "it should be equal to or less than %d",
5412 hw->mac.max_rx_queues);
5417 * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
5418 * disables the VF receipt of packets if the PF MTU is > 1500.
5419 * This is done to deal with 82599 limitations that imposes
5420 * the PF and all VFs to share the same MTU.
5421 * Then, the PF driver enables again the VF receipt of packet when
5422 * the VF driver issues a IXGBE_VF_SET_LPE request.
5423 * In the meantime, the VF device cannot be used, even if the VF driver
5424 * and the Guest VM network stack are ready to accept packets with a
5425 * size up to the PF MTU.
5426 * As a work-around to this PF behaviour, force the call to
5427 * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
5428 * VF packets received can work in all cases.
5430 ixgbevf_rlpml_set_vf(hw,
5431 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
5434 * Assume no header split and no VLAN strip support
5435 * on any Rx queue first .
5437 rxmode->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
5438 /* Setup RX queues */
5439 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5440 rxq = dev->data->rx_queues[i];
5442 /* Allocate buffers for descriptor rings */
5443 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
5447 /* Setup the Base and Length of the Rx Descriptor Rings */
5448 bus_addr = rxq->rx_ring_phys_addr;
5450 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
5451 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
5452 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
5453 (uint32_t)(bus_addr >> 32));
5454 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
5455 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
5456 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
5457 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
5460 /* Configure the SRRCTL register */
5461 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
5463 /* Set if packets are dropped when no descriptors available */
5465 srrctl |= IXGBE_SRRCTL_DROP_EN;
5468 * Configure the RX buffer size in the BSIZEPACKET field of
5469 * the SRRCTL register of the queue.
5470 * The value is in 1 KB resolution. Valid values can be from
5473 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
5474 RTE_PKTMBUF_HEADROOM);
5475 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
5476 IXGBE_SRRCTL_BSIZEPKT_MASK);
5479 * VF modification to write virtual function SRRCTL register
5481 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
5483 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
5484 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
5486 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER ||
5487 /* It adds dual VLAN length for supporting dual VLAN */
5488 (rxmode->max_rx_pkt_len +
5489 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
5490 if (!dev->data->scattered_rx)
5491 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
5492 dev->data->scattered_rx = 1;
5495 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
5496 rxmode->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
5499 /* Set RQPL for VF RSS according to max Rx queue */
5500 psrtype |= (dev->data->nb_rx_queues >> 1) <<
5501 IXGBE_PSRTYPE_RQPL_SHIFT;
5502 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
5504 ixgbe_set_rx_function(dev);
5510 * [VF] Initializes Transmit Unit.
5512 void __attribute__((cold))
5513 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
5515 struct ixgbe_hw *hw;
5516 struct ixgbe_tx_queue *txq;
5521 PMD_INIT_FUNC_TRACE();
5522 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5524 /* Setup the Base and Length of the Tx Descriptor Rings */
5525 for (i = 0; i < dev->data->nb_tx_queues; i++) {
5526 txq = dev->data->tx_queues[i];
5527 bus_addr = txq->tx_ring_phys_addr;
5528 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
5529 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
5530 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
5531 (uint32_t)(bus_addr >> 32));
5532 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
5533 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
5534 /* Setup the HW Tx Head and TX Tail descriptor pointers */
5535 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
5536 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
5539 * Disable Tx Head Writeback RO bit, since this hoses
5540 * bookkeeping if things aren't delivered in order.
5542 txctrl = IXGBE_READ_REG(hw,
5543 IXGBE_VFDCA_TXCTRL(i));
5544 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
5545 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
5551 * [VF] Start Transmit and Receive Units.
5553 void __attribute__((cold))
5554 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
5556 struct ixgbe_hw *hw;
5557 struct ixgbe_tx_queue *txq;
5558 struct ixgbe_rx_queue *rxq;
5564 PMD_INIT_FUNC_TRACE();
5565 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5567 for (i = 0; i < dev->data->nb_tx_queues; i++) {
5568 txq = dev->data->tx_queues[i];
5569 /* Setup Transmit Threshold Registers */
5570 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5571 txdctl |= txq->pthresh & 0x7F;
5572 txdctl |= ((txq->hthresh & 0x7F) << 8);
5573 txdctl |= ((txq->wthresh & 0x7F) << 16);
5574 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
5577 for (i = 0; i < dev->data->nb_tx_queues; i++) {
5579 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5580 txdctl |= IXGBE_TXDCTL_ENABLE;
5581 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
5584 /* Wait until TX Enable ready */
5587 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5588 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
5590 PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
5592 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5594 rxq = dev->data->rx_queues[i];
5596 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
5597 rxdctl |= IXGBE_RXDCTL_ENABLE;
5598 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
5600 /* Wait until RX Enable ready */
5604 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
5605 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
5607 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
5609 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);
5615 ixgbe_rss_conf_init(struct ixgbe_rte_flow_rss_conf *out,
5616 const struct rte_flow_action_rss *in)
5618 if (in->key_len > RTE_DIM(out->key) ||
5619 in->queue_num > RTE_DIM(out->queue))
5621 out->conf = (struct rte_flow_action_rss){
5625 .key_len = in->key_len,
5626 .queue_num = in->queue_num,
5627 .key = memcpy(out->key, in->key, in->key_len),
5628 .queue = memcpy(out->queue, in->queue,
5629 sizeof(*in->queue) * in->queue_num),
5635 ixgbe_action_rss_same(const struct rte_flow_action_rss *comp,
5636 const struct rte_flow_action_rss *with)
5638 return (comp->func == with->func &&
5639 comp->level == with->level &&
5640 comp->types == with->types &&
5641 comp->key_len == with->key_len &&
5642 comp->queue_num == with->queue_num &&
5643 !memcmp(comp->key, with->key, with->key_len) &&
5644 !memcmp(comp->queue, with->queue,
5645 sizeof(*with->queue) * with->queue_num));
5649 ixgbe_config_rss_filter(struct rte_eth_dev *dev,
5650 struct ixgbe_rte_flow_rss_conf *conf, bool add)
5652 struct ixgbe_hw *hw;
5656 uint16_t sp_reta_size;
5658 struct rte_eth_rss_conf rss_conf = {
5659 .rss_key = conf->conf.key_len ?
5660 (void *)(uintptr_t)conf->conf.key : NULL,
5661 .rss_key_len = conf->conf.key_len,
5662 .rss_hf = conf->conf.types,
5664 struct ixgbe_filter_info *filter_info =
5665 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5667 PMD_INIT_FUNC_TRACE();
5668 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5670 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5673 if (ixgbe_action_rss_same(&filter_info->rss_info.conf,
5675 ixgbe_rss_disable(dev);
5676 memset(&filter_info->rss_info, 0,
5677 sizeof(struct ixgbe_rte_flow_rss_conf));
5683 if (filter_info->rss_info.conf.queue_num)
5685 /* Fill in redirection table
5686 * The byte-swap is needed because NIC registers are in
5687 * little-endian order.
5690 for (i = 0, j = 0; i < sp_reta_size; i++, j++) {
5691 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5693 if (j == conf->conf.queue_num)
5695 reta = (reta << 8) | conf->conf.queue[j];
5697 IXGBE_WRITE_REG(hw, reta_reg,
5701 /* Configure the RSS key and the RSS protocols used to compute
5702 * the RSS hash of input packets.
5704 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
5705 ixgbe_rss_disable(dev);
5708 if (rss_conf.rss_key == NULL)
5709 rss_conf.rss_key = rss_intel_key; /* Default hash key */
5710 ixgbe_hw_rss_hash_set(hw, &rss_conf);
5712 if (ixgbe_rss_conf_init(&filter_info->rss_info, &conf->conf))
5718 /* Stubs needed for linkage when CONFIG_RTE_IXGBE_INC_VECTOR is set to 'n' */
5719 int __attribute__((weak))
5720 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
5725 uint16_t __attribute__((weak))
5726 ixgbe_recv_pkts_vec(
5727 void __rte_unused *rx_queue,
5728 struct rte_mbuf __rte_unused **rx_pkts,
5729 uint16_t __rte_unused nb_pkts)
5734 uint16_t __attribute__((weak))
5735 ixgbe_recv_scattered_pkts_vec(
5736 void __rte_unused *rx_queue,
5737 struct rte_mbuf __rte_unused **rx_pkts,
5738 uint16_t __rte_unused nb_pkts)
5743 int __attribute__((weak))
5744 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue __rte_unused *rxq)