4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5 * Copyright 2014 6WIND S.A.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
18 * * Neither the name of Intel Corporation nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/queue.h>
46 #include <rte_byteorder.h>
47 #include <rte_common.h>
48 #include <rte_cycles.h>
50 #include <rte_debug.h>
51 #include <rte_interrupts.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_launch.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
75 #include "ixgbe_logs.h"
76 #include "base/ixgbe_api.h"
77 #include "base/ixgbe_vf.h"
78 #include "ixgbe_ethdev.h"
79 #include "base/ixgbe_dcb.h"
80 #include "base/ixgbe_common.h"
81 #include "ixgbe_rxtx.h"
83 /* Bit Mask to indicate what bits required for building TX context */
84 #define IXGBE_TX_OFFLOAD_MASK ( \
90 static inline struct rte_mbuf *
91 rte_rxmbuf_alloc(struct rte_mempool *mp)
95 m = __rte_mbuf_raw_alloc(mp);
96 __rte_mbuf_sanity_check_raw(m, 0);
102 #define RTE_PMD_USE_PREFETCH
105 #ifdef RTE_PMD_USE_PREFETCH
107 * Prefetch a cache line into all cache levels.
109 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
111 #define rte_ixgbe_prefetch(p) do {} while(0)
114 /*********************************************************************
118 **********************************************************************/
121 * Check for descriptors with their DD bit set and free mbufs.
122 * Return the total number of buffers freed.
124 static inline int __attribute__((always_inline))
125 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
127 struct ixgbe_tx_entry *txep;
131 /* check DD bit on threshold descriptor */
132 status = txq->tx_ring[txq->tx_next_dd].wb.status;
133 if (! (status & IXGBE_ADVTXD_STAT_DD))
137 * first buffer to free from S/W ring is at index
138 * tx_next_dd - (tx_rs_thresh-1)
140 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
142 /* free buffers one at a time */
143 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
144 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
145 txep->mbuf->next = NULL;
146 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
150 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
151 rte_pktmbuf_free_seg(txep->mbuf);
156 /* buffers were freed, update counters */
157 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
158 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
159 if (txq->tx_next_dd >= txq->nb_tx_desc)
160 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
162 return txq->tx_rs_thresh;
165 /* Populate 4 descriptors with data from 4 mbufs */
167 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
169 uint64_t buf_dma_addr;
173 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
174 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
175 pkt_len = (*pkts)->data_len;
177 /* write data to descriptor */
178 txdp->read.buffer_addr = buf_dma_addr;
179 txdp->read.cmd_type_len =
180 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
181 txdp->read.olinfo_status =
182 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
183 rte_prefetch0(&(*pkts)->pool);
187 /* Populate 1 descriptor with data from 1 mbuf */
189 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
191 uint64_t buf_dma_addr;
194 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
195 pkt_len = (*pkts)->data_len;
197 /* write data to descriptor */
198 txdp->read.buffer_addr = buf_dma_addr;
199 txdp->read.cmd_type_len =
200 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
201 txdp->read.olinfo_status =
202 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
203 rte_prefetch0(&(*pkts)->pool);
207 * Fill H/W descriptor ring with mbuf data.
208 * Copy mbuf pointers to the S/W ring.
211 ixgbe_tx_fill_hw_ring(struct ixgbe_tx_queue *txq, struct rte_mbuf **pkts,
214 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
215 struct ixgbe_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
216 const int N_PER_LOOP = 4;
217 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
218 int mainpart, leftover;
222 * Process most of the packets in chunks of N pkts. Any
223 * leftover packets will get processed one at a time.
225 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
226 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
227 for (i = 0; i < mainpart; i += N_PER_LOOP) {
228 /* Copy N mbuf pointers to the S/W ring */
229 for (j = 0; j < N_PER_LOOP; ++j) {
230 (txep + i + j)->mbuf = *(pkts + i + j);
232 tx4(txdp + i, pkts + i);
235 if (unlikely(leftover > 0)) {
236 for (i = 0; i < leftover; ++i) {
237 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
238 tx1(txdp + mainpart + i, pkts + mainpart + i);
243 static inline uint16_t
244 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
247 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
248 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
252 * Begin scanning the H/W ring for done descriptors when the
253 * number of available descriptors drops below tx_free_thresh. For
254 * each done descriptor, free the associated buffer.
256 if (txq->nb_tx_free < txq->tx_free_thresh)
257 ixgbe_tx_free_bufs(txq);
259 /* Only use descriptors that are available */
260 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
261 if (unlikely(nb_pkts == 0))
264 /* Use exactly nb_pkts descriptors */
265 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
268 * At this point, we know there are enough descriptors in the
269 * ring to transmit all the packets. This assumes that each
270 * mbuf contains a single segment, and that no new offloads
271 * are expected, which would require a new context descriptor.
275 * See if we're going to wrap-around. If so, handle the top
276 * of the descriptor ring first, then do the bottom. If not,
277 * the processing looks just like the "bottom" part anyway...
279 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
280 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
281 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
284 * We know that the last descriptor in the ring will need to
285 * have its RS bit set because tx_rs_thresh has to be
286 * a divisor of the ring size
288 tx_r[txq->tx_next_rs].read.cmd_type_len |=
289 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
290 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
295 /* Fill H/W descriptor ring with mbuf data */
296 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
297 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
300 * Determine if RS bit should be set
301 * This is what we actually want:
302 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
303 * but instead of subtracting 1 and doing >=, we can just do
304 * greater than without subtracting.
306 if (txq->tx_tail > txq->tx_next_rs) {
307 tx_r[txq->tx_next_rs].read.cmd_type_len |=
308 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
309 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
311 if (txq->tx_next_rs >= txq->nb_tx_desc)
312 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
316 * Check for wrap-around. This would only happen if we used
317 * up to the last descriptor in the ring, no more, no less.
319 if (txq->tx_tail >= txq->nb_tx_desc)
322 /* update tail pointer */
324 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
330 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
335 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
336 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
337 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
339 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
343 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
344 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
345 nb_tx = (uint16_t)(nb_tx + ret);
346 nb_pkts = (uint16_t)(nb_pkts - ret);
355 ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,
356 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
357 uint64_t ol_flags, union ixgbe_tx_offload tx_offload)
359 uint32_t type_tucmd_mlhl;
360 uint32_t mss_l4len_idx = 0;
362 uint32_t vlan_macip_lens;
363 union ixgbe_tx_offload tx_offload_mask;
365 ctx_idx = txq->ctx_curr;
366 tx_offload_mask.data = 0;
369 /* Specify which HW CTX to upload. */
370 mss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
372 if (ol_flags & PKT_TX_VLAN_PKT) {
373 tx_offload_mask.vlan_tci |= ~0;
376 /* check if TCP segmentation required for this packet */
377 if (ol_flags & PKT_TX_TCP_SEG) {
378 /* implies IP cksum in IPv4 */
379 if (ol_flags & PKT_TX_IP_CKSUM)
380 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |
381 IXGBE_ADVTXD_TUCMD_L4T_TCP |
382 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
384 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV6 |
385 IXGBE_ADVTXD_TUCMD_L4T_TCP |
386 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
388 tx_offload_mask.l2_len |= ~0;
389 tx_offload_mask.l3_len |= ~0;
390 tx_offload_mask.l4_len |= ~0;
391 tx_offload_mask.tso_segsz |= ~0;
392 mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
393 mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;
394 } else { /* no TSO, check if hardware checksum is needed */
395 if (ol_flags & PKT_TX_IP_CKSUM) {
396 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
397 tx_offload_mask.l2_len |= ~0;
398 tx_offload_mask.l3_len |= ~0;
401 switch (ol_flags & PKT_TX_L4_MASK) {
402 case PKT_TX_UDP_CKSUM:
403 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
404 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
405 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
406 tx_offload_mask.l2_len |= ~0;
407 tx_offload_mask.l3_len |= ~0;
409 case PKT_TX_TCP_CKSUM:
410 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
411 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
412 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
413 tx_offload_mask.l2_len |= ~0;
414 tx_offload_mask.l3_len |= ~0;
415 tx_offload_mask.l4_len |= ~0;
417 case PKT_TX_SCTP_CKSUM:
418 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
419 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
420 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
421 tx_offload_mask.l2_len |= ~0;
422 tx_offload_mask.l3_len |= ~0;
425 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
426 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
431 txq->ctx_cache[ctx_idx].flags = ol_flags;
432 txq->ctx_cache[ctx_idx].tx_offload.data =
433 tx_offload_mask.data & tx_offload.data;
434 txq->ctx_cache[ctx_idx].tx_offload_mask = tx_offload_mask;
436 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
437 vlan_macip_lens = tx_offload.l3_len;
438 vlan_macip_lens |= (tx_offload.l2_len << IXGBE_ADVTXD_MACLEN_SHIFT);
439 vlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);
440 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
441 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
442 ctx_txd->seqnum_seed = 0;
446 * Check which hardware context can be used. Use the existing match
447 * or create a new context descriptor.
449 static inline uint32_t
450 what_advctx_update(struct ixgbe_tx_queue *txq, uint64_t flags,
451 union ixgbe_tx_offload tx_offload)
453 /* If match with the current used context */
454 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
455 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
456 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
457 return txq->ctx_curr;
460 /* What if match with the next context */
462 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
463 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
464 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
465 return txq->ctx_curr;
468 /* Mismatch, use the previous context */
469 return (IXGBE_CTX_NUM);
472 static inline uint32_t
473 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
476 if ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM)
477 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
478 if (ol_flags & PKT_TX_IP_CKSUM)
479 tmp |= IXGBE_ADVTXD_POPTS_IXSM;
480 if (ol_flags & PKT_TX_TCP_SEG)
481 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
485 static inline uint32_t
486 tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)
488 uint32_t cmdtype = 0;
489 if (ol_flags & PKT_TX_VLAN_PKT)
490 cmdtype |= IXGBE_ADVTXD_DCMD_VLE;
491 if (ol_flags & PKT_TX_TCP_SEG)
492 cmdtype |= IXGBE_ADVTXD_DCMD_TSE;
496 /* Default RS bit threshold values */
497 #ifndef DEFAULT_TX_RS_THRESH
498 #define DEFAULT_TX_RS_THRESH 32
500 #ifndef DEFAULT_TX_FREE_THRESH
501 #define DEFAULT_TX_FREE_THRESH 32
504 /* Reset transmit descriptors after they have been used */
506 ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)
508 struct ixgbe_tx_entry *sw_ring = txq->sw_ring;
509 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
510 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
511 uint16_t nb_tx_desc = txq->nb_tx_desc;
512 uint16_t desc_to_clean_to;
513 uint16_t nb_tx_to_clean;
515 /* Determine the last descriptor needing to be cleaned */
516 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
517 if (desc_to_clean_to >= nb_tx_desc)
518 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
520 /* Check to make sure the last descriptor to clean is done */
521 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
522 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
524 PMD_TX_FREE_LOG(DEBUG,
525 "TX descriptor %4u is not done"
526 "(port=%d queue=%d)",
528 txq->port_id, txq->queue_id);
529 /* Failed to clean any descriptors, better luck next time */
533 /* Figure out how many descriptors will be cleaned */
534 if (last_desc_cleaned > desc_to_clean_to)
535 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
538 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
541 PMD_TX_FREE_LOG(DEBUG,
542 "Cleaning %4u TX descriptors: %4u to %4u "
543 "(port=%d queue=%d)",
544 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
545 txq->port_id, txq->queue_id);
548 * The last descriptor to clean is done, so that means all the
549 * descriptors from the last descriptor that was cleaned
550 * up to the last descriptor with the RS bit set
551 * are done. Only reset the threshold descriptor.
553 txr[desc_to_clean_to].wb.status = 0;
555 /* Update the txq to reflect the last descriptor that was cleaned */
556 txq->last_desc_cleaned = desc_to_clean_to;
557 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
564 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
567 struct ixgbe_tx_queue *txq;
568 struct ixgbe_tx_entry *sw_ring;
569 struct ixgbe_tx_entry *txe, *txn;
570 volatile union ixgbe_adv_tx_desc *txr;
571 volatile union ixgbe_adv_tx_desc *txd;
572 struct rte_mbuf *tx_pkt;
573 struct rte_mbuf *m_seg;
574 uint64_t buf_dma_addr;
575 uint32_t olinfo_status;
576 uint32_t cmd_type_len;
587 union ixgbe_tx_offload tx_offload = {0};
590 sw_ring = txq->sw_ring;
592 tx_id = txq->tx_tail;
593 txe = &sw_ring[tx_id];
595 /* Determine if the descriptor ring needs to be cleaned. */
596 if (txq->nb_tx_free < txq->tx_free_thresh)
597 ixgbe_xmit_cleanup(txq);
599 rte_prefetch0(&txe->mbuf->pool);
602 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
605 pkt_len = tx_pkt->pkt_len;
608 * Determine how many (if any) context descriptors
609 * are needed for offload functionality.
611 ol_flags = tx_pkt->ol_flags;
613 /* If hardware offload required */
614 tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
616 tx_offload.l2_len = tx_pkt->l2_len;
617 tx_offload.l3_len = tx_pkt->l3_len;
618 tx_offload.l4_len = tx_pkt->l4_len;
619 tx_offload.vlan_tci = tx_pkt->vlan_tci;
620 tx_offload.tso_segsz = tx_pkt->tso_segsz;
622 /* If new context need be built or reuse the exist ctx. */
623 ctx = what_advctx_update(txq, tx_ol_req,
625 /* Only allocate context descriptor if required*/
626 new_ctx = (ctx == IXGBE_CTX_NUM);
631 * Keep track of how many descriptors are used this loop
632 * This will always be the number of segments + the number of
633 * Context descriptors required to transmit the packet
635 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
638 * The number of descriptors that must be allocated for a
639 * packet is the number of segments of that packet, plus 1
640 * Context Descriptor for the hardware offload, if any.
641 * Determine the last TX descriptor to allocate in the TX ring
642 * for the packet, starting from the current position (tx_id)
645 tx_last = (uint16_t) (tx_id + nb_used - 1);
648 if (tx_last >= txq->nb_tx_desc)
649 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
651 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
652 " tx_first=%u tx_last=%u",
653 (unsigned) txq->port_id,
654 (unsigned) txq->queue_id,
660 * Make sure there are enough TX descriptors available to
661 * transmit the entire packet.
662 * nb_used better be less than or equal to txq->tx_rs_thresh
664 if (nb_used > txq->nb_tx_free) {
665 PMD_TX_FREE_LOG(DEBUG,
666 "Not enough free TX descriptors "
667 "nb_used=%4u nb_free=%4u "
668 "(port=%d queue=%d)",
669 nb_used, txq->nb_tx_free,
670 txq->port_id, txq->queue_id);
672 if (ixgbe_xmit_cleanup(txq) != 0) {
673 /* Could not clean any descriptors */
679 /* nb_used better be <= txq->tx_rs_thresh */
680 if (unlikely(nb_used > txq->tx_rs_thresh)) {
681 PMD_TX_FREE_LOG(DEBUG,
682 "The number of descriptors needed to "
683 "transmit the packet exceeds the "
684 "RS bit threshold. This will impact "
686 "nb_used=%4u nb_free=%4u "
688 "(port=%d queue=%d)",
689 nb_used, txq->nb_tx_free,
691 txq->port_id, txq->queue_id);
693 * Loop here until there are enough TX
694 * descriptors or until the ring cannot be
697 while (nb_used > txq->nb_tx_free) {
698 if (ixgbe_xmit_cleanup(txq) != 0) {
700 * Could not clean any
712 * By now there are enough free TX descriptors to transmit
717 * Set common flags of all TX Data Descriptors.
719 * The following bits must be set in all Data Descriptors:
720 * - IXGBE_ADVTXD_DTYP_DATA
721 * - IXGBE_ADVTXD_DCMD_DEXT
723 * The following bits must be set in the first Data Descriptor
724 * and are ignored in the other ones:
725 * - IXGBE_ADVTXD_DCMD_IFCS
726 * - IXGBE_ADVTXD_MAC_1588
727 * - IXGBE_ADVTXD_DCMD_VLE
729 * The following bits must only be set in the last Data
731 * - IXGBE_TXD_CMD_EOP
733 * The following bits can be set in any Data Descriptor, but
734 * are only set in the last Data Descriptor:
737 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
738 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
740 #ifdef RTE_LIBRTE_IEEE1588
741 if (ol_flags & PKT_TX_IEEE1588_TMST)
742 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
748 if (ol_flags & PKT_TX_TCP_SEG) {
749 /* when TSO is on, paylen in descriptor is the
750 * not the packet len but the tcp payload len */
751 pkt_len -= (tx_offload.l2_len +
752 tx_offload.l3_len + tx_offload.l4_len);
756 * Setup the TX Advanced Context Descriptor if required
759 volatile struct ixgbe_adv_tx_context_desc *
762 ctx_txd = (volatile struct
763 ixgbe_adv_tx_context_desc *)
766 txn = &sw_ring[txe->next_id];
767 rte_prefetch0(&txn->mbuf->pool);
769 if (txe->mbuf != NULL) {
770 rte_pktmbuf_free_seg(txe->mbuf);
774 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
777 txe->last_id = tx_last;
778 tx_id = txe->next_id;
783 * Setup the TX Advanced Data Descriptor,
784 * This path will go through
785 * whatever new/reuse the context descriptor
787 cmd_type_len |= tx_desc_ol_flags_to_cmdtype(ol_flags);
788 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
789 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
792 olinfo_status |= (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
797 txn = &sw_ring[txe->next_id];
798 rte_prefetch0(&txn->mbuf->pool);
800 if (txe->mbuf != NULL)
801 rte_pktmbuf_free_seg(txe->mbuf);
805 * Set up Transmit Data Descriptor.
807 slen = m_seg->data_len;
808 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
809 txd->read.buffer_addr =
810 rte_cpu_to_le_64(buf_dma_addr);
811 txd->read.cmd_type_len =
812 rte_cpu_to_le_32(cmd_type_len | slen);
813 txd->read.olinfo_status =
814 rte_cpu_to_le_32(olinfo_status);
815 txe->last_id = tx_last;
816 tx_id = txe->next_id;
819 } while (m_seg != NULL);
822 * The last packet data descriptor needs End Of Packet (EOP)
824 cmd_type_len |= IXGBE_TXD_CMD_EOP;
825 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
826 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
828 /* Set RS bit only on threshold packets' last descriptor */
829 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
830 PMD_TX_FREE_LOG(DEBUG,
831 "Setting RS bit on TXD id="
832 "%4u (port=%d queue=%d)",
833 tx_last, txq->port_id, txq->queue_id);
835 cmd_type_len |= IXGBE_TXD_CMD_RS;
837 /* Update txq RS bit counters */
840 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
846 * Set the Transmit Descriptor Tail (TDT)
848 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
849 (unsigned) txq->port_id, (unsigned) txq->queue_id,
850 (unsigned) tx_id, (unsigned) nb_tx);
851 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
852 txq->tx_tail = tx_id;
857 /*********************************************************************
861 **********************************************************************/
863 #define IXGBE_PACKET_TYPE_IPV4 0X01
864 #define IXGBE_PACKET_TYPE_IPV4_TCP 0X11
865 #define IXGBE_PACKET_TYPE_IPV4_UDP 0X21
866 #define IXGBE_PACKET_TYPE_IPV4_SCTP 0X41
867 #define IXGBE_PACKET_TYPE_IPV4_EXT 0X03
868 #define IXGBE_PACKET_TYPE_IPV4_EXT_SCTP 0X43
869 #define IXGBE_PACKET_TYPE_IPV6 0X04
870 #define IXGBE_PACKET_TYPE_IPV6_TCP 0X14
871 #define IXGBE_PACKET_TYPE_IPV6_UDP 0X24
872 #define IXGBE_PACKET_TYPE_IPV6_EXT 0X0C
873 #define IXGBE_PACKET_TYPE_IPV6_EXT_TCP 0X1C
874 #define IXGBE_PACKET_TYPE_IPV6_EXT_UDP 0X2C
875 #define IXGBE_PACKET_TYPE_IPV4_IPV6 0X05
876 #define IXGBE_PACKET_TYPE_IPV4_IPV6_TCP 0X15
877 #define IXGBE_PACKET_TYPE_IPV4_IPV6_UDP 0X25
878 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT 0X0D
879 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP 0X1D
880 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP 0X2D
881 #define IXGBE_PACKET_TYPE_MAX 0X80
882 #define IXGBE_PACKET_TYPE_MASK 0X7F
883 #define IXGBE_PACKET_TYPE_SHIFT 0X04
884 static inline uint32_t
885 ixgbe_rxd_pkt_info_to_pkt_type(uint16_t pkt_info)
887 static const uint32_t
888 ptype_table[IXGBE_PACKET_TYPE_MAX] __rte_cache_aligned = {
889 [IXGBE_PACKET_TYPE_IPV4] = RTE_PTYPE_L2_ETHER |
891 [IXGBE_PACKET_TYPE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
892 RTE_PTYPE_L3_IPV4_EXT,
893 [IXGBE_PACKET_TYPE_IPV6] = RTE_PTYPE_L2_ETHER |
895 [IXGBE_PACKET_TYPE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
896 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
897 RTE_PTYPE_INNER_L3_IPV6,
898 [IXGBE_PACKET_TYPE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
899 RTE_PTYPE_L3_IPV6_EXT,
900 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
901 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
902 RTE_PTYPE_INNER_L3_IPV6_EXT,
903 [IXGBE_PACKET_TYPE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
904 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
905 [IXGBE_PACKET_TYPE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
906 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
907 [IXGBE_PACKET_TYPE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
908 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
909 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
910 [IXGBE_PACKET_TYPE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
911 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,
912 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
913 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
914 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
915 [IXGBE_PACKET_TYPE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
916 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
917 [IXGBE_PACKET_TYPE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
918 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
919 [IXGBE_PACKET_TYPE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
920 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
921 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
922 [IXGBE_PACKET_TYPE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
923 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
924 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
925 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
926 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
927 [IXGBE_PACKET_TYPE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
928 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP,
929 [IXGBE_PACKET_TYPE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
930 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_SCTP,
932 if (unlikely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
933 return RTE_PTYPE_UNKNOWN;
935 pkt_info = (pkt_info >> IXGBE_PACKET_TYPE_SHIFT) &
936 IXGBE_PACKET_TYPE_MASK;
938 return ptype_table[pkt_info];
941 static inline uint64_t
942 ixgbe_rxd_pkt_info_to_pkt_flags(uint16_t pkt_info)
944 static uint64_t ip_rss_types_map[16] __rte_cache_aligned = {
945 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
946 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
947 PKT_RX_RSS_HASH, 0, 0, 0,
948 0, 0, 0, PKT_RX_FDIR,
950 #ifdef RTE_LIBRTE_IEEE1588
951 static uint64_t ip_pkt_etqf_map[8] = {
952 0, 0, 0, PKT_RX_IEEE1588_PTP,
956 if (likely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
957 return ip_pkt_etqf_map[(pkt_info >> 4) & 0X07] |
958 ip_rss_types_map[pkt_info & 0XF];
960 return ip_rss_types_map[pkt_info & 0XF];
962 return ip_rss_types_map[pkt_info & 0XF];
965 #else /* RTE_NEXT_ABI */
966 static inline uint64_t
967 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
971 static const uint64_t ip_pkt_types_map[16] = {
972 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
973 PKT_RX_IPV6_HDR, 0, 0, 0,
974 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
975 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
978 static const uint64_t ip_rss_types_map[16] = {
979 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
980 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
981 PKT_RX_RSS_HASH, 0, 0, 0,
982 0, 0, 0, PKT_RX_FDIR,
985 #ifdef RTE_LIBRTE_IEEE1588
986 static uint64_t ip_pkt_etqf_map[8] = {
987 0, 0, 0, PKT_RX_IEEE1588_PTP,
991 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
992 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
993 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
995 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
996 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
999 return pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF];
1001 #endif /* RTE_NEXT_ABI */
1003 static inline uint64_t
1004 rx_desc_status_to_pkt_flags(uint32_t rx_status)
1009 * Check if VLAN present only.
1010 * Do not check whether L3/L4 rx checksum done by NIC or not,
1011 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
1013 pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;
1015 #ifdef RTE_LIBRTE_IEEE1588
1016 if (rx_status & IXGBE_RXD_STAT_TMST)
1017 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
1022 static inline uint64_t
1023 rx_desc_error_to_pkt_flags(uint32_t rx_status)
1026 * Bit 31: IPE, IPv4 checksum error
1027 * Bit 30: L4I, L4I integrity error
1029 static uint64_t error_to_pkt_flags_map[4] = {
1030 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
1031 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
1033 return error_to_pkt_flags_map[(rx_status >>
1034 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
1037 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1039 * LOOK_AHEAD defines how many desc statuses to check beyond the
1040 * current descriptor.
1041 * It must be a pound define for optimal performance.
1042 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
1043 * function only works with LOOK_AHEAD=8.
1045 #define LOOK_AHEAD 8
1046 #if (LOOK_AHEAD != 8)
1047 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
1050 ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
1052 volatile union ixgbe_adv_rx_desc *rxdp;
1053 struct ixgbe_rx_entry *rxep;
1054 struct rte_mbuf *mb;
1059 uint32_t s[LOOK_AHEAD];
1060 uint16_t pkt_info[LOOK_AHEAD];
1062 int s[LOOK_AHEAD], nb_dd;
1063 #endif /* RTE_NEXT_ABI */
1064 int i, j, nb_rx = 0;
1067 /* get references to current descriptor and S/W ring entry */
1068 rxdp = &rxq->rx_ring[rxq->rx_tail];
1069 rxep = &rxq->sw_ring[rxq->rx_tail];
1071 /* check to make sure there is at least 1 packet to receive */
1072 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
1076 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
1077 * reference packets that are ready to be received.
1079 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
1080 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
1082 /* Read desc statuses backwards to avoid race condition */
1083 for (j = LOOK_AHEAD-1; j >= 0; --j)
1084 s[j] = rxdp[j].wb.upper.status_error;
1087 for (j = LOOK_AHEAD - 1; j >= 0; --j)
1088 pkt_info[j] = rxdp[j].wb.lower.lo_dword.
1090 #endif /* RTE_NEXT_ABI */
1092 /* Compute how many status bits were set */
1094 for (j = 0; j < LOOK_AHEAD; ++j)
1095 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
1099 /* Translate descriptor info to mbuf format */
1100 for (j = 0; j < nb_dd; ++j) {
1102 pkt_len = (uint16_t)(rxdp[j].wb.upper.length - rxq->crc_len);
1103 mb->data_len = pkt_len;
1104 mb->pkt_len = pkt_len;
1105 mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
1107 /* convert descriptor fields to rte mbuf flags */
1109 pkt_flags = rx_desc_status_to_pkt_flags(s[j]);
1110 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
1112 ixgbe_rxd_pkt_info_to_pkt_flags(pkt_info[j]);
1113 mb->ol_flags = pkt_flags;
1115 ixgbe_rxd_pkt_info_to_pkt_type(pkt_info[j]);
1116 #else /* RTE_NEXT_ABI */
1117 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(
1118 rxdp[j].wb.lower.lo_dword.data);
1119 /* reuse status field from scan list */
1120 pkt_flags |= rx_desc_status_to_pkt_flags(s[j]);
1121 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
1122 mb->ol_flags = pkt_flags;
1123 #endif /* RTE_NEXT_ABI */
1125 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1126 mb->hash.rss = rxdp[j].wb.lower.hi_dword.rss;
1127 else if (pkt_flags & PKT_RX_FDIR) {
1128 mb->hash.fdir.hash =
1129 (uint16_t)((rxdp[j].wb.lower.hi_dword.csum_ip.csum)
1130 & IXGBE_ATR_HASH_MASK);
1131 mb->hash.fdir.id = rxdp[j].wb.lower.hi_dword.csum_ip.ip_id;
1135 /* Move mbuf pointers from the S/W ring to the stage */
1136 for (j = 0; j < LOOK_AHEAD; ++j) {
1137 rxq->rx_stage[i + j] = rxep[j].mbuf;
1140 /* stop if all requested packets could not be received */
1141 if (nb_dd != LOOK_AHEAD)
1145 /* clear software ring entries so we can cleanup correctly */
1146 for (i = 0; i < nb_rx; ++i) {
1147 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1155 ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq, bool reset_mbuf)
1157 volatile union ixgbe_adv_rx_desc *rxdp;
1158 struct ixgbe_rx_entry *rxep;
1159 struct rte_mbuf *mb;
1164 /* allocate buffers in bulk directly into the S/W ring */
1165 alloc_idx = rxq->rx_free_trigger - (rxq->rx_free_thresh - 1);
1166 rxep = &rxq->sw_ring[alloc_idx];
1167 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1168 rxq->rx_free_thresh);
1169 if (unlikely(diag != 0))
1172 rxdp = &rxq->rx_ring[alloc_idx];
1173 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1174 /* populate the static rte mbuf fields */
1179 mb->port = rxq->port_id;
1182 rte_mbuf_refcnt_set(mb, 1);
1183 mb->data_off = RTE_PKTMBUF_HEADROOM;
1185 /* populate the descriptors */
1186 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
1187 rxdp[i].read.hdr_addr = dma_addr;
1188 rxdp[i].read.pkt_addr = dma_addr;
1191 /* update state of internal queue structure */
1192 rxq->rx_free_trigger = rxq->rx_free_trigger + rxq->rx_free_thresh;
1193 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1194 rxq->rx_free_trigger = rxq->rx_free_thresh - 1;
1200 static inline uint16_t
1201 ixgbe_rx_fill_from_stage(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1204 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1207 /* how many packets are ready to return? */
1208 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1210 /* copy mbuf pointers to the application's packet list */
1211 for (i = 0; i < nb_pkts; ++i)
1212 rx_pkts[i] = stage[i];
1214 /* update internal queue state */
1215 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1216 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1221 static inline uint16_t
1222 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1225 struct ixgbe_rx_queue *rxq = (struct ixgbe_rx_queue *)rx_queue;
1228 /* Any previously recv'd pkts will be returned from the Rx stage */
1229 if (rxq->rx_nb_avail)
1230 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1232 /* Scan the H/W ring for packets to receive */
1233 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1235 /* update internal queue state */
1236 rxq->rx_next_avail = 0;
1237 rxq->rx_nb_avail = nb_rx;
1238 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1240 /* if required, allocate new buffers to replenish descriptors */
1241 if (rxq->rx_tail > rxq->rx_free_trigger) {
1242 uint16_t cur_free_trigger = rxq->rx_free_trigger;
1244 if (ixgbe_rx_alloc_bufs(rxq, true) != 0) {
1246 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1247 "queue_id=%u", (unsigned) rxq->port_id,
1248 (unsigned) rxq->queue_id);
1250 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1251 rxq->rx_free_thresh;
1254 * Need to rewind any previous receives if we cannot
1255 * allocate new buffers to replenish the old ones.
1257 rxq->rx_nb_avail = 0;
1258 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1259 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1260 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1265 /* update tail pointer */
1267 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, cur_free_trigger);
1270 if (rxq->rx_tail >= rxq->nb_rx_desc)
1273 /* received any packets this loop? */
1274 if (rxq->rx_nb_avail)
1275 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1280 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1282 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1287 if (unlikely(nb_pkts == 0))
1290 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1291 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1293 /* request is relatively large, chunk it up */
1297 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1298 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1299 nb_rx = (uint16_t)(nb_rx + ret);
1300 nb_pkts = (uint16_t)(nb_pkts - ret);
1310 /* Stub to avoid extra ifdefs */
1312 ixgbe_recv_pkts_bulk_alloc(__rte_unused void *rx_queue,
1313 __rte_unused struct rte_mbuf **rx_pkts, __rte_unused uint16_t nb_pkts)
1319 ixgbe_rx_alloc_bufs(__rte_unused struct ixgbe_rx_queue *rxq,
1320 __rte_unused bool reset_mbuf)
1324 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1327 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1330 struct ixgbe_rx_queue *rxq;
1331 volatile union ixgbe_adv_rx_desc *rx_ring;
1332 volatile union ixgbe_adv_rx_desc *rxdp;
1333 struct ixgbe_rx_entry *sw_ring;
1334 struct ixgbe_rx_entry *rxe;
1335 struct rte_mbuf *rxm;
1336 struct rte_mbuf *nmb;
1337 union ixgbe_adv_rx_desc rxd;
1343 uint32_t hlen_type_rss;
1354 rx_id = rxq->rx_tail;
1355 rx_ring = rxq->rx_ring;
1356 sw_ring = rxq->sw_ring;
1357 while (nb_rx < nb_pkts) {
1359 * The order of operations here is important as the DD status
1360 * bit must not be read after any other descriptor fields.
1361 * rx_ring and rxdp are pointing to volatile data so the order
1362 * of accesses cannot be reordered by the compiler. If they were
1363 * not volatile, they could be reordered which could lead to
1364 * using invalid descriptor fields when read from rxd.
1366 rxdp = &rx_ring[rx_id];
1367 staterr = rxdp->wb.upper.status_error;
1368 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1375 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1376 * is likely to be invalid and to be dropped by the various
1377 * validation checks performed by the network stack.
1379 * Allocate a new mbuf to replenish the RX ring descriptor.
1380 * If the allocation fails:
1381 * - arrange for that RX descriptor to be the first one
1382 * being parsed the next time the receive function is
1383 * invoked [on the same queue].
1385 * - Stop parsing the RX ring and return immediately.
1387 * This policy do not drop the packet received in the RX
1388 * descriptor for which the allocation of a new mbuf failed.
1389 * Thus, it allows that packet to be later retrieved if
1390 * mbuf have been freed in the mean time.
1391 * As a side effect, holding RX descriptors instead of
1392 * systematically giving them back to the NIC may lead to
1393 * RX ring exhaustion situations.
1394 * However, the NIC can gracefully prevent such situations
1395 * to happen by sending specific "back-pressure" flow control
1396 * frames to its peer(s).
1398 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1399 "ext_err_stat=0x%08x pkt_len=%u",
1400 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1401 (unsigned) rx_id, (unsigned) staterr,
1402 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1404 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1406 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1407 "queue_id=%u", (unsigned) rxq->port_id,
1408 (unsigned) rxq->queue_id);
1409 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1414 rxe = &sw_ring[rx_id];
1416 if (rx_id == rxq->nb_rx_desc)
1419 /* Prefetch next mbuf while processing current one. */
1420 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1423 * When next RX descriptor is on a cache-line boundary,
1424 * prefetch the next 4 RX descriptors and the next 8 pointers
1427 if ((rx_id & 0x3) == 0) {
1428 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1429 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1435 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1436 rxdp->read.hdr_addr = dma_addr;
1437 rxdp->read.pkt_addr = dma_addr;
1440 * Initialize the returned mbuf.
1441 * 1) setup generic mbuf fields:
1442 * - number of segments,
1445 * - RX port identifier.
1446 * 2) integrate hardware offload data, if any:
1447 * - RSS flag & hash,
1448 * - IP checksum flag,
1449 * - VLAN TCI, if any,
1452 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1454 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1455 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1458 rxm->pkt_len = pkt_len;
1459 rxm->data_len = pkt_len;
1460 rxm->port = rxq->port_id;
1463 pkt_info = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.hs_rss.
1465 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1466 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1468 pkt_flags = rx_desc_status_to_pkt_flags(staterr);
1469 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1470 pkt_flags = pkt_flags |
1471 ixgbe_rxd_pkt_info_to_pkt_flags(pkt_info);
1472 rxm->ol_flags = pkt_flags;
1473 rxm->packet_type = ixgbe_rxd_pkt_info_to_pkt_type(pkt_info);
1474 #else /* RTE_NEXT_ABI */
1475 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1476 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1477 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1479 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1480 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1481 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1482 rxm->ol_flags = pkt_flags;
1483 #endif /* RTE_NEXT_ABI */
1485 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1486 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
1487 else if (pkt_flags & PKT_RX_FDIR) {
1488 rxm->hash.fdir.hash =
1489 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1490 & IXGBE_ATR_HASH_MASK);
1491 rxm->hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1494 * Store the mbuf address into the next entry of the array
1495 * of returned packets.
1497 rx_pkts[nb_rx++] = rxm;
1499 rxq->rx_tail = rx_id;
1502 * If the number of free RX descriptors is greater than the RX free
1503 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1505 * Update the RDT with the value of the last processed RX descriptor
1506 * minus 1, to guarantee that the RDT register is never equal to the
1507 * RDH register, which creates a "full" ring situtation from the
1508 * hardware point of view...
1510 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1511 if (nb_hold > rxq->rx_free_thresh) {
1512 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1513 "nb_hold=%u nb_rx=%u",
1514 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1515 (unsigned) rx_id, (unsigned) nb_hold,
1517 rx_id = (uint16_t) ((rx_id == 0) ?
1518 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1519 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1522 rxq->nb_rx_hold = nb_hold;
1527 * Detect an RSC descriptor.
1529 static inline uint32_t
1530 ixgbe_rsc_count(union ixgbe_adv_rx_desc *rx)
1532 return (rte_le_to_cpu_32(rx->wb.lower.lo_dword.data) &
1533 IXGBE_RXDADV_RSCCNT_MASK) >> IXGBE_RXDADV_RSCCNT_SHIFT;
1537 * ixgbe_fill_cluster_head_buf - fill the first mbuf of the returned packet
1539 * Fill the following info in the HEAD buffer of the Rx cluster:
1540 * - RX port identifier
1541 * - hardware offload data, if any:
1543 * - IP checksum flag
1544 * - VLAN TCI, if any
1546 * @head HEAD of the packet cluster
1547 * @desc HW descriptor to get data from
1548 * @port_id Port ID of the Rx queue
1551 ixgbe_fill_cluster_head_buf(
1552 struct rte_mbuf *head,
1553 union ixgbe_adv_rx_desc *desc,
1561 head->port = port_id;
1563 /* The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1564 * set in the pkt_flags field.
1566 head->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);
1567 pkt_info = rte_le_to_cpu_32(desc->wb.lower.lo_dword.hs_rss.pkt_info);
1568 pkt_flags = rx_desc_status_to_pkt_flags(staterr);
1569 pkt_flags |= rx_desc_error_to_pkt_flags(staterr);
1570 pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags(pkt_info);
1571 head->ol_flags = pkt_flags;
1572 head->packet_type = ixgbe_rxd_pkt_info_to_pkt_type(pkt_info);
1573 #else /* RTE_NEXT_ABI */
1574 uint32_t hlen_type_rss;
1577 head->port = port_id;
1580 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1581 * set in the pkt_flags field.
1583 head->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);
1584 hlen_type_rss = rte_le_to_cpu_32(desc->wb.lower.lo_dword.data);
1585 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1586 pkt_flags |= rx_desc_status_to_pkt_flags(staterr);
1587 pkt_flags |= rx_desc_error_to_pkt_flags(staterr);
1588 head->ol_flags = pkt_flags;
1589 #endif /* RTE_NEXT_ABI */
1591 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1592 head->hash.rss = rte_le_to_cpu_32(desc->wb.lower.hi_dword.rss);
1593 else if (pkt_flags & PKT_RX_FDIR) {
1594 head->hash.fdir.hash =
1595 rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.csum)
1596 & IXGBE_ATR_HASH_MASK;
1597 head->hash.fdir.id =
1598 rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.ip_id);
1603 * ixgbe_recv_pkts_lro - receive handler for and LRO case.
1605 * @rx_queue Rx queue handle
1606 * @rx_pkts table of received packets
1607 * @nb_pkts size of rx_pkts table
1608 * @bulk_alloc if TRUE bulk allocation is used for a HW ring refilling
1610 * Handles the Rx HW ring completions when RSC feature is configured. Uses an
1611 * additional ring of ixgbe_rsc_entry's that will hold the relevant RSC info.
1613 * We use the same logic as in Linux and in FreeBSD ixgbe drivers:
1614 * 1) When non-EOP RSC completion arrives:
1615 * a) Update the HEAD of the current RSC aggregation cluster with the new
1616 * segment's data length.
1617 * b) Set the "next" pointer of the current segment to point to the segment
1618 * at the NEXTP index.
1619 * c) Pass the HEAD of RSC aggregation cluster on to the next NEXTP entry
1620 * in the sw_rsc_ring.
1621 * 2) When EOP arrives we just update the cluster's total length and offload
1622 * flags and deliver the cluster up to the upper layers. In our case - put it
1623 * in the rx_pkts table.
1625 * Returns the number of received packets/clusters (according to the "bulk
1626 * receive" interface).
1628 static inline uint16_t
1629 ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
1632 struct ixgbe_rx_queue *rxq = rx_queue;
1633 volatile union ixgbe_adv_rx_desc *rx_ring = rxq->rx_ring;
1634 struct ixgbe_rx_entry *sw_ring = rxq->sw_ring;
1635 struct ixgbe_scattered_rx_entry *sw_sc_ring = rxq->sw_sc_ring;
1636 uint16_t rx_id = rxq->rx_tail;
1638 uint16_t nb_hold = rxq->nb_rx_hold;
1639 uint16_t prev_id = rxq->rx_tail;
1641 while (nb_rx < nb_pkts) {
1643 struct ixgbe_rx_entry *rxe;
1644 struct ixgbe_scattered_rx_entry *sc_entry;
1645 struct ixgbe_scattered_rx_entry *next_sc_entry;
1646 struct ixgbe_rx_entry *next_rxe;
1647 struct rte_mbuf *first_seg;
1648 struct rte_mbuf *rxm;
1649 struct rte_mbuf *nmb;
1650 union ixgbe_adv_rx_desc rxd;
1653 volatile union ixgbe_adv_rx_desc *rxdp;
1658 * The code in this whole file uses the volatile pointer to
1659 * ensure the read ordering of the status and the rest of the
1660 * descriptor fields (on the compiler level only!!!). This is so
1661 * UGLY - why not to just use the compiler barrier instead? DPDK
1662 * even has the rte_compiler_barrier() for that.
1664 * But most importantly this is just wrong because this doesn't
1665 * ensure memory ordering in a general case at all. For
1666 * instance, DPDK is supposed to work on Power CPUs where
1667 * compiler barrier may just not be enough!
1669 * I tried to write only this function properly to have a
1670 * starting point (as a part of an LRO/RSC series) but the
1671 * compiler cursed at me when I tried to cast away the
1672 * "volatile" from rx_ring (yes, it's volatile too!!!). So, I'm
1673 * keeping it the way it is for now.
1675 * The code in this file is broken in so many other places and
1676 * will just not work on a big endian CPU anyway therefore the
1677 * lines below will have to be revisited together with the rest
1681 * - Get rid of "volatile" crap and let the compiler do its
1683 * - Use the proper memory barrier (rte_rmb()) to ensure the
1684 * memory ordering below.
1686 rxdp = &rx_ring[rx_id];
1687 staterr = rte_le_to_cpu_32(rxdp->wb.upper.status_error);
1689 if (!(staterr & IXGBE_RXDADV_STAT_DD))
1694 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1695 "staterr=0x%x data_len=%u",
1696 rxq->port_id, rxq->queue_id, rx_id, staterr,
1697 rte_le_to_cpu_16(rxd.wb.upper.length));
1700 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1702 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed "
1703 "port_id=%u queue_id=%u",
1704 rxq->port_id, rxq->queue_id);
1706 rte_eth_devices[rxq->port_id].data->
1707 rx_mbuf_alloc_failed++;
1711 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1712 else if (nb_hold > rxq->rx_free_thresh) {
1713 uint16_t next_rdt = rxq->rx_free_trigger;
1715 if (!ixgbe_rx_alloc_bufs(rxq, false)) {
1717 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr,
1719 nb_hold -= rxq->rx_free_thresh;
1721 PMD_RX_LOG(DEBUG, "RX bulk alloc failed "
1722 "port_id=%u queue_id=%u",
1723 rxq->port_id, rxq->queue_id);
1725 rte_eth_devices[rxq->port_id].data->
1726 rx_mbuf_alloc_failed++;
1733 rxe = &sw_ring[rx_id];
1734 eop = staterr & IXGBE_RXDADV_STAT_EOP;
1736 next_id = rx_id + 1;
1737 if (next_id == rxq->nb_rx_desc)
1740 /* Prefetch next mbuf while processing current one. */
1741 rte_ixgbe_prefetch(sw_ring[next_id].mbuf);
1744 * When next RX descriptor is on a cache-line boundary,
1745 * prefetch the next 4 RX descriptors and the next 4 pointers
1748 if ((next_id & 0x3) == 0) {
1749 rte_ixgbe_prefetch(&rx_ring[next_id]);
1750 rte_ixgbe_prefetch(&sw_ring[next_id]);
1757 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1759 * Update RX descriptor with the physical address of the
1760 * new data buffer of the new allocated mbuf.
1764 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1765 rxdp->read.hdr_addr = dma;
1766 rxdp->read.pkt_addr = dma;
1771 * Set data length & data buffer address of mbuf.
1773 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1774 rxm->data_len = data_len;
1779 * Get next descriptor index:
1780 * - For RSC it's in the NEXTP field.
1781 * - For a scattered packet - it's just a following
1784 if (ixgbe_rsc_count(&rxd))
1786 (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1787 IXGBE_RXDADV_NEXTP_SHIFT;
1791 next_sc_entry = &sw_sc_ring[nextp_id];
1792 next_rxe = &sw_ring[nextp_id];
1793 rte_ixgbe_prefetch(next_rxe);
1796 sc_entry = &sw_sc_ring[rx_id];
1797 first_seg = sc_entry->fbuf;
1798 sc_entry->fbuf = NULL;
1801 * If this is the first buffer of the received packet,
1802 * set the pointer to the first mbuf of the packet and
1803 * initialize its context.
1804 * Otherwise, update the total length and the number of segments
1805 * of the current scattered packet, and update the pointer to
1806 * the last mbuf of the current packet.
1808 if (first_seg == NULL) {
1810 first_seg->pkt_len = data_len;
1811 first_seg->nb_segs = 1;
1813 first_seg->pkt_len += data_len;
1814 first_seg->nb_segs++;
1821 * If this is not the last buffer of the received packet, update
1822 * the pointer to the first mbuf at the NEXTP entry in the
1823 * sw_sc_ring and continue to parse the RX ring.
1826 rxm->next = next_rxe->mbuf;
1827 next_sc_entry->fbuf = first_seg;
1832 * This is the last buffer of the received packet - return
1833 * the current cluster to the user.
1837 /* Initialize the first mbuf of the returned packet */
1838 ixgbe_fill_cluster_head_buf(first_seg, &rxd, rxq->port_id,
1841 /* Prefetch data of first segment, if configured to do so. */
1842 rte_packet_prefetch((char *)first_seg->buf_addr +
1843 first_seg->data_off);
1846 * Store the mbuf address into the next entry of the array
1847 * of returned packets.
1849 rx_pkts[nb_rx++] = first_seg;
1853 * Record index of the next RX descriptor to probe.
1855 rxq->rx_tail = rx_id;
1858 * If the number of free RX descriptors is greater than the RX free
1859 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1861 * Update the RDT with the value of the last processed RX descriptor
1862 * minus 1, to guarantee that the RDT register is never equal to the
1863 * RDH register, which creates a "full" ring situtation from the
1864 * hardware point of view...
1866 if (!bulk_alloc && nb_hold > rxq->rx_free_thresh) {
1867 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1868 "nb_hold=%u nb_rx=%u",
1869 rxq->port_id, rxq->queue_id, rx_id, nb_hold, nb_rx);
1872 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, prev_id);
1876 rxq->nb_rx_hold = nb_hold;
1881 ixgbe_recv_pkts_lro_single_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1884 return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, false);
1888 ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1891 return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, true);
1894 /*********************************************************************
1896 * Queue management functions
1898 **********************************************************************/
1901 * Rings setup and release.
1903 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1904 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1905 * also optimize cache line size effect. H/W supports up to cache line size 128.
1907 #define IXGBE_ALIGN 128
1910 * Maximum number of Ring Descriptors.
1912 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1913 * descriptors should meet the following condition:
1914 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1916 #define IXGBE_MIN_RING_DESC 32
1917 #define IXGBE_MAX_RING_DESC 4096
1920 * Create memzone for HW rings. malloc can't be used as the physical address is
1921 * needed. If the memzone is already created, then this function returns a ptr
1924 static const struct rte_memzone * __attribute__((cold))
1925 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1926 uint16_t queue_id, uint32_t ring_size, int socket_id)
1928 char z_name[RTE_MEMZONE_NAMESIZE];
1929 const struct rte_memzone *mz;
1931 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1932 dev->driver->pci_drv.name, ring_name,
1933 dev->data->port_id, queue_id);
1935 mz = rte_memzone_lookup(z_name);
1939 #ifdef RTE_LIBRTE_XEN_DOM0
1940 return rte_memzone_reserve_bounded(z_name, ring_size,
1941 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1943 return rte_memzone_reserve_aligned(z_name, ring_size,
1944 socket_id, 0, IXGBE_ALIGN);
1948 static void __attribute__((cold))
1949 ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)
1953 if (txq->sw_ring != NULL) {
1954 for (i = 0; i < txq->nb_tx_desc; i++) {
1955 if (txq->sw_ring[i].mbuf != NULL) {
1956 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1957 txq->sw_ring[i].mbuf = NULL;
1963 static void __attribute__((cold))
1964 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
1967 txq->sw_ring != NULL)
1968 rte_free(txq->sw_ring);
1971 static void __attribute__((cold))
1972 ixgbe_tx_queue_release(struct ixgbe_tx_queue *txq)
1974 if (txq != NULL && txq->ops != NULL) {
1975 txq->ops->release_mbufs(txq);
1976 txq->ops->free_swring(txq);
1981 void __attribute__((cold))
1982 ixgbe_dev_tx_queue_release(void *txq)
1984 ixgbe_tx_queue_release(txq);
1987 /* (Re)set dynamic ixgbe_tx_queue fields to defaults */
1988 static void __attribute__((cold))
1989 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
1991 static const union ixgbe_adv_tx_desc zeroed_desc = {{0}};
1992 struct ixgbe_tx_entry *txe = txq->sw_ring;
1995 /* Zero out HW ring memory */
1996 for (i = 0; i < txq->nb_tx_desc; i++) {
1997 txq->tx_ring[i] = zeroed_desc;
2000 /* Initialize SW ring entries */
2001 prev = (uint16_t) (txq->nb_tx_desc - 1);
2002 for (i = 0; i < txq->nb_tx_desc; i++) {
2003 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
2004 txd->wb.status = IXGBE_TXD_STAT_DD;
2007 txe[prev].next_id = i;
2011 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2012 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2015 txq->nb_tx_used = 0;
2017 * Always allow 1 descriptor to be un-allocated to avoid
2018 * a H/W race condition
2020 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2021 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2023 memset((void*)&txq->ctx_cache, 0,
2024 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
2027 static const struct ixgbe_txq_ops def_txq_ops = {
2028 .release_mbufs = ixgbe_tx_queue_release_mbufs,
2029 .free_swring = ixgbe_tx_free_swring,
2030 .reset = ixgbe_reset_tx_queue,
2033 /* Takes an ethdev and a queue and sets up the tx function to be used based on
2034 * the queue parameters. Used in tx_queue_setup by primary process and then
2035 * in dev_init by secondary process when attaching to an existing ethdev.
2037 void __attribute__((cold))
2038 ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)
2040 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2041 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS)
2042 && (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
2043 PMD_INIT_LOG(INFO, "Using simple tx code path");
2044 #ifdef RTE_IXGBE_INC_VECTOR
2045 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
2046 (rte_eal_process_type() != RTE_PROC_PRIMARY ||
2047 ixgbe_txq_vec_setup(txq) == 0)) {
2048 PMD_INIT_LOG(INFO, "Vector tx enabled.");
2049 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
2052 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
2054 PMD_INIT_LOG(INFO, "Using full-featured tx code path");
2056 " - txq_flags = %lx " "[IXGBE_SIMPLE_FLAGS=%lx]",
2057 (unsigned long)txq->txq_flags,
2058 (unsigned long)IXGBE_SIMPLE_FLAGS);
2060 " - tx_rs_thresh = %lu " "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
2061 (unsigned long)txq->tx_rs_thresh,
2062 (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST);
2063 dev->tx_pkt_burst = ixgbe_xmit_pkts;
2067 int __attribute__((cold))
2068 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
2071 unsigned int socket_id,
2072 const struct rte_eth_txconf *tx_conf)
2074 const struct rte_memzone *tz;
2075 struct ixgbe_tx_queue *txq;
2076 struct ixgbe_hw *hw;
2077 uint16_t tx_rs_thresh, tx_free_thresh;
2079 PMD_INIT_FUNC_TRACE();
2080 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2083 * Validate number of transmit descriptors.
2084 * It must not exceed hardware maximum, and must be multiple
2087 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
2088 (nb_desc > IXGBE_MAX_RING_DESC) ||
2089 (nb_desc < IXGBE_MIN_RING_DESC)) {
2094 * The following two parameters control the setting of the RS bit on
2095 * transmit descriptors.
2096 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
2097 * descriptors have been used.
2098 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
2099 * descriptors are used or if the number of descriptors required
2100 * to transmit a packet is greater than the number of free TX
2102 * The following constraints must be satisfied:
2103 * tx_rs_thresh must be greater than 0.
2104 * tx_rs_thresh must be less than the size of the ring minus 2.
2105 * tx_rs_thresh must be less than or equal to tx_free_thresh.
2106 * tx_rs_thresh must be a divisor of the ring size.
2107 * tx_free_thresh must be greater than 0.
2108 * tx_free_thresh must be less than the size of the ring minus 3.
2109 * One descriptor in the TX ring is used as a sentinel to avoid a
2110 * H/W race condition, hence the maximum threshold constraints.
2111 * When set to zero use default values.
2113 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2114 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2115 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2116 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2117 if (tx_rs_thresh >= (nb_desc - 2)) {
2118 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
2119 "of TX descriptors minus 2. (tx_rs_thresh=%u "
2120 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2121 (int)dev->data->port_id, (int)queue_idx);
2124 if (tx_free_thresh >= (nb_desc - 3)) {
2125 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2126 "tx_free_thresh must be less than the number of "
2127 "TX descriptors minus 3. (tx_free_thresh=%u "
2128 "port=%d queue=%d)",
2129 (unsigned int)tx_free_thresh,
2130 (int)dev->data->port_id, (int)queue_idx);
2133 if (tx_rs_thresh > tx_free_thresh) {
2134 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
2135 "tx_free_thresh. (tx_free_thresh=%u "
2136 "tx_rs_thresh=%u port=%d queue=%d)",
2137 (unsigned int)tx_free_thresh,
2138 (unsigned int)tx_rs_thresh,
2139 (int)dev->data->port_id,
2143 if ((nb_desc % tx_rs_thresh) != 0) {
2144 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2145 "number of TX descriptors. (tx_rs_thresh=%u "
2146 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2147 (int)dev->data->port_id, (int)queue_idx);
2152 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
2153 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
2154 * by the NIC and all descriptors are written back after the NIC
2155 * accumulates WTHRESH descriptors.
2157 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2158 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2159 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
2160 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2161 (int)dev->data->port_id, (int)queue_idx);
2165 /* Free memory prior to re-allocation if needed... */
2166 if (dev->data->tx_queues[queue_idx] != NULL) {
2167 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
2168 dev->data->tx_queues[queue_idx] = NULL;
2171 /* First allocate the tx queue data structure */
2172 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct ixgbe_tx_queue),
2173 RTE_CACHE_LINE_SIZE, socket_id);
2178 * Allocate TX ring hardware descriptors. A memzone large enough to
2179 * handle the maximum ring size is allocated in order to allow for
2180 * resizing in later calls to the queue setup function.
2182 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
2183 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
2186 ixgbe_tx_queue_release(txq);
2190 txq->nb_tx_desc = nb_desc;
2191 txq->tx_rs_thresh = tx_rs_thresh;
2192 txq->tx_free_thresh = tx_free_thresh;
2193 txq->pthresh = tx_conf->tx_thresh.pthresh;
2194 txq->hthresh = tx_conf->tx_thresh.hthresh;
2195 txq->wthresh = tx_conf->tx_thresh.wthresh;
2196 txq->queue_id = queue_idx;
2197 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2198 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2199 txq->port_id = dev->data->port_id;
2200 txq->txq_flags = tx_conf->txq_flags;
2201 txq->ops = &def_txq_ops;
2202 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2205 * Modification to set VFTDT for virtual function if vf is detected
2207 if (hw->mac.type == ixgbe_mac_82599_vf ||
2208 hw->mac.type == ixgbe_mac_X540_vf ||
2209 hw->mac.type == ixgbe_mac_X550_vf ||
2210 hw->mac.type == ixgbe_mac_X550EM_x_vf)
2211 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
2213 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
2214 #ifndef RTE_LIBRTE_XEN_DOM0
2215 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
2217 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2219 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
2221 /* Allocate software ring */
2222 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
2223 sizeof(struct ixgbe_tx_entry) * nb_desc,
2224 RTE_CACHE_LINE_SIZE, socket_id);
2225 if (txq->sw_ring == NULL) {
2226 ixgbe_tx_queue_release(txq);
2229 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2230 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
2232 /* set up vector or scalar TX function as appropriate */
2233 ixgbe_set_tx_function(dev, txq);
2235 txq->ops->reset(txq);
2237 dev->data->tx_queues[queue_idx] = txq;
2244 * ixgbe_free_sc_cluster - free the not-yet-completed scattered cluster
2246 * The "next" pointer of the last segment of (not-yet-completed) RSC clusters
2247 * in the sw_rsc_ring is not set to NULL but rather points to the next
2248 * mbuf of this RSC aggregation (that has not been completed yet and still
2249 * resides on the HW ring). So, instead of calling for rte_pktmbuf_free() we
2250 * will just free first "nb_segs" segments of the cluster explicitly by calling
2251 * an rte_pktmbuf_free_seg().
2253 * @m scattered cluster head
2255 static void __attribute__((cold))
2256 ixgbe_free_sc_cluster(struct rte_mbuf *m)
2258 uint8_t i, nb_segs = m->nb_segs;
2259 struct rte_mbuf *next_seg;
2261 for (i = 0; i < nb_segs; i++) {
2263 rte_pktmbuf_free_seg(m);
2268 static void __attribute__((cold))
2269 ixgbe_rx_queue_release_mbufs(struct ixgbe_rx_queue *rxq)
2273 if (rxq->sw_ring != NULL) {
2274 for (i = 0; i < rxq->nb_rx_desc; i++) {
2275 if (rxq->sw_ring[i].mbuf != NULL &&
2276 rte_mbuf_refcnt_read(rxq->sw_ring[i].mbuf)) {
2277 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2278 rxq->sw_ring[i].mbuf = NULL;
2281 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2282 if (rxq->rx_nb_avail) {
2283 for (i = 0; i < rxq->rx_nb_avail; ++i) {
2284 struct rte_mbuf *mb;
2285 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2286 rte_pktmbuf_free_seg(mb);
2288 rxq->rx_nb_avail = 0;
2293 if (rxq->sw_sc_ring)
2294 for (i = 0; i < rxq->nb_rx_desc; i++)
2295 if (rxq->sw_sc_ring[i].fbuf) {
2296 ixgbe_free_sc_cluster(rxq->sw_sc_ring[i].fbuf);
2297 rxq->sw_sc_ring[i].fbuf = NULL;
2301 static void __attribute__((cold))
2302 ixgbe_rx_queue_release(struct ixgbe_rx_queue *rxq)
2305 ixgbe_rx_queue_release_mbufs(rxq);
2306 rte_free(rxq->sw_ring);
2307 rte_free(rxq->sw_sc_ring);
2312 void __attribute__((cold))
2313 ixgbe_dev_rx_queue_release(void *rxq)
2315 ixgbe_rx_queue_release(rxq);
2319 * Check if Rx Burst Bulk Alloc function can be used.
2321 * 0: the preconditions are satisfied and the bulk allocation function
2323 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2324 * function must be used.
2326 static inline int __attribute__((cold))
2327 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2328 check_rx_burst_bulk_alloc_preconditions(struct ixgbe_rx_queue *rxq)
2330 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct ixgbe_rx_queue *rxq)
2336 * Make sure the following pre-conditions are satisfied:
2337 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2338 * rxq->rx_free_thresh < rxq->nb_rx_desc
2339 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2340 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
2341 * Scattered packets are not supported. This should be checked
2342 * outside of this function.
2344 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2345 if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
2346 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2347 "rxq->rx_free_thresh=%d, "
2348 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2349 rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
2351 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
2352 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2353 "rxq->rx_free_thresh=%d, "
2354 "rxq->nb_rx_desc=%d",
2355 rxq->rx_free_thresh, rxq->nb_rx_desc);
2357 } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
2358 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2359 "rxq->nb_rx_desc=%d, "
2360 "rxq->rx_free_thresh=%d",
2361 rxq->nb_rx_desc, rxq->rx_free_thresh);
2363 } else if (!(rxq->nb_rx_desc <
2364 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST))) {
2365 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2366 "rxq->nb_rx_desc=%d, "
2367 "IXGBE_MAX_RING_DESC=%d, "
2368 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2369 rxq->nb_rx_desc, IXGBE_MAX_RING_DESC,
2370 RTE_PMD_IXGBE_RX_MAX_BURST);
2380 /* Reset dynamic ixgbe_rx_queue fields back to defaults */
2381 static void __attribute__((cold))
2382 ixgbe_reset_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_rx_queue *rxq)
2384 static const union ixgbe_adv_rx_desc zeroed_desc = {{0}};
2386 uint16_t len = rxq->nb_rx_desc;
2389 * By default, the Rx queue setup function allocates enough memory for
2390 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2391 * extra memory at the end of the descriptor ring to be zero'd out. A
2392 * pre-condition for using the Rx burst bulk alloc function is that the
2393 * number of descriptors is less than or equal to
2394 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2395 * constraints here to see if we need to zero out memory after the end
2396 * of the H/W descriptor ring.
2398 if (adapter->rx_bulk_alloc_allowed)
2399 /* zero out extra memory */
2400 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2403 * Zero out HW ring memory. Zero out extra memory at the end of
2404 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2405 * reads extra memory as zeros.
2407 for (i = 0; i < len; i++) {
2408 rxq->rx_ring[i] = zeroed_desc;
2411 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2413 * initialize extra software ring entries. Space for these extra
2414 * entries is always allocated
2416 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2417 for (i = rxq->nb_rx_desc; i < len; ++i) {
2418 rxq->sw_ring[i].mbuf = &rxq->fake_mbuf;
2421 rxq->rx_nb_avail = 0;
2422 rxq->rx_next_avail = 0;
2423 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2424 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2426 rxq->nb_rx_hold = 0;
2427 rxq->pkt_first_seg = NULL;
2428 rxq->pkt_last_seg = NULL;
2431 int __attribute__((cold))
2432 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2435 unsigned int socket_id,
2436 const struct rte_eth_rxconf *rx_conf,
2437 struct rte_mempool *mp)
2439 const struct rte_memzone *rz;
2440 struct ixgbe_rx_queue *rxq;
2441 struct ixgbe_hw *hw;
2443 struct ixgbe_adapter *adapter =
2444 (struct ixgbe_adapter *)dev->data->dev_private;
2446 PMD_INIT_FUNC_TRACE();
2447 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2450 * Validate number of receive descriptors.
2451 * It must not exceed hardware maximum, and must be multiple
2454 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2455 (nb_desc > IXGBE_MAX_RING_DESC) ||
2456 (nb_desc < IXGBE_MIN_RING_DESC)) {
2460 /* Free memory prior to re-allocation if needed... */
2461 if (dev->data->rx_queues[queue_idx] != NULL) {
2462 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2463 dev->data->rx_queues[queue_idx] = NULL;
2466 /* First allocate the rx queue data structure */
2467 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct ixgbe_rx_queue),
2468 RTE_CACHE_LINE_SIZE, socket_id);
2472 rxq->nb_rx_desc = nb_desc;
2473 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2474 rxq->queue_id = queue_idx;
2475 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2476 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2477 rxq->port_id = dev->data->port_id;
2478 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2480 rxq->drop_en = rx_conf->rx_drop_en;
2481 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2484 * Allocate RX ring hardware descriptors. A memzone large enough to
2485 * handle the maximum ring size is allocated in order to allow for
2486 * resizing in later calls to the queue setup function.
2488 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2489 RX_RING_SZ, socket_id);
2491 ixgbe_rx_queue_release(rxq);
2496 * Zero init all the descriptors in the ring.
2498 memset (rz->addr, 0, RX_RING_SZ);
2501 * Modified to setup VFRDT for Virtual Function
2503 if (hw->mac.type == ixgbe_mac_82599_vf ||
2504 hw->mac.type == ixgbe_mac_X540_vf ||
2505 hw->mac.type == ixgbe_mac_X550_vf ||
2506 hw->mac.type == ixgbe_mac_X550EM_x_vf) {
2508 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2510 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2514 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2516 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2518 #ifndef RTE_LIBRTE_XEN_DOM0
2519 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2521 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2523 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2526 * Certain constraints must be met in order to use the bulk buffer
2527 * allocation Rx burst function. If any of Rx queues doesn't meet them
2528 * the feature should be disabled for the whole port.
2530 if (check_rx_burst_bulk_alloc_preconditions(rxq)) {
2531 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Rx Bulk Alloc "
2532 "preconditions - canceling the feature for "
2533 "the whole port[%d]",
2534 rxq->queue_id, rxq->port_id);
2535 adapter->rx_bulk_alloc_allowed = false;
2539 * Allocate software ring. Allow for space at the end of the
2540 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2541 * function does not access an invalid memory region.
2544 if (adapter->rx_bulk_alloc_allowed)
2545 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2547 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2548 sizeof(struct ixgbe_rx_entry) * len,
2549 RTE_CACHE_LINE_SIZE, socket_id);
2550 if (!rxq->sw_ring) {
2551 ixgbe_rx_queue_release(rxq);
2556 * Always allocate even if it's not going to be needed in order to
2557 * simplify the code.
2559 * This ring is used in LRO and Scattered Rx cases and Scattered Rx may
2560 * be requested in ixgbe_dev_rx_init(), which is called later from
2564 rte_zmalloc_socket("rxq->sw_sc_ring",
2565 sizeof(struct ixgbe_scattered_rx_entry) * len,
2566 RTE_CACHE_LINE_SIZE, socket_id);
2567 if (!rxq->sw_sc_ring) {
2568 ixgbe_rx_queue_release(rxq);
2572 PMD_INIT_LOG(DEBUG, "sw_ring=%p sw_sc_ring=%p hw_ring=%p "
2573 "dma_addr=0x%"PRIx64,
2574 rxq->sw_ring, rxq->sw_sc_ring, rxq->rx_ring,
2575 rxq->rx_ring_phys_addr);
2577 if (!rte_is_power_of_2(nb_desc)) {
2578 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
2579 "preconditions - canceling the feature for "
2580 "the whole port[%d]",
2581 rxq->queue_id, rxq->port_id);
2582 adapter->rx_vec_allowed = false;
2584 ixgbe_rxq_vec_setup(rxq);
2586 dev->data->rx_queues[queue_idx] = rxq;
2588 ixgbe_reset_rx_queue(adapter, rxq);
2594 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2596 #define IXGBE_RXQ_SCAN_INTERVAL 4
2597 volatile union ixgbe_adv_rx_desc *rxdp;
2598 struct ixgbe_rx_queue *rxq;
2601 if (rx_queue_id >= dev->data->nb_rx_queues) {
2602 PMD_RX_LOG(ERR, "Invalid RX queue id=%d", rx_queue_id);
2606 rxq = dev->data->rx_queues[rx_queue_id];
2607 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2609 while ((desc < rxq->nb_rx_desc) &&
2610 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2611 desc += IXGBE_RXQ_SCAN_INTERVAL;
2612 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2613 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2614 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2615 desc - rxq->nb_rx_desc]);
2622 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2624 volatile union ixgbe_adv_rx_desc *rxdp;
2625 struct ixgbe_rx_queue *rxq = rx_queue;
2628 if (unlikely(offset >= rxq->nb_rx_desc))
2630 desc = rxq->rx_tail + offset;
2631 if (desc >= rxq->nb_rx_desc)
2632 desc -= rxq->nb_rx_desc;
2634 rxdp = &rxq->rx_ring[desc];
2635 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2638 void __attribute__((cold))
2639 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2642 struct ixgbe_adapter *adapter =
2643 (struct ixgbe_adapter *)dev->data->dev_private;
2645 PMD_INIT_FUNC_TRACE();
2647 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2648 struct ixgbe_tx_queue *txq = dev->data->tx_queues[i];
2650 txq->ops->release_mbufs(txq);
2651 txq->ops->reset(txq);
2655 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2656 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
2658 ixgbe_rx_queue_release_mbufs(rxq);
2659 ixgbe_reset_rx_queue(adapter, rxq);
2665 ixgbe_dev_free_queues(struct rte_eth_dev *dev)
2669 PMD_INIT_FUNC_TRACE();
2671 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2672 ixgbe_dev_rx_queue_release(dev->data->rx_queues[i]);
2673 dev->data->rx_queues[i] = NULL;
2675 dev->data->nb_rx_queues = 0;
2677 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2678 ixgbe_dev_tx_queue_release(dev->data->tx_queues[i]);
2679 dev->data->tx_queues[i] = NULL;
2681 dev->data->nb_tx_queues = 0;
2684 /*********************************************************************
2686 * Device RX/TX init functions
2688 **********************************************************************/
2691 * Receive Side Scaling (RSS)
2692 * See section 7.1.2.8 in the following document:
2693 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2696 * The source and destination IP addresses of the IP header and the source
2697 * and destination ports of TCP/UDP headers, if any, of received packets are
2698 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2699 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2700 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2701 * RSS output index which is used as the RX queue index where to store the
2703 * The following output is supplied in the RX write-back descriptor:
2704 * - 32-bit result of the Microsoft RSS hash function,
2705 * - 4-bit RSS type field.
2709 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2710 * Used as the default key.
2712 static uint8_t rss_intel_key[40] = {
2713 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2714 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2715 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2716 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2717 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2721 ixgbe_rss_disable(struct rte_eth_dev *dev)
2723 struct ixgbe_hw *hw;
2726 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2727 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2728 mrqc &= ~IXGBE_MRQC_RSSEN;
2729 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2733 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2741 hash_key = rss_conf->rss_key;
2742 if (hash_key != NULL) {
2743 /* Fill in RSS hash key */
2744 for (i = 0; i < 10; i++) {
2745 rss_key = hash_key[(i * 4)];
2746 rss_key |= hash_key[(i * 4) + 1] << 8;
2747 rss_key |= hash_key[(i * 4) + 2] << 16;
2748 rss_key |= hash_key[(i * 4) + 3] << 24;
2749 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2753 /* Set configured hashing protocols in MRQC register */
2754 rss_hf = rss_conf->rss_hf;
2755 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2756 if (rss_hf & ETH_RSS_IPV4)
2757 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2758 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2759 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2760 if (rss_hf & ETH_RSS_IPV6)
2761 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2762 if (rss_hf & ETH_RSS_IPV6_EX)
2763 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2764 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2765 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2766 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2767 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2768 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2769 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2770 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2771 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2772 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2773 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2774 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2778 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2779 struct rte_eth_rss_conf *rss_conf)
2781 struct ixgbe_hw *hw;
2785 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2788 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2789 * "RSS enabling cannot be done dynamically while it must be
2790 * preceded by a software reset"
2791 * Before changing anything, first check that the update RSS operation
2792 * does not attempt to disable RSS, if RSS was enabled at
2793 * initialization time, or does not attempt to enable RSS, if RSS was
2794 * disabled at initialization time.
2796 rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
2797 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2798 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2799 if (rss_hf != 0) /* Enable RSS */
2801 return 0; /* Nothing to do */
2804 if (rss_hf == 0) /* Disable RSS */
2806 ixgbe_hw_rss_hash_set(hw, rss_conf);
2811 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2812 struct rte_eth_rss_conf *rss_conf)
2814 struct ixgbe_hw *hw;
2821 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2822 hash_key = rss_conf->rss_key;
2823 if (hash_key != NULL) {
2824 /* Return RSS hash key */
2825 for (i = 0; i < 10; i++) {
2826 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2827 hash_key[(i * 4)] = rss_key & 0x000000FF;
2828 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2829 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2830 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2834 /* Get RSS functions configured in MRQC register */
2835 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2836 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2837 rss_conf->rss_hf = 0;
2841 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2842 rss_hf |= ETH_RSS_IPV4;
2843 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2844 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2845 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2846 rss_hf |= ETH_RSS_IPV6;
2847 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2848 rss_hf |= ETH_RSS_IPV6_EX;
2849 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2850 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2851 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2852 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2853 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2854 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2855 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2856 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2857 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2858 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2859 rss_conf->rss_hf = rss_hf;
2864 ixgbe_rss_configure(struct rte_eth_dev *dev)
2866 struct rte_eth_rss_conf rss_conf;
2867 struct ixgbe_hw *hw;
2872 PMD_INIT_FUNC_TRACE();
2873 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876 * Fill in redirection table
2877 * The byte-swap is needed because NIC registers are in
2878 * little-endian order.
2881 for (i = 0, j = 0; i < 128; i++, j++) {
2882 if (j == dev->data->nb_rx_queues)
2884 reta = (reta << 8) | j;
2886 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2891 * Configure the RSS key and the RSS protocols used to compute
2892 * the RSS hash of input packets.
2894 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2895 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
2896 ixgbe_rss_disable(dev);
2899 if (rss_conf.rss_key == NULL)
2900 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2901 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2904 #define NUM_VFTA_REGISTERS 128
2905 #define NIC_RX_BUFFER_SIZE 0x200
2908 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2910 struct rte_eth_vmdq_dcb_conf *cfg;
2911 struct ixgbe_hw *hw;
2912 enum rte_eth_nb_pools num_pools;
2913 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2915 uint8_t nb_tcs; /* number of traffic classes */
2918 PMD_INIT_FUNC_TRACE();
2919 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2920 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2921 num_pools = cfg->nb_queue_pools;
2922 /* Check we have a valid number of pools */
2923 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2924 ixgbe_rss_disable(dev);
2927 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2928 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2932 * split rx buffer up into sections, each for 1 traffic class
2934 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2935 for (i = 0 ; i < nb_tcs; i++) {
2936 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2937 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2938 /* clear 10 bits. */
2939 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2940 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2942 /* zero alloc all unused TCs */
2943 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2944 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2945 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2946 /* clear 10 bits. */
2947 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2950 /* MRQC: enable vmdq and dcb */
2951 mrqc = ((num_pools == ETH_16_POOLS) ? \
2952 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2953 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2955 /* PFVTCTL: turn on virtualisation and set the default pool */
2956 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2957 if (cfg->enable_default_pool) {
2958 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2960 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2963 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2965 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2967 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2969 * mapping is done with 3 bits per priority,
2970 * so shift by i*3 each time
2972 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2974 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2976 /* RTRPCS: DCB related */
2977 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2979 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2980 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2981 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2982 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2984 /* VFTA - enable all vlan filters */
2985 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2986 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2989 /* VFRE: pool enabling for receive - 16 or 32 */
2990 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2991 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2994 * MPSAR - allow pools to read specific mac addresses
2995 * In this case, all pools should be able to read from mac addr 0
2997 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2998 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
3000 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3001 for (i = 0; i < cfg->nb_pool_maps; i++) {
3002 /* set vlan id in VF register and set the valid bit */
3003 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3004 (cfg->pool_map[i].vlan_id & 0xFFF)));
3006 * Put the allowed pools in VFB reg. As we only have 16 or 32
3007 * pools, we only need to use the first half of the register
3010 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
3015 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
3016 * @hw: pointer to hardware structure
3017 * @dcb_config: pointer to ixgbe_dcb_config structure
3020 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
3021 struct ixgbe_dcb_config *dcb_config)
3026 PMD_INIT_FUNC_TRACE();
3027 if (hw->mac.type != ixgbe_mac_82598EB) {
3028 /* Disable the Tx desc arbiter so that MTQC can be changed */
3029 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3030 reg |= IXGBE_RTTDCS_ARBDIS;
3031 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3033 /* Enable DCB for Tx with 8 TCs */
3034 if (dcb_config->num_tcs.pg_tcs == 8) {
3035 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3038 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3040 if (dcb_config->vt_mode)
3041 reg |= IXGBE_MTQC_VT_ENA;
3042 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3044 /* Disable drop for all queues */
3045 for (q = 0; q < 128; q++)
3046 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3047 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3049 /* Enable the Tx desc arbiter */
3050 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3051 reg &= ~IXGBE_RTTDCS_ARBDIS;
3052 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3054 /* Enable Security TX Buffer IFG for DCB */
3055 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3056 reg |= IXGBE_SECTX_DCB;
3057 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
3063 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
3064 * @dev: pointer to rte_eth_dev structure
3065 * @dcb_config: pointer to ixgbe_dcb_config structure
3068 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
3069 struct ixgbe_dcb_config *dcb_config)
3071 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3072 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3073 struct ixgbe_hw *hw =
3074 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3076 PMD_INIT_FUNC_TRACE();
3077 if (hw->mac.type != ixgbe_mac_82598EB)
3078 /*PF VF Transmit Enable*/
3079 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
3080 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3082 /*Configure general DCB TX parameters*/
3083 ixgbe_dcb_tx_hw_config(hw,dcb_config);
3088 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
3089 struct ixgbe_dcb_config *dcb_config)
3091 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
3092 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3093 struct ixgbe_dcb_tc_config *tc;
3096 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3097 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
3098 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3099 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3102 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3103 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3105 /* User Priority to Traffic Class mapping */
3106 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3107 j = vmdq_rx_conf->dcb_queue[i];
3108 tc = &dcb_config->tc_config[j];
3109 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
3115 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
3116 struct ixgbe_dcb_config *dcb_config)
3118 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3119 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3120 struct ixgbe_dcb_tc_config *tc;
3123 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3124 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
3125 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3126 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3129 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3130 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3133 /* User Priority to Traffic Class mapping */
3134 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3135 j = vmdq_tx_conf->dcb_queue[i];
3136 tc = &dcb_config->tc_config[j];
3137 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
3144 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
3145 struct ixgbe_dcb_config *dcb_config)
3147 struct rte_eth_dcb_rx_conf *rx_conf =
3148 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
3149 struct ixgbe_dcb_tc_config *tc;
3152 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
3153 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
3155 /* User Priority to Traffic Class mapping */
3156 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3157 j = rx_conf->dcb_queue[i];
3158 tc = &dcb_config->tc_config[j];
3159 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
3165 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
3166 struct ixgbe_dcb_config *dcb_config)
3168 struct rte_eth_dcb_tx_conf *tx_conf =
3169 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
3170 struct ixgbe_dcb_tc_config *tc;
3173 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
3174 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
3176 /* User Priority to Traffic Class mapping */
3177 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3178 j = tx_conf->dcb_queue[i];
3179 tc = &dcb_config->tc_config[j];
3180 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
3186 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
3187 * @hw: pointer to hardware structure
3188 * @dcb_config: pointer to ixgbe_dcb_config structure
3191 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
3192 struct ixgbe_dcb_config *dcb_config)
3198 PMD_INIT_FUNC_TRACE();
3200 * Disable the arbiter before changing parameters
3201 * (always enable recycle mode; WSP)
3203 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
3204 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3206 if (hw->mac.type != ixgbe_mac_82598EB) {
3207 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
3208 if (dcb_config->num_tcs.pg_tcs == 4) {
3209 if (dcb_config->vt_mode)
3210 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3211 IXGBE_MRQC_VMDQRT4TCEN;
3213 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3214 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3218 if (dcb_config->num_tcs.pg_tcs == 8) {
3219 if (dcb_config->vt_mode)
3220 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3221 IXGBE_MRQC_VMDQRT8TCEN;
3223 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3224 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3229 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
3232 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3233 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3234 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3235 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3237 /* VFTA - enable all vlan filters */
3238 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3239 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3243 * Configure Rx packet plane (recycle mode; WSP) and
3246 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
3247 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3253 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
3254 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3256 switch (hw->mac.type) {
3257 case ixgbe_mac_82598EB:
3258 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
3260 case ixgbe_mac_82599EB:
3261 case ixgbe_mac_X540:
3262 case ixgbe_mac_X550:
3263 case ixgbe_mac_X550EM_x:
3264 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
3273 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
3274 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3276 switch (hw->mac.type) {
3277 case ixgbe_mac_82598EB:
3278 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
3279 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
3281 case ixgbe_mac_82599EB:
3282 case ixgbe_mac_X540:
3283 case ixgbe_mac_X550:
3284 case ixgbe_mac_X550EM_x:
3285 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
3286 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
3293 #define DCB_RX_CONFIG 1
3294 #define DCB_TX_CONFIG 1
3295 #define DCB_TX_PB 1024
3297 * ixgbe_dcb_hw_configure - Enable DCB and configure
3298 * general DCB in VT mode and non-VT mode parameters
3299 * @dev: pointer to rte_eth_dev structure
3300 * @dcb_config: pointer to ixgbe_dcb_config structure
3303 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
3304 struct ixgbe_dcb_config *dcb_config)
3307 uint8_t i,pfc_en,nb_tcs;
3309 uint8_t config_dcb_rx = 0;
3310 uint8_t config_dcb_tx = 0;
3311 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3312 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3313 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3314 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3315 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3316 struct ixgbe_dcb_tc_config *tc;
3317 uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3318 struct ixgbe_hw *hw =
3319 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3321 switch(dev->data->dev_conf.rxmode.mq_mode){
3322 case ETH_MQ_RX_VMDQ_DCB:
3323 dcb_config->vt_mode = true;
3324 if (hw->mac.type != ixgbe_mac_82598EB) {
3325 config_dcb_rx = DCB_RX_CONFIG;
3327 *get dcb and VT rx configuration parameters
3330 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
3331 /*Configure general VMDQ and DCB RX parameters*/
3332 ixgbe_vmdq_dcb_configure(dev);
3336 dcb_config->vt_mode = false;
3337 config_dcb_rx = DCB_RX_CONFIG;
3338 /* Get dcb TX configuration parameters from rte_eth_conf */
3339 ixgbe_dcb_rx_config(dev,dcb_config);
3340 /*Configure general DCB RX parameters*/
3341 ixgbe_dcb_rx_hw_config(hw, dcb_config);
3344 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
3347 switch (dev->data->dev_conf.txmode.mq_mode) {
3348 case ETH_MQ_TX_VMDQ_DCB:
3349 dcb_config->vt_mode = true;
3350 config_dcb_tx = DCB_TX_CONFIG;
3351 /* get DCB and VT TX configuration parameters from rte_eth_conf */
3352 ixgbe_dcb_vt_tx_config(dev,dcb_config);
3353 /*Configure general VMDQ and DCB TX parameters*/
3354 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
3358 dcb_config->vt_mode = false;
3359 config_dcb_tx = DCB_TX_CONFIG;
3360 /*get DCB TX configuration parameters from rte_eth_conf*/
3361 ixgbe_dcb_tx_config(dev,dcb_config);
3362 /*Configure general DCB TX parameters*/
3363 ixgbe_dcb_tx_hw_config(hw, dcb_config);
3366 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
3370 nb_tcs = dcb_config->num_tcs.pfc_tcs;
3372 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3373 if(nb_tcs == ETH_4_TCS) {
3374 /* Avoid un-configured priority mapping to TC0 */
3376 uint8_t mask = 0xFF;
3377 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
3378 mask = (uint8_t)(mask & (~ (1 << map[i])));
3379 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
3380 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
3384 /* Re-configure 4 TCs BW */
3385 for (i = 0; i < nb_tcs; i++) {
3386 tc = &dcb_config->tc_config[i];
3387 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
3388 (uint8_t)(100 / nb_tcs);
3389 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
3390 (uint8_t)(100 / nb_tcs);
3392 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3393 tc = &dcb_config->tc_config[i];
3394 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
3395 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
3400 /* Set RX buffer size */
3401 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3402 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
3403 for (i = 0 ; i < nb_tcs; i++) {
3404 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3406 /* zero alloc all unused TCs */
3407 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3408 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3412 /* Only support an equally distributed Tx packet buffer strategy. */
3413 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
3414 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
3415 for (i = 0; i < nb_tcs; i++) {
3416 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3417 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3419 /* Clear unused TCs, if any, to zero buffer size*/
3420 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3421 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3422 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3426 /*Calculates traffic class credits*/
3427 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3428 IXGBE_DCB_TX_CONFIG);
3429 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3430 IXGBE_DCB_RX_CONFIG);
3433 /* Unpack CEE standard containers */
3434 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
3435 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3436 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3437 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3438 /* Configure PG(ETS) RX */
3439 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3443 /* Unpack CEE standard containers */
3444 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3445 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3446 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3447 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3448 /* Configure PG(ETS) TX */
3449 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3452 /*Configure queue statistics registers*/
3453 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3455 /* Check if the PFC is supported */
3456 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3457 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3458 for (i = 0; i < nb_tcs; i++) {
3460 * If the TC count is 8,and the default high_water is 48,
3461 * the low_water is 16 as default.
3463 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3464 hw->fc.low_water[i] = pbsize / 4;
3465 /* Enable pfc for this TC */
3466 tc = &dcb_config->tc_config[i];
3467 tc->pfc = ixgbe_dcb_pfc_enabled;
3469 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3470 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3472 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3479 * ixgbe_configure_dcb - Configure DCB Hardware
3480 * @dev: pointer to rte_eth_dev
3482 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3484 struct ixgbe_dcb_config *dcb_cfg =
3485 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3486 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3488 PMD_INIT_FUNC_TRACE();
3490 /* check support mq_mode for DCB */
3491 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3492 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3495 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3498 /** Configure DCB hardware **/
3499 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3505 * VMDq only support for 10 GbE NIC.
3508 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3510 struct rte_eth_vmdq_rx_conf *cfg;
3511 struct ixgbe_hw *hw;
3512 enum rte_eth_nb_pools num_pools;
3513 uint32_t mrqc, vt_ctl, vlanctrl;
3517 PMD_INIT_FUNC_TRACE();
3518 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3519 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3520 num_pools = cfg->nb_queue_pools;
3522 ixgbe_rss_disable(dev);
3524 /* MRQC: enable vmdq */
3525 mrqc = IXGBE_MRQC_VMDQEN;
3526 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3528 /* PFVTCTL: turn on virtualisation and set the default pool */
3529 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3530 if (cfg->enable_default_pool)
3531 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3533 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3535 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3537 for (i = 0; i < (int)num_pools; i++) {
3538 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
3539 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
3542 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3543 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3544 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3545 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3547 /* VFTA - enable all vlan filters */
3548 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3549 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3551 /* VFRE: pool enabling for receive - 64 */
3552 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3553 if (num_pools == ETH_64_POOLS)
3554 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3557 * MPSAR - allow pools to read specific mac addresses
3558 * In this case, all pools should be able to read from mac addr 0
3560 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3561 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3563 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3564 for (i = 0; i < cfg->nb_pool_maps; i++) {
3565 /* set vlan id in VF register and set the valid bit */
3566 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3567 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3569 * Put the allowed pools in VFB reg. As we only have 16 or 64
3570 * pools, we only need to use the first half of the register
3573 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3574 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3575 (cfg->pool_map[i].pools & UINT32_MAX));
3577 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3578 ((cfg->pool_map[i].pools >> 32) \
3583 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3584 if (cfg->enable_loop_back) {
3585 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3586 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3587 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3590 IXGBE_WRITE_FLUSH(hw);
3594 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3595 * @hw: pointer to hardware structure
3598 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3603 PMD_INIT_FUNC_TRACE();
3604 /*PF VF Transmit Enable*/
3605 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3606 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3608 /* Disable the Tx desc arbiter so that MTQC can be changed */
3609 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3610 reg |= IXGBE_RTTDCS_ARBDIS;
3611 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3613 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3614 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3616 /* Disable drop for all queues */
3617 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3618 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3619 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3621 /* Enable the Tx desc arbiter */
3622 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3623 reg &= ~IXGBE_RTTDCS_ARBDIS;
3624 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3626 IXGBE_WRITE_FLUSH(hw);
3631 static int __attribute__((cold))
3632 ixgbe_alloc_rx_queue_mbufs(struct ixgbe_rx_queue *rxq)
3634 struct ixgbe_rx_entry *rxe = rxq->sw_ring;
3638 /* Initialize software ring entries */
3639 for (i = 0; i < rxq->nb_rx_desc; i++) {
3640 volatile union ixgbe_adv_rx_desc *rxd;
3641 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3643 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
3644 (unsigned) rxq->queue_id);
3648 rte_mbuf_refcnt_set(mbuf, 1);
3650 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
3652 mbuf->port = rxq->port_id;
3655 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3656 rxd = &rxq->rx_ring[i];
3657 rxd->read.hdr_addr = dma_addr;
3658 rxd->read.pkt_addr = dma_addr;
3666 ixgbe_config_vf_rss(struct rte_eth_dev *dev)
3668 struct ixgbe_hw *hw;
3671 ixgbe_rss_configure(dev);
3673 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3675 /* MRQC: enable VF RSS */
3676 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
3677 mrqc &= ~IXGBE_MRQC_MRQE_MASK;
3678 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3680 mrqc |= IXGBE_MRQC_VMDQRSS64EN;
3684 mrqc |= IXGBE_MRQC_VMDQRSS32EN;
3688 PMD_INIT_LOG(ERR, "Invalid pool number in IOV mode with VMDQ RSS");
3692 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3698 ixgbe_config_vf_default(struct rte_eth_dev *dev)
3700 struct ixgbe_hw *hw =
3701 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3703 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3705 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3710 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3711 IXGBE_MRQC_VMDQRT4TCEN);
3715 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3716 IXGBE_MRQC_VMDQRT8TCEN);
3720 "invalid pool number in IOV mode");
3727 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3729 struct ixgbe_hw *hw =
3730 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3732 if (hw->mac.type == ixgbe_mac_82598EB)
3735 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3737 * SRIOV inactive scheme
3738 * any DCB/RSS w/o VMDq multi-queue setting
3740 switch (dev->data->dev_conf.rxmode.mq_mode) {
3742 ixgbe_rss_configure(dev);
3745 case ETH_MQ_RX_VMDQ_DCB:
3746 ixgbe_vmdq_dcb_configure(dev);
3749 case ETH_MQ_RX_VMDQ_ONLY:
3750 ixgbe_vmdq_rx_hw_configure(dev);
3753 case ETH_MQ_RX_NONE:
3754 /* if mq_mode is none, disable rss mode.*/
3755 default: ixgbe_rss_disable(dev);
3759 * SRIOV active scheme
3760 * Support RSS together with VMDq & SRIOV
3762 switch (dev->data->dev_conf.rxmode.mq_mode) {
3764 case ETH_MQ_RX_VMDQ_RSS:
3765 ixgbe_config_vf_rss(dev);
3768 /* FIXME if support DCB/RSS together with VMDq & SRIOV */
3769 case ETH_MQ_RX_VMDQ_DCB:
3770 case ETH_MQ_RX_VMDQ_DCB_RSS:
3772 "Could not support DCB with VMDq & SRIOV");
3775 ixgbe_config_vf_default(dev);
3784 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3786 struct ixgbe_hw *hw =
3787 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3791 if (hw->mac.type == ixgbe_mac_82598EB)
3794 /* disable arbiter before setting MTQC */
3795 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3796 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3797 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3799 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3801 * SRIOV inactive scheme
3802 * any DCB w/o VMDq multi-queue setting
3804 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3805 ixgbe_vmdq_tx_hw_configure(hw);
3807 mtqc = IXGBE_MTQC_64Q_1PB;
3808 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3811 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3814 * SRIOV active scheme
3815 * FIXME if support DCB together with VMDq & SRIOV
3818 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3821 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3824 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3828 mtqc = IXGBE_MTQC_64Q_1PB;
3829 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
3831 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3834 /* re-enable arbiter */
3835 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3836 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3842 * ixgbe_get_rscctl_maxdesc - Calculate the RSCCTL[n].MAXDESC for PF
3844 * Return the RSCCTL[n].MAXDESC for 82599 and x540 PF devices according to the
3845 * spec rev. 3.0 chapter 8.2.3.8.13.
3847 * @pool Memory pool of the Rx queue
3849 static inline uint32_t
3850 ixgbe_get_rscctl_maxdesc(struct rte_mempool *pool)
3852 struct rte_pktmbuf_pool_private *mp_priv = rte_mempool_get_priv(pool);
3854 /* MAXDESC * SRRCTL.BSIZEPKT must not exceed 64 KB minus one */
3857 (mp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM);
3860 return IXGBE_RSCCTL_MAXDESC_16;
3861 else if (maxdesc >= 8)
3862 return IXGBE_RSCCTL_MAXDESC_8;
3863 else if (maxdesc >= 4)
3864 return IXGBE_RSCCTL_MAXDESC_4;
3866 return IXGBE_RSCCTL_MAXDESC_1;
3870 * ixgbe_set_ivar - Setup the correct IVAR register for a particular MSIX
3873 * (Taken from FreeBSD tree)
3874 * (yes this is all very magic and confusing :)
3877 * @entry the register array entry
3878 * @vector the MSIX vector for this queue
3882 ixgbe_set_ivar(struct rte_eth_dev *dev, u8 entry, u8 vector, s8 type)
3884 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3887 vector |= IXGBE_IVAR_ALLOC_VAL;
3889 switch (hw->mac.type) {
3891 case ixgbe_mac_82598EB:
3893 entry = IXGBE_IVAR_OTHER_CAUSES_INDEX;
3895 entry += (type * 64);
3896 index = (entry >> 2) & 0x1F;
3897 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
3898 ivar &= ~(0xFF << (8 * (entry & 0x3)));
3899 ivar |= (vector << (8 * (entry & 0x3)));
3900 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
3903 case ixgbe_mac_82599EB:
3904 case ixgbe_mac_X540:
3905 if (type == -1) { /* MISC IVAR */
3906 index = (entry & 1) * 8;
3907 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
3908 ivar &= ~(0xFF << index);
3909 ivar |= (vector << index);
3910 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
3911 } else { /* RX/TX IVARS */
3912 index = (16 * (entry & 1)) + (8 * type);
3913 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1));
3914 ivar &= ~(0xFF << index);
3915 ivar |= (vector << index);
3916 IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar);
3926 void __attribute__((cold))
3927 ixgbe_set_rx_function(struct rte_eth_dev *dev)
3929 struct ixgbe_adapter *adapter =
3930 (struct ixgbe_adapter *)dev->data->dev_private;
3933 * In order to allow Vector Rx there are a few configuration
3934 * conditions to be met and Rx Bulk Allocation should be allowed.
3936 if (ixgbe_rx_vec_dev_conf_condition_check(dev) ||
3937 !adapter->rx_bulk_alloc_allowed) {
3938 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx "
3939 "preconditions or RTE_IXGBE_INC_VECTOR is "
3941 dev->data->port_id);
3943 adapter->rx_vec_allowed = false;
3947 * Initialize the appropriate LRO callback.
3949 * If all queues satisfy the bulk allocation preconditions
3950 * (hw->rx_bulk_alloc_allowed is TRUE) then we may use bulk allocation.
3951 * Otherwise use a single allocation version.
3953 if (dev->data->lro) {
3954 if (adapter->rx_bulk_alloc_allowed) {
3955 PMD_INIT_LOG(INFO, "LRO is requested. Using a bulk "
3956 "allocation version");
3957 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
3959 PMD_INIT_LOG(INFO, "LRO is requested. Using a single "
3960 "allocation version");
3961 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
3963 } else if (dev->data->scattered_rx) {
3965 * Set the non-LRO scattered callback: there are Vector and
3966 * single allocation versions.
3968 if (adapter->rx_vec_allowed) {
3969 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
3970 "callback (port=%d).",
3971 dev->data->port_id);
3973 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3974 } else if (adapter->rx_bulk_alloc_allowed) {
3975 PMD_INIT_LOG(INFO, "Using a Scattered with bulk "
3976 "allocation callback (port=%d).",
3977 dev->data->port_id);
3978 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
3980 PMD_INIT_LOG(DEBUG, "Using Regualr (non-vector, "
3981 "single allocation) "
3982 "Scattered Rx callback "
3984 dev->data->port_id);
3986 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
3989 * Below we set "simple" callbacks according to port/queues parameters.
3990 * If parameters allow we are going to choose between the following
3994 * - Single buffer allocation (the simplest one)
3996 } else if (adapter->rx_vec_allowed) {
3997 PMD_INIT_LOG(INFO, "Vector rx enabled, please make sure RX "
3998 "burst size no less than 32.");
4000 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
4001 } else if (adapter->rx_bulk_alloc_allowed) {
4002 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
4003 "satisfied. Rx Burst Bulk Alloc function "
4004 "will be used on port=%d.",
4005 dev->data->port_id);
4007 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
4009 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
4010 "satisfied, or Scattered Rx is requested, "
4011 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC "
4012 "is not enabled (port=%d).",
4013 dev->data->port_id);
4015 dev->rx_pkt_burst = ixgbe_recv_pkts;
4020 * ixgbe_set_rsc - configure RSC related port HW registers
4022 * Configures the port's RSC related registers according to the 4.6.7.2 chapter
4023 * of 82599 Spec (x540 configuration is virtually the same).
4027 * Returns 0 in case of success or a non-zero error code
4030 ixgbe_set_rsc(struct rte_eth_dev *dev)
4032 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4033 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4034 struct rte_eth_dev_info dev_info = { 0 };
4035 bool rsc_capable = false;
4040 dev->dev_ops->dev_infos_get(dev, &dev_info);
4041 if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_TCP_LRO)
4044 if (!rsc_capable && rx_conf->enable_lro) {
4045 PMD_INIT_LOG(CRIT, "LRO is requested on HW that doesn't "
4050 /* RSC global configuration (chapter 4.6.7.2.1 of 82599 Spec) */
4052 if (!rx_conf->hw_strip_crc && rx_conf->enable_lro) {
4054 * According to chapter of 4.6.7.2.1 of the Spec Rev.
4055 * 3.0 RSC configuration requires HW CRC stripping being
4056 * enabled. If user requested both HW CRC stripping off
4057 * and RSC on - return an error.
4059 PMD_INIT_LOG(CRIT, "LRO can't be enabled when HW CRC "
4064 /* RFCTL configuration */
4066 uint32_t rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4067 if (rx_conf->enable_lro)
4069 * Since NFS packets coalescing is not supported - clear
4070 * RFCTL.NFSW_DIS and RFCTL.NFSR_DIS when RSC is
4073 rfctl &= ~(IXGBE_RFCTL_RSC_DIS | IXGBE_RFCTL_NFSW_DIS |
4074 IXGBE_RFCTL_NFSR_DIS);
4076 rfctl |= IXGBE_RFCTL_RSC_DIS;
4078 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4081 /* If LRO hasn't been requested - we are done here. */
4082 if (!rx_conf->enable_lro)
4085 /* Set RDRXCTL.RSCACKC bit */
4086 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4087 rdrxctl |= IXGBE_RDRXCTL_RSCACKC;
4088 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4090 /* Per-queue RSC configuration (chapter 4.6.7.2.2 of 82599 Spec) */
4091 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4092 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4094 IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxq->reg_idx));
4096 IXGBE_READ_REG(hw, IXGBE_RSCCTL(rxq->reg_idx));
4098 IXGBE_READ_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx));
4100 IXGBE_READ_REG(hw, IXGBE_EITR(rxq->reg_idx));
4103 * ixgbe PMD doesn't support header-split at the moment.
4105 * Following the 4.6.7.2.1 chapter of the 82599/x540
4106 * Spec if RSC is enabled the SRRCTL[n].BSIZEHEADER
4107 * should be configured even if header split is not
4108 * enabled. We will configure it 128 bytes following the
4109 * recommendation in the spec.
4111 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
4112 srrctl |= (128 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4113 IXGBE_SRRCTL_BSIZEHDR_MASK;
4116 * TODO: Consider setting the Receive Descriptor Minimum
4117 * Threshold Size for an RSC case. This is not an obviously
4118 * beneficiary option but the one worth considering...
4121 rscctl |= IXGBE_RSCCTL_RSCEN;
4122 rscctl |= ixgbe_get_rscctl_maxdesc(rxq->mb_pool);
4123 psrtype |= IXGBE_PSRTYPE_TCPHDR;
4126 * RSC: Set ITR interval corresponding to 2K ints/s.
4128 * Full-sized RSC aggregations for a 10Gb/s link will
4129 * arrive at about 20K aggregation/s rate.
4131 * 2K inst/s rate will make only 10% of the
4132 * aggregations to be closed due to the interrupt timer
4133 * expiration for a streaming at wire-speed case.
4135 * For a sparse streaming case this setting will yield
4136 * at most 500us latency for a single RSC aggregation.
4138 eitr &= ~IXGBE_EITR_ITR_INT_MASK;
4139 eitr |= IXGBE_EITR_INTERVAL_US(500) | IXGBE_EITR_CNT_WDIS;
4141 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4142 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(rxq->reg_idx), rscctl);
4143 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
4144 IXGBE_WRITE_REG(hw, IXGBE_EITR(rxq->reg_idx), eitr);
4147 * RSC requires the mapping of the queue to the
4150 ixgbe_set_ivar(dev, rxq->reg_idx, i, 0);
4155 PMD_INIT_LOG(INFO, "enabling LRO mode");
4161 * Initializes Receive Unit.
4163 int __attribute__((cold))
4164 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
4166 struct ixgbe_hw *hw;
4167 struct ixgbe_rx_queue *rxq;
4178 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4181 PMD_INIT_FUNC_TRACE();
4182 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4185 * Make sure receives are disabled while setting
4186 * up the RX context (registers, descriptor rings, etc.).
4188 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4189 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4191 /* Enable receipt of broadcasted frames */
4192 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4193 fctrl |= IXGBE_FCTRL_BAM;
4194 fctrl |= IXGBE_FCTRL_DPF;
4195 fctrl |= IXGBE_FCTRL_PMCF;
4196 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4199 * Configure CRC stripping, if any.
4201 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4202 if (rx_conf->hw_strip_crc)
4203 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
4205 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
4208 * Configure jumbo frame support, if any.
4210 if (rx_conf->jumbo_frame == 1) {
4211 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4212 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4213 maxfrs &= 0x0000FFFF;
4214 maxfrs |= (rx_conf->max_rx_pkt_len << 16);
4215 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4217 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4220 * If loopback mode is configured for 82599, set LPBK bit.
4222 if (hw->mac.type == ixgbe_mac_82599EB &&
4223 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
4224 hlreg0 |= IXGBE_HLREG0_LPBK;
4226 hlreg0 &= ~IXGBE_HLREG0_LPBK;
4228 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4230 /* Setup RX queues */
4231 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4232 rxq = dev->data->rx_queues[i];
4235 * Reset crc_len in case it was changed after queue setup by a
4236 * call to configure.
4238 rxq->crc_len = rx_conf->hw_strip_crc ? 0 : ETHER_CRC_LEN;
4240 /* Setup the Base and Length of the Rx Descriptor Rings */
4241 bus_addr = rxq->rx_ring_phys_addr;
4242 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
4243 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4244 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
4245 (uint32_t)(bus_addr >> 32));
4246 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
4247 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4248 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
4249 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
4251 /* Configure the SRRCTL register */
4252 #ifdef RTE_HEADER_SPLIT_ENABLE
4254 * Configure Header Split
4256 if (rx_conf->header_split) {
4257 if (hw->mac.type == ixgbe_mac_82599EB) {
4258 /* Must setup the PSRTYPE register */
4260 psrtype = IXGBE_PSRTYPE_TCPHDR |
4261 IXGBE_PSRTYPE_UDPHDR |
4262 IXGBE_PSRTYPE_IPV4HDR |
4263 IXGBE_PSRTYPE_IPV6HDR;
4264 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
4266 srrctl = ((rx_conf->split_hdr_size <<
4267 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4268 IXGBE_SRRCTL_BSIZEHDR_MASK);
4269 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4272 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4274 /* Set if packets are dropped when no descriptors available */
4276 srrctl |= IXGBE_SRRCTL_DROP_EN;
4279 * Configure the RX buffer size in the BSIZEPACKET field of
4280 * the SRRCTL register of the queue.
4281 * The value is in 1 KB resolution. Valid values can be from
4284 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
4285 RTE_PKTMBUF_HEADROOM);
4286 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4287 IXGBE_SRRCTL_BSIZEPKT_MASK);
4289 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4291 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4292 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4294 /* It adds dual VLAN length for supporting dual VLAN */
4295 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4296 2 * IXGBE_VLAN_TAG_SIZE > buf_size)
4297 dev->data->scattered_rx = 1;
4300 if (rx_conf->enable_scatter)
4301 dev->data->scattered_rx = 1;
4304 * Device configured with multiple RX queues.
4306 ixgbe_dev_mq_rx_configure(dev);
4309 * Setup the Checksum Register.
4310 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
4311 * Enable IP/L4 checkum computation by hardware if requested to do so.
4313 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
4314 rxcsum |= IXGBE_RXCSUM_PCSD;
4315 if (rx_conf->hw_ip_checksum)
4316 rxcsum |= IXGBE_RXCSUM_IPPCSE;
4318 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
4320 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
4322 if (hw->mac.type == ixgbe_mac_82599EB ||
4323 hw->mac.type == ixgbe_mac_X540) {
4324 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4325 if (rx_conf->hw_strip_crc)
4326 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4328 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
4329 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4330 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4333 rc = ixgbe_set_rsc(dev);
4337 ixgbe_set_rx_function(dev);
4343 * Initializes Transmit Unit.
4345 void __attribute__((cold))
4346 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
4348 struct ixgbe_hw *hw;
4349 struct ixgbe_tx_queue *txq;
4355 PMD_INIT_FUNC_TRACE();
4356 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4358 /* Enable TX CRC (checksum offload requirement) and hw padding
4359 * (TSO requirement) */
4360 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4361 hlreg0 |= (IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);
4362 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4364 /* Setup the Base and Length of the Tx Descriptor Rings */
4365 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4366 txq = dev->data->tx_queues[i];
4368 bus_addr = txq->tx_ring_phys_addr;
4369 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
4370 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4371 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
4372 (uint32_t)(bus_addr >> 32));
4373 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
4374 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4375 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4376 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
4377 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
4380 * Disable Tx Head Writeback RO bit, since this hoses
4381 * bookkeeping if things aren't delivered in order.
4383 switch (hw->mac.type) {
4384 case ixgbe_mac_82598EB:
4385 txctrl = IXGBE_READ_REG(hw,
4386 IXGBE_DCA_TXCTRL(txq->reg_idx));
4387 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4388 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
4392 case ixgbe_mac_82599EB:
4393 case ixgbe_mac_X540:
4394 case ixgbe_mac_X550:
4395 case ixgbe_mac_X550EM_x:
4397 txctrl = IXGBE_READ_REG(hw,
4398 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
4399 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4400 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
4406 /* Device configured with multiple TX queues. */
4407 ixgbe_dev_mq_tx_configure(dev);
4411 * Set up link for 82599 loopback mode Tx->Rx.
4413 static inline void __attribute__((cold))
4414 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
4416 PMD_INIT_FUNC_TRACE();
4418 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
4419 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
4421 PMD_INIT_LOG(ERR, "Could not enable loopback mode");
4430 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
4431 ixgbe_reset_pipeline_82599(hw);
4433 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
4439 * Start Transmit and Receive Units.
4441 int __attribute__((cold))
4442 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
4444 struct ixgbe_hw *hw;
4445 struct ixgbe_tx_queue *txq;
4446 struct ixgbe_rx_queue *rxq;
4453 PMD_INIT_FUNC_TRACE();
4454 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4456 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4457 txq = dev->data->tx_queues[i];
4458 /* Setup Transmit Threshold Registers */
4459 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4460 txdctl |= txq->pthresh & 0x7F;
4461 txdctl |= ((txq->hthresh & 0x7F) << 8);
4462 txdctl |= ((txq->wthresh & 0x7F) << 16);
4463 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4466 if (hw->mac.type != ixgbe_mac_82598EB) {
4467 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
4468 dmatxctl |= IXGBE_DMATXCTL_TE;
4469 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
4472 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4473 txq = dev->data->tx_queues[i];
4474 if (!txq->tx_deferred_start) {
4475 ret = ixgbe_dev_tx_queue_start(dev, i);
4481 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4482 rxq = dev->data->rx_queues[i];
4483 if (!rxq->rx_deferred_start) {
4484 ret = ixgbe_dev_rx_queue_start(dev, i);
4490 /* Enable Receive engine */
4491 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4492 if (hw->mac.type == ixgbe_mac_82598EB)
4493 rxctrl |= IXGBE_RXCTRL_DMBYPS;
4494 rxctrl |= IXGBE_RXCTRL_RXEN;
4495 hw->mac.ops.enable_rx_dma(hw, rxctrl);
4497 /* If loopback mode is enabled for 82599, set up the link accordingly */
4498 if (hw->mac.type == ixgbe_mac_82599EB &&
4499 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
4500 ixgbe_setup_loopback_link_82599(hw);
4506 * Start Receive Units for specified queue.
4508 int __attribute__((cold))
4509 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4511 struct ixgbe_hw *hw;
4512 struct ixgbe_rx_queue *rxq;
4516 PMD_INIT_FUNC_TRACE();
4517 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4519 if (rx_queue_id < dev->data->nb_rx_queues) {
4520 rxq = dev->data->rx_queues[rx_queue_id];
4522 /* Allocate buffers for descriptor rings */
4523 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
4524 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
4528 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4529 rxdctl |= IXGBE_RXDCTL_ENABLE;
4530 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
4532 /* Wait until RX Enable ready */
4533 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4536 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4537 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4539 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d",
4542 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
4543 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
4551 * Stop Receive Units for specified queue.
4553 int __attribute__((cold))
4554 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4556 struct ixgbe_hw *hw;
4557 struct ixgbe_adapter *adapter =
4558 (struct ixgbe_adapter *)dev->data->dev_private;
4559 struct ixgbe_rx_queue *rxq;
4563 PMD_INIT_FUNC_TRACE();
4564 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4566 if (rx_queue_id < dev->data->nb_rx_queues) {
4567 rxq = dev->data->rx_queues[rx_queue_id];
4569 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4570 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
4571 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
4573 /* Wait until RX Enable ready */
4574 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4577 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4578 } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));
4580 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d",
4583 rte_delay_us(RTE_IXGBE_WAIT_100_US);
4585 ixgbe_rx_queue_release_mbufs(rxq);
4586 ixgbe_reset_rx_queue(adapter, rxq);
4595 * Start Transmit Units for specified queue.
4597 int __attribute__((cold))
4598 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4600 struct ixgbe_hw *hw;
4601 struct ixgbe_tx_queue *txq;
4605 PMD_INIT_FUNC_TRACE();
4606 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4608 if (tx_queue_id < dev->data->nb_tx_queues) {
4609 txq = dev->data->tx_queues[tx_queue_id];
4610 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4611 txdctl |= IXGBE_TXDCTL_ENABLE;
4612 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4614 /* Wait until TX Enable ready */
4615 if (hw->mac.type == ixgbe_mac_82599EB) {
4616 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4619 txdctl = IXGBE_READ_REG(hw,
4620 IXGBE_TXDCTL(txq->reg_idx));
4621 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4623 PMD_INIT_LOG(ERR, "Could not enable "
4624 "Tx Queue %d", tx_queue_id);
4627 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
4628 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
4636 * Stop Transmit Units for specified queue.
4638 int __attribute__((cold))
4639 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4641 struct ixgbe_hw *hw;
4642 struct ixgbe_tx_queue *txq;
4644 uint32_t txtdh, txtdt;
4647 PMD_INIT_FUNC_TRACE();
4648 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4650 if (tx_queue_id < dev->data->nb_tx_queues) {
4651 txq = dev->data->tx_queues[tx_queue_id];
4653 /* Wait until TX queue is empty */
4654 if (hw->mac.type == ixgbe_mac_82599EB) {
4655 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4657 rte_delay_us(RTE_IXGBE_WAIT_100_US);
4658 txtdh = IXGBE_READ_REG(hw,
4659 IXGBE_TDH(txq->reg_idx));
4660 txtdt = IXGBE_READ_REG(hw,
4661 IXGBE_TDT(txq->reg_idx));
4662 } while (--poll_ms && (txtdh != txtdt));
4664 PMD_INIT_LOG(ERR, "Tx Queue %d is not empty "
4665 "when stopping.", tx_queue_id);
4668 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4669 txdctl &= ~IXGBE_TXDCTL_ENABLE;
4670 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4672 /* Wait until TX Enable ready */
4673 if (hw->mac.type == ixgbe_mac_82599EB) {
4674 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4677 txdctl = IXGBE_READ_REG(hw,
4678 IXGBE_TXDCTL(txq->reg_idx));
4679 } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));
4681 PMD_INIT_LOG(ERR, "Could not disable "
4682 "Tx Queue %d", tx_queue_id);
4685 if (txq->ops != NULL) {
4686 txq->ops->release_mbufs(txq);
4687 txq->ops->reset(txq);
4696 * [VF] Initializes Receive Unit.
4698 int __attribute__((cold))
4699 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
4701 struct ixgbe_hw *hw;
4702 struct ixgbe_rx_queue *rxq;
4704 uint32_t srrctl, psrtype = 0;
4709 PMD_INIT_FUNC_TRACE();
4710 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4712 if (rte_is_power_of_2(dev->data->nb_rx_queues) == 0) {
4713 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4714 "it should be power of 2");
4718 if (dev->data->nb_rx_queues > hw->mac.max_rx_queues) {
4719 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4720 "it should be equal to or less than %d",
4721 hw->mac.max_rx_queues);
4726 * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
4727 * disables the VF receipt of packets if the PF MTU is > 1500.
4728 * This is done to deal with 82599 limitations that imposes
4729 * the PF and all VFs to share the same MTU.
4730 * Then, the PF driver enables again the VF receipt of packet when
4731 * the VF driver issues a IXGBE_VF_SET_LPE request.
4732 * In the meantime, the VF device cannot be used, even if the VF driver
4733 * and the Guest VM network stack are ready to accept packets with a
4734 * size up to the PF MTU.
4735 * As a work-around to this PF behaviour, force the call to
4736 * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
4737 * VF packets received can work in all cases.
4739 ixgbevf_rlpml_set_vf(hw,
4740 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
4742 /* Setup RX queues */
4743 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4744 rxq = dev->data->rx_queues[i];
4746 /* Allocate buffers for descriptor rings */
4747 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
4751 /* Setup the Base and Length of the Rx Descriptor Rings */
4752 bus_addr = rxq->rx_ring_phys_addr;
4754 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
4755 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4756 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
4757 (uint32_t)(bus_addr >> 32));
4758 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
4759 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4760 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
4761 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
4764 /* Configure the SRRCTL register */
4765 #ifdef RTE_HEADER_SPLIT_ENABLE
4767 * Configure Header Split
4769 if (dev->data->dev_conf.rxmode.header_split) {
4770 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
4771 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4772 IXGBE_SRRCTL_BSIZEHDR_MASK);
4773 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4776 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4778 /* Set if packets are dropped when no descriptors available */
4780 srrctl |= IXGBE_SRRCTL_DROP_EN;
4783 * Configure the RX buffer size in the BSIZEPACKET field of
4784 * the SRRCTL register of the queue.
4785 * The value is in 1 KB resolution. Valid values can be from
4788 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
4789 RTE_PKTMBUF_HEADROOM);
4790 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4791 IXGBE_SRRCTL_BSIZEPKT_MASK);
4794 * VF modification to write virtual function SRRCTL register
4796 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
4798 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4799 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4801 if (dev->data->dev_conf.rxmode.enable_scatter ||
4802 /* It adds dual VLAN length for supporting dual VLAN */
4803 (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4804 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
4805 if (!dev->data->scattered_rx)
4806 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
4807 dev->data->scattered_rx = 1;
4811 #ifdef RTE_HEADER_SPLIT_ENABLE
4812 if (dev->data->dev_conf.rxmode.header_split)
4813 /* Must setup the PSRTYPE register */
4814 psrtype = IXGBE_PSRTYPE_TCPHDR |
4815 IXGBE_PSRTYPE_UDPHDR |
4816 IXGBE_PSRTYPE_IPV4HDR |
4817 IXGBE_PSRTYPE_IPV6HDR;
4820 /* Set RQPL for VF RSS according to max Rx queue */
4821 psrtype |= (dev->data->nb_rx_queues >> 1) <<
4822 IXGBE_PSRTYPE_RQPL_SHIFT;
4823 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
4825 ixgbe_set_rx_function(dev);
4831 * [VF] Initializes Transmit Unit.
4833 void __attribute__((cold))
4834 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
4836 struct ixgbe_hw *hw;
4837 struct ixgbe_tx_queue *txq;
4842 PMD_INIT_FUNC_TRACE();
4843 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4845 /* Setup the Base and Length of the Tx Descriptor Rings */
4846 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4847 txq = dev->data->tx_queues[i];
4848 bus_addr = txq->tx_ring_phys_addr;
4849 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
4850 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4851 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
4852 (uint32_t)(bus_addr >> 32));
4853 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
4854 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4855 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4856 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
4857 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
4860 * Disable Tx Head Writeback RO bit, since this hoses
4861 * bookkeeping if things aren't delivered in order.
4863 txctrl = IXGBE_READ_REG(hw,
4864 IXGBE_VFDCA_TXCTRL(i));
4865 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4866 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
4872 * [VF] Start Transmit and Receive Units.
4874 void __attribute__((cold))
4875 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
4877 struct ixgbe_hw *hw;
4878 struct ixgbe_tx_queue *txq;
4879 struct ixgbe_rx_queue *rxq;
4885 PMD_INIT_FUNC_TRACE();
4886 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4888 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4889 txq = dev->data->tx_queues[i];
4890 /* Setup Transmit Threshold Registers */
4891 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4892 txdctl |= txq->pthresh & 0x7F;
4893 txdctl |= ((txq->hthresh & 0x7F) << 8);
4894 txdctl |= ((txq->wthresh & 0x7F) << 16);
4895 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4898 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4900 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4901 txdctl |= IXGBE_TXDCTL_ENABLE;
4902 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4905 /* Wait until TX Enable ready */
4908 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4909 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4911 PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
4913 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4915 rxq = dev->data->rx_queues[i];
4917 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4918 rxdctl |= IXGBE_RXDCTL_ENABLE;
4919 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
4921 /* Wait until RX Enable ready */
4925 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4926 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4928 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
4930 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);
4935 /* Stubs needed for linkage when CONFIG_RTE_IXGBE_INC_VECTOR is set to 'n' */
4936 int __attribute__((weak))
4937 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
4942 uint16_t __attribute__((weak))
4943 ixgbe_recv_pkts_vec(
4944 void __rte_unused *rx_queue,
4945 struct rte_mbuf __rte_unused **rx_pkts,
4946 uint16_t __rte_unused nb_pkts)
4951 uint16_t __attribute__((weak))
4952 ixgbe_recv_scattered_pkts_vec(
4953 void __rte_unused *rx_queue,
4954 struct rte_mbuf __rte_unused **rx_pkts,
4955 uint16_t __rte_unused nb_pkts)
4960 int __attribute__((weak))
4961 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue __rte_unused *rxq)