1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation.
3 * Copyright 2014 6WIND S.A.
17 #include <rte_byteorder.h>
18 #include <rte_common.h>
19 #include <rte_cycles.h>
21 #include <rte_debug.h>
22 #include <rte_interrupts.h>
24 #include <rte_memory.h>
25 #include <rte_memzone.h>
26 #include <rte_launch.h>
28 #include <rte_per_lcore.h>
29 #include <rte_lcore.h>
30 #include <rte_atomic.h>
31 #include <rte_branch_prediction.h>
32 #include <rte_mempool.h>
33 #include <rte_malloc.h>
35 #include <rte_ether.h>
36 #include <rte_ethdev_driver.h>
37 #include <rte_prefetch.h>
41 #include <rte_string_fns.h>
42 #include <rte_errno.h>
46 #include "ixgbe_logs.h"
47 #include "base/ixgbe_api.h"
48 #include "base/ixgbe_vf.h"
49 #include "ixgbe_ethdev.h"
50 #include "base/ixgbe_dcb.h"
51 #include "base/ixgbe_common.h"
52 #include "ixgbe_rxtx.h"
54 #ifdef RTE_LIBRTE_IEEE1588
55 #define IXGBE_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
57 #define IXGBE_TX_IEEE1588_TMST 0
59 /* Bit Mask to indicate what bits required for building TX context */
60 #define IXGBE_TX_OFFLOAD_MASK ( \
66 PKT_TX_OUTER_IP_CKSUM | \
67 PKT_TX_SEC_OFFLOAD | \
68 IXGBE_TX_IEEE1588_TMST)
70 #define IXGBE_TX_OFFLOAD_NOTSUP_MASK \
71 (PKT_TX_OFFLOAD_MASK ^ IXGBE_TX_OFFLOAD_MASK)
74 #define RTE_PMD_USE_PREFETCH
77 #ifdef RTE_PMD_USE_PREFETCH
79 * Prefetch a cache line into all cache levels.
81 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
83 #define rte_ixgbe_prefetch(p) do {} while (0)
86 #ifdef RTE_IXGBE_INC_VECTOR
87 uint16_t ixgbe_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
91 /*********************************************************************
95 **********************************************************************/
98 * Check for descriptors with their DD bit set and free mbufs.
99 * Return the total number of buffers freed.
101 static __rte_always_inline int
102 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
104 struct ixgbe_tx_entry *txep;
107 struct rte_mbuf *m, *free[RTE_IXGBE_TX_MAX_FREE_BUF_SZ];
109 /* check DD bit on threshold descriptor */
110 status = txq->tx_ring[txq->tx_next_dd].wb.status;
111 if (!(status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD)))
115 * first buffer to free from S/W ring is at index
116 * tx_next_dd - (tx_rs_thresh-1)
118 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
120 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
121 /* free buffers one at a time */
122 m = rte_pktmbuf_prefree_seg(txep->mbuf);
125 if (unlikely(m == NULL))
128 if (nb_free >= RTE_IXGBE_TX_MAX_FREE_BUF_SZ ||
129 (nb_free > 0 && m->pool != free[0]->pool)) {
130 rte_mempool_put_bulk(free[0]->pool,
131 (void **)free, nb_free);
139 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
141 /* buffers were freed, update counters */
142 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
143 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
144 if (txq->tx_next_dd >= txq->nb_tx_desc)
145 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
147 return txq->tx_rs_thresh;
150 /* Populate 4 descriptors with data from 4 mbufs */
152 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
154 uint64_t buf_dma_addr;
158 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
159 buf_dma_addr = rte_mbuf_data_iova(*pkts);
160 pkt_len = (*pkts)->data_len;
162 /* write data to descriptor */
163 txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
165 txdp->read.cmd_type_len =
166 rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
168 txdp->read.olinfo_status =
169 rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
171 rte_prefetch0(&(*pkts)->pool);
175 /* Populate 1 descriptor with data from 1 mbuf */
177 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
179 uint64_t buf_dma_addr;
182 buf_dma_addr = rte_mbuf_data_iova(*pkts);
183 pkt_len = (*pkts)->data_len;
185 /* write data to descriptor */
186 txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
187 txdp->read.cmd_type_len =
188 rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
189 txdp->read.olinfo_status =
190 rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
191 rte_prefetch0(&(*pkts)->pool);
195 * Fill H/W descriptor ring with mbuf data.
196 * Copy mbuf pointers to the S/W ring.
199 ixgbe_tx_fill_hw_ring(struct ixgbe_tx_queue *txq, struct rte_mbuf **pkts,
202 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
203 struct ixgbe_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
204 const int N_PER_LOOP = 4;
205 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
206 int mainpart, leftover;
210 * Process most of the packets in chunks of N pkts. Any
211 * leftover packets will get processed one at a time.
213 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
214 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
215 for (i = 0; i < mainpart; i += N_PER_LOOP) {
216 /* Copy N mbuf pointers to the S/W ring */
217 for (j = 0; j < N_PER_LOOP; ++j) {
218 (txep + i + j)->mbuf = *(pkts + i + j);
220 tx4(txdp + i, pkts + i);
223 if (unlikely(leftover > 0)) {
224 for (i = 0; i < leftover; ++i) {
225 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
226 tx1(txdp + mainpart + i, pkts + mainpart + i);
231 static inline uint16_t
232 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
235 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
236 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
240 * Begin scanning the H/W ring for done descriptors when the
241 * number of available descriptors drops below tx_free_thresh. For
242 * each done descriptor, free the associated buffer.
244 if (txq->nb_tx_free < txq->tx_free_thresh)
245 ixgbe_tx_free_bufs(txq);
247 /* Only use descriptors that are available */
248 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
249 if (unlikely(nb_pkts == 0))
252 /* Use exactly nb_pkts descriptors */
253 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
256 * At this point, we know there are enough descriptors in the
257 * ring to transmit all the packets. This assumes that each
258 * mbuf contains a single segment, and that no new offloads
259 * are expected, which would require a new context descriptor.
263 * See if we're going to wrap-around. If so, handle the top
264 * of the descriptor ring first, then do the bottom. If not,
265 * the processing looks just like the "bottom" part anyway...
267 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
268 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
269 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
272 * We know that the last descriptor in the ring will need to
273 * have its RS bit set because tx_rs_thresh has to be
274 * a divisor of the ring size
276 tx_r[txq->tx_next_rs].read.cmd_type_len |=
277 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
278 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
283 /* Fill H/W descriptor ring with mbuf data */
284 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
285 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
288 * Determine if RS bit should be set
289 * This is what we actually want:
290 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
291 * but instead of subtracting 1 and doing >=, we can just do
292 * greater than without subtracting.
294 if (txq->tx_tail > txq->tx_next_rs) {
295 tx_r[txq->tx_next_rs].read.cmd_type_len |=
296 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
297 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
299 if (txq->tx_next_rs >= txq->nb_tx_desc)
300 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
304 * Check for wrap-around. This would only happen if we used
305 * up to the last descriptor in the ring, no more, no less.
307 if (txq->tx_tail >= txq->nb_tx_desc)
310 /* update tail pointer */
312 IXGBE_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, txq->tx_tail);
318 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
323 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
324 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
325 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
327 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
332 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
333 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
334 nb_tx = (uint16_t)(nb_tx + ret);
335 nb_pkts = (uint16_t)(nb_pkts - ret);
343 #ifdef RTE_IXGBE_INC_VECTOR
345 ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
349 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
354 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
355 ret = ixgbe_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
368 ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,
369 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
370 uint64_t ol_flags, union ixgbe_tx_offload tx_offload,
371 __rte_unused uint64_t *mdata)
373 uint32_t type_tucmd_mlhl;
374 uint32_t mss_l4len_idx = 0;
376 uint32_t vlan_macip_lens;
377 union ixgbe_tx_offload tx_offload_mask;
378 uint32_t seqnum_seed = 0;
380 ctx_idx = txq->ctx_curr;
381 tx_offload_mask.data[0] = 0;
382 tx_offload_mask.data[1] = 0;
385 /* Specify which HW CTX to upload. */
386 mss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
388 if (ol_flags & PKT_TX_VLAN_PKT) {
389 tx_offload_mask.vlan_tci |= ~0;
392 /* check if TCP segmentation required for this packet */
393 if (ol_flags & PKT_TX_TCP_SEG) {
394 /* implies IP cksum in IPv4 */
395 if (ol_flags & PKT_TX_IP_CKSUM)
396 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |
397 IXGBE_ADVTXD_TUCMD_L4T_TCP |
398 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
400 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV6 |
401 IXGBE_ADVTXD_TUCMD_L4T_TCP |
402 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
404 tx_offload_mask.l2_len |= ~0;
405 tx_offload_mask.l3_len |= ~0;
406 tx_offload_mask.l4_len |= ~0;
407 tx_offload_mask.tso_segsz |= ~0;
408 mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
409 mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;
410 } else { /* no TSO, check if hardware checksum is needed */
411 if (ol_flags & PKT_TX_IP_CKSUM) {
412 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
413 tx_offload_mask.l2_len |= ~0;
414 tx_offload_mask.l3_len |= ~0;
417 switch (ol_flags & PKT_TX_L4_MASK) {
418 case PKT_TX_UDP_CKSUM:
419 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
420 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
421 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
422 tx_offload_mask.l2_len |= ~0;
423 tx_offload_mask.l3_len |= ~0;
425 case PKT_TX_TCP_CKSUM:
426 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
427 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
428 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
429 tx_offload_mask.l2_len |= ~0;
430 tx_offload_mask.l3_len |= ~0;
432 case PKT_TX_SCTP_CKSUM:
433 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
434 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
435 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
436 tx_offload_mask.l2_len |= ~0;
437 tx_offload_mask.l3_len |= ~0;
440 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
441 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
446 if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
447 tx_offload_mask.outer_l2_len |= ~0;
448 tx_offload_mask.outer_l3_len |= ~0;
449 tx_offload_mask.l2_len |= ~0;
450 seqnum_seed |= tx_offload.outer_l3_len
451 << IXGBE_ADVTXD_OUTER_IPLEN;
452 seqnum_seed |= tx_offload.l2_len
453 << IXGBE_ADVTXD_TUNNEL_LEN;
455 #ifdef RTE_LIBRTE_SECURITY
456 if (ol_flags & PKT_TX_SEC_OFFLOAD) {
457 union ixgbe_crypto_tx_desc_md *md =
458 (union ixgbe_crypto_tx_desc_md *)mdata;
460 (IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK & md->sa_idx);
461 type_tucmd_mlhl |= md->enc ?
462 (IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP |
463 IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN) : 0;
465 (md->pad_len & IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK);
466 tx_offload_mask.sa_idx |= ~0;
467 tx_offload_mask.sec_pad_len |= ~0;
471 txq->ctx_cache[ctx_idx].flags = ol_flags;
472 txq->ctx_cache[ctx_idx].tx_offload.data[0] =
473 tx_offload_mask.data[0] & tx_offload.data[0];
474 txq->ctx_cache[ctx_idx].tx_offload.data[1] =
475 tx_offload_mask.data[1] & tx_offload.data[1];
476 txq->ctx_cache[ctx_idx].tx_offload_mask = tx_offload_mask;
478 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
479 vlan_macip_lens = tx_offload.l3_len;
480 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
481 vlan_macip_lens |= (tx_offload.outer_l2_len <<
482 IXGBE_ADVTXD_MACLEN_SHIFT);
484 vlan_macip_lens |= (tx_offload.l2_len <<
485 IXGBE_ADVTXD_MACLEN_SHIFT);
486 vlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);
487 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
488 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
489 ctx_txd->seqnum_seed = seqnum_seed;
493 * Check which hardware context can be used. Use the existing match
494 * or create a new context descriptor.
496 static inline uint32_t
497 what_advctx_update(struct ixgbe_tx_queue *txq, uint64_t flags,
498 union ixgbe_tx_offload tx_offload)
500 /* If match with the current used context */
501 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
502 (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] ==
503 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0]
504 & tx_offload.data[0])) &&
505 (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] ==
506 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1]
507 & tx_offload.data[1]))))
508 return txq->ctx_curr;
510 /* What if match with the next context */
512 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
513 (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] ==
514 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0]
515 & tx_offload.data[0])) &&
516 (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] ==
517 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1]
518 & tx_offload.data[1]))))
519 return txq->ctx_curr;
521 /* Mismatch, use the previous context */
522 return IXGBE_CTX_NUM;
525 static inline uint32_t
526 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
530 if ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM)
531 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
532 if (ol_flags & PKT_TX_IP_CKSUM)
533 tmp |= IXGBE_ADVTXD_POPTS_IXSM;
534 if (ol_flags & PKT_TX_TCP_SEG)
535 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
539 static inline uint32_t
540 tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)
542 uint32_t cmdtype = 0;
544 if (ol_flags & PKT_TX_VLAN_PKT)
545 cmdtype |= IXGBE_ADVTXD_DCMD_VLE;
546 if (ol_flags & PKT_TX_TCP_SEG)
547 cmdtype |= IXGBE_ADVTXD_DCMD_TSE;
548 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
549 cmdtype |= (1 << IXGBE_ADVTXD_OUTERIPCS_SHIFT);
550 if (ol_flags & PKT_TX_MACSEC)
551 cmdtype |= IXGBE_ADVTXD_MAC_LINKSEC;
555 /* Default RS bit threshold values */
556 #ifndef DEFAULT_TX_RS_THRESH
557 #define DEFAULT_TX_RS_THRESH 32
559 #ifndef DEFAULT_TX_FREE_THRESH
560 #define DEFAULT_TX_FREE_THRESH 32
563 /* Reset transmit descriptors after they have been used */
565 ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)
567 struct ixgbe_tx_entry *sw_ring = txq->sw_ring;
568 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
569 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
570 uint16_t nb_tx_desc = txq->nb_tx_desc;
571 uint16_t desc_to_clean_to;
572 uint16_t nb_tx_to_clean;
575 /* Determine the last descriptor needing to be cleaned */
576 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
577 if (desc_to_clean_to >= nb_tx_desc)
578 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
580 /* Check to make sure the last descriptor to clean is done */
581 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
582 status = txr[desc_to_clean_to].wb.status;
583 if (!(status & rte_cpu_to_le_32(IXGBE_TXD_STAT_DD))) {
584 PMD_TX_FREE_LOG(DEBUG,
585 "TX descriptor %4u is not done"
586 "(port=%d queue=%d)",
588 txq->port_id, txq->queue_id);
589 /* Failed to clean any descriptors, better luck next time */
593 /* Figure out how many descriptors will be cleaned */
594 if (last_desc_cleaned > desc_to_clean_to)
595 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
598 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
601 PMD_TX_FREE_LOG(DEBUG,
602 "Cleaning %4u TX descriptors: %4u to %4u "
603 "(port=%d queue=%d)",
604 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
605 txq->port_id, txq->queue_id);
608 * The last descriptor to clean is done, so that means all the
609 * descriptors from the last descriptor that was cleaned
610 * up to the last descriptor with the RS bit set
611 * are done. Only reset the threshold descriptor.
613 txr[desc_to_clean_to].wb.status = 0;
615 /* Update the txq to reflect the last descriptor that was cleaned */
616 txq->last_desc_cleaned = desc_to_clean_to;
617 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
624 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
627 struct ixgbe_tx_queue *txq;
628 struct ixgbe_tx_entry *sw_ring;
629 struct ixgbe_tx_entry *txe, *txn;
630 volatile union ixgbe_adv_tx_desc *txr;
631 volatile union ixgbe_adv_tx_desc *txd, *txp;
632 struct rte_mbuf *tx_pkt;
633 struct rte_mbuf *m_seg;
634 uint64_t buf_dma_addr;
635 uint32_t olinfo_status;
636 uint32_t cmd_type_len;
647 union ixgbe_tx_offload tx_offload;
648 #ifdef RTE_LIBRTE_SECURITY
652 tx_offload.data[0] = 0;
653 tx_offload.data[1] = 0;
655 sw_ring = txq->sw_ring;
657 tx_id = txq->tx_tail;
658 txe = &sw_ring[tx_id];
661 /* Determine if the descriptor ring needs to be cleaned. */
662 if (txq->nb_tx_free < txq->tx_free_thresh)
663 ixgbe_xmit_cleanup(txq);
665 rte_prefetch0(&txe->mbuf->pool);
668 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
671 pkt_len = tx_pkt->pkt_len;
674 * Determine how many (if any) context descriptors
675 * are needed for offload functionality.
677 ol_flags = tx_pkt->ol_flags;
678 #ifdef RTE_LIBRTE_SECURITY
679 use_ipsec = txq->using_ipsec && (ol_flags & PKT_TX_SEC_OFFLOAD);
682 /* If hardware offload required */
683 tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
685 tx_offload.l2_len = tx_pkt->l2_len;
686 tx_offload.l3_len = tx_pkt->l3_len;
687 tx_offload.l4_len = tx_pkt->l4_len;
688 tx_offload.vlan_tci = tx_pkt->vlan_tci;
689 tx_offload.tso_segsz = tx_pkt->tso_segsz;
690 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
691 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
692 #ifdef RTE_LIBRTE_SECURITY
694 union ixgbe_crypto_tx_desc_md *ipsec_mdata =
695 (union ixgbe_crypto_tx_desc_md *)
697 tx_offload.sa_idx = ipsec_mdata->sa_idx;
698 tx_offload.sec_pad_len = ipsec_mdata->pad_len;
702 /* If new context need be built or reuse the exist ctx. */
703 ctx = what_advctx_update(txq, tx_ol_req,
705 /* Only allocate context descriptor if required*/
706 new_ctx = (ctx == IXGBE_CTX_NUM);
711 * Keep track of how many descriptors are used this loop
712 * This will always be the number of segments + the number of
713 * Context descriptors required to transmit the packet
715 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
718 nb_used + txq->nb_tx_used >= txq->tx_rs_thresh)
719 /* set RS on the previous packet in the burst */
720 txp->read.cmd_type_len |=
721 rte_cpu_to_le_32(IXGBE_TXD_CMD_RS);
724 * The number of descriptors that must be allocated for a
725 * packet is the number of segments of that packet, plus 1
726 * Context Descriptor for the hardware offload, if any.
727 * Determine the last TX descriptor to allocate in the TX ring
728 * for the packet, starting from the current position (tx_id)
731 tx_last = (uint16_t) (tx_id + nb_used - 1);
734 if (tx_last >= txq->nb_tx_desc)
735 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
737 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
738 " tx_first=%u tx_last=%u",
739 (unsigned) txq->port_id,
740 (unsigned) txq->queue_id,
746 * Make sure there are enough TX descriptors available to
747 * transmit the entire packet.
748 * nb_used better be less than or equal to txq->tx_rs_thresh
750 if (nb_used > txq->nb_tx_free) {
751 PMD_TX_FREE_LOG(DEBUG,
752 "Not enough free TX descriptors "
753 "nb_used=%4u nb_free=%4u "
754 "(port=%d queue=%d)",
755 nb_used, txq->nb_tx_free,
756 txq->port_id, txq->queue_id);
758 if (ixgbe_xmit_cleanup(txq) != 0) {
759 /* Could not clean any descriptors */
765 /* nb_used better be <= txq->tx_rs_thresh */
766 if (unlikely(nb_used > txq->tx_rs_thresh)) {
767 PMD_TX_FREE_LOG(DEBUG,
768 "The number of descriptors needed to "
769 "transmit the packet exceeds the "
770 "RS bit threshold. This will impact "
772 "nb_used=%4u nb_free=%4u "
774 "(port=%d queue=%d)",
775 nb_used, txq->nb_tx_free,
777 txq->port_id, txq->queue_id);
779 * Loop here until there are enough TX
780 * descriptors or until the ring cannot be
783 while (nb_used > txq->nb_tx_free) {
784 if (ixgbe_xmit_cleanup(txq) != 0) {
786 * Could not clean any
798 * By now there are enough free TX descriptors to transmit
803 * Set common flags of all TX Data Descriptors.
805 * The following bits must be set in all Data Descriptors:
806 * - IXGBE_ADVTXD_DTYP_DATA
807 * - IXGBE_ADVTXD_DCMD_DEXT
809 * The following bits must be set in the first Data Descriptor
810 * and are ignored in the other ones:
811 * - IXGBE_ADVTXD_DCMD_IFCS
812 * - IXGBE_ADVTXD_MAC_1588
813 * - IXGBE_ADVTXD_DCMD_VLE
815 * The following bits must only be set in the last Data
817 * - IXGBE_TXD_CMD_EOP
819 * The following bits can be set in any Data Descriptor, but
820 * are only set in the last Data Descriptor:
823 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
824 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
826 #ifdef RTE_LIBRTE_IEEE1588
827 if (ol_flags & PKT_TX_IEEE1588_TMST)
828 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
834 if (ol_flags & PKT_TX_TCP_SEG) {
835 /* when TSO is on, paylen in descriptor is the
836 * not the packet len but the tcp payload len */
837 pkt_len -= (tx_offload.l2_len +
838 tx_offload.l3_len + tx_offload.l4_len);
842 * Setup the TX Advanced Context Descriptor if required
845 volatile struct ixgbe_adv_tx_context_desc *
848 ctx_txd = (volatile struct
849 ixgbe_adv_tx_context_desc *)
852 txn = &sw_ring[txe->next_id];
853 rte_prefetch0(&txn->mbuf->pool);
855 if (txe->mbuf != NULL) {
856 rte_pktmbuf_free_seg(txe->mbuf);
860 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
861 tx_offload, &tx_pkt->udata64);
863 txe->last_id = tx_last;
864 tx_id = txe->next_id;
869 * Setup the TX Advanced Data Descriptor,
870 * This path will go through
871 * whatever new/reuse the context descriptor
873 cmd_type_len |= tx_desc_ol_flags_to_cmdtype(ol_flags);
874 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
875 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
878 olinfo_status |= (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
879 #ifdef RTE_LIBRTE_SECURITY
881 olinfo_status |= IXGBE_ADVTXD_POPTS_IPSEC;
887 txn = &sw_ring[txe->next_id];
888 rte_prefetch0(&txn->mbuf->pool);
890 if (txe->mbuf != NULL)
891 rte_pktmbuf_free_seg(txe->mbuf);
895 * Set up Transmit Data Descriptor.
897 slen = m_seg->data_len;
898 buf_dma_addr = rte_mbuf_data_iova(m_seg);
899 txd->read.buffer_addr =
900 rte_cpu_to_le_64(buf_dma_addr);
901 txd->read.cmd_type_len =
902 rte_cpu_to_le_32(cmd_type_len | slen);
903 txd->read.olinfo_status =
904 rte_cpu_to_le_32(olinfo_status);
905 txe->last_id = tx_last;
906 tx_id = txe->next_id;
909 } while (m_seg != NULL);
912 * The last packet data descriptor needs End Of Packet (EOP)
914 cmd_type_len |= IXGBE_TXD_CMD_EOP;
915 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
916 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
918 /* Set RS bit only on threshold packets' last descriptor */
919 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
920 PMD_TX_FREE_LOG(DEBUG,
921 "Setting RS bit on TXD id="
922 "%4u (port=%d queue=%d)",
923 tx_last, txq->port_id, txq->queue_id);
925 cmd_type_len |= IXGBE_TXD_CMD_RS;
927 /* Update txq RS bit counters */
933 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
937 /* set RS on last packet in the burst */
939 txp->read.cmd_type_len |= rte_cpu_to_le_32(IXGBE_TXD_CMD_RS);
944 * Set the Transmit Descriptor Tail (TDT)
946 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
947 (unsigned) txq->port_id, (unsigned) txq->queue_id,
948 (unsigned) tx_id, (unsigned) nb_tx);
949 IXGBE_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, tx_id);
950 txq->tx_tail = tx_id;
955 /*********************************************************************
959 **********************************************************************/
961 ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
966 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
968 for (i = 0; i < nb_pkts; i++) {
970 ol_flags = m->ol_flags;
973 * Check if packet meets requirements for number of segments
975 * NOTE: for ixgbe it's always (40 - WTHRESH) for both TSO and
979 if (m->nb_segs > IXGBE_TX_MAX_SEG - txq->wthresh) {
984 if (ol_flags & IXGBE_TX_OFFLOAD_NOTSUP_MASK) {
985 rte_errno = -ENOTSUP;
989 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
990 ret = rte_validate_tx_offload(m);
996 ret = rte_net_intel_cksum_prepare(m);
1006 /*********************************************************************
1010 **********************************************************************/
1012 #define IXGBE_PACKET_TYPE_ETHER 0X00
1013 #define IXGBE_PACKET_TYPE_IPV4 0X01
1014 #define IXGBE_PACKET_TYPE_IPV4_TCP 0X11
1015 #define IXGBE_PACKET_TYPE_IPV4_UDP 0X21
1016 #define IXGBE_PACKET_TYPE_IPV4_SCTP 0X41
1017 #define IXGBE_PACKET_TYPE_IPV4_EXT 0X03
1018 #define IXGBE_PACKET_TYPE_IPV4_EXT_TCP 0X13
1019 #define IXGBE_PACKET_TYPE_IPV4_EXT_UDP 0X23
1020 #define IXGBE_PACKET_TYPE_IPV4_EXT_SCTP 0X43
1021 #define IXGBE_PACKET_TYPE_IPV6 0X04
1022 #define IXGBE_PACKET_TYPE_IPV6_TCP 0X14
1023 #define IXGBE_PACKET_TYPE_IPV6_UDP 0X24
1024 #define IXGBE_PACKET_TYPE_IPV6_SCTP 0X44
1025 #define IXGBE_PACKET_TYPE_IPV6_EXT 0X0C
1026 #define IXGBE_PACKET_TYPE_IPV6_EXT_TCP 0X1C
1027 #define IXGBE_PACKET_TYPE_IPV6_EXT_UDP 0X2C
1028 #define IXGBE_PACKET_TYPE_IPV6_EXT_SCTP 0X4C
1029 #define IXGBE_PACKET_TYPE_IPV4_IPV6 0X05
1030 #define IXGBE_PACKET_TYPE_IPV4_IPV6_TCP 0X15
1031 #define IXGBE_PACKET_TYPE_IPV4_IPV6_UDP 0X25
1032 #define IXGBE_PACKET_TYPE_IPV4_IPV6_SCTP 0X45
1033 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6 0X07
1034 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_TCP 0X17
1035 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_UDP 0X27
1036 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_SCTP 0X47
1037 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT 0X0D
1038 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP 0X1D
1039 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP 0X2D
1040 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_SCTP 0X4D
1041 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT 0X0F
1042 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_TCP 0X1F
1043 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_UDP 0X2F
1044 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_SCTP 0X4F
1046 #define IXGBE_PACKET_TYPE_NVGRE 0X00
1047 #define IXGBE_PACKET_TYPE_NVGRE_IPV4 0X01
1048 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_TCP 0X11
1049 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_UDP 0X21
1050 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_SCTP 0X41
1051 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT 0X03
1052 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_TCP 0X13
1053 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_UDP 0X23
1054 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_SCTP 0X43
1055 #define IXGBE_PACKET_TYPE_NVGRE_IPV6 0X04
1056 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_TCP 0X14
1057 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_UDP 0X24
1058 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_SCTP 0X44
1059 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT 0X0C
1060 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_TCP 0X1C
1061 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_UDP 0X2C
1062 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_SCTP 0X4C
1063 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6 0X05
1064 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_TCP 0X15
1065 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_UDP 0X25
1066 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT 0X0D
1067 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_TCP 0X1D
1068 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_UDP 0X2D
1070 #define IXGBE_PACKET_TYPE_VXLAN 0X80
1071 #define IXGBE_PACKET_TYPE_VXLAN_IPV4 0X81
1072 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_TCP 0x91
1073 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_UDP 0xA1
1074 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_SCTP 0xC1
1075 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT 0x83
1076 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_TCP 0X93
1077 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_UDP 0XA3
1078 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_SCTP 0XC3
1079 #define IXGBE_PACKET_TYPE_VXLAN_IPV6 0X84
1080 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_TCP 0X94
1081 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_UDP 0XA4
1082 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_SCTP 0XC4
1083 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT 0X8C
1084 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_TCP 0X9C
1085 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_UDP 0XAC
1086 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_SCTP 0XCC
1087 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6 0X85
1088 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_TCP 0X95
1089 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_UDP 0XA5
1090 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT 0X8D
1091 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_TCP 0X9D
1092 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_UDP 0XAD
1095 * Use 2 different table for normal packet and tunnel packet
1096 * to save the space.
1099 ptype_table[IXGBE_PACKET_TYPE_MAX] __rte_cache_aligned = {
1100 [IXGBE_PACKET_TYPE_ETHER] = RTE_PTYPE_L2_ETHER,
1101 [IXGBE_PACKET_TYPE_IPV4] = RTE_PTYPE_L2_ETHER |
1103 [IXGBE_PACKET_TYPE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1104 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
1105 [IXGBE_PACKET_TYPE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1106 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
1107 [IXGBE_PACKET_TYPE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1108 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP,
1109 [IXGBE_PACKET_TYPE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1110 RTE_PTYPE_L3_IPV4_EXT,
1111 [IXGBE_PACKET_TYPE_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1112 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_TCP,
1113 [IXGBE_PACKET_TYPE_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1114 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_UDP,
1115 [IXGBE_PACKET_TYPE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1116 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_SCTP,
1117 [IXGBE_PACKET_TYPE_IPV6] = RTE_PTYPE_L2_ETHER |
1119 [IXGBE_PACKET_TYPE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1120 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
1121 [IXGBE_PACKET_TYPE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1122 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
1123 [IXGBE_PACKET_TYPE_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1124 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_SCTP,
1125 [IXGBE_PACKET_TYPE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1126 RTE_PTYPE_L3_IPV6_EXT,
1127 [IXGBE_PACKET_TYPE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1128 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,
1129 [IXGBE_PACKET_TYPE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1130 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
1131 [IXGBE_PACKET_TYPE_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1132 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_SCTP,
1133 [IXGBE_PACKET_TYPE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1134 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1135 RTE_PTYPE_INNER_L3_IPV6,
1136 [IXGBE_PACKET_TYPE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1137 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1138 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1139 [IXGBE_PACKET_TYPE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1140 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1141 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1142 [IXGBE_PACKET_TYPE_IPV4_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1143 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1144 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
1145 [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6] = RTE_PTYPE_L2_ETHER |
1146 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1147 RTE_PTYPE_INNER_L3_IPV6,
1148 [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1149 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1150 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1151 [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1152 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1153 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1154 [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1155 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1156 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
1157 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1158 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1159 RTE_PTYPE_INNER_L3_IPV6_EXT,
1160 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1161 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1162 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1163 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1164 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1165 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1166 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1167 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1168 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
1169 [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1170 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1171 RTE_PTYPE_INNER_L3_IPV6_EXT,
1172 [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1173 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1174 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1175 [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1176 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1177 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1178 [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_SCTP] =
1179 RTE_PTYPE_L2_ETHER |
1180 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1181 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
1185 ptype_table_tn[IXGBE_PACKET_TYPE_TN_MAX] __rte_cache_aligned = {
1186 [IXGBE_PACKET_TYPE_NVGRE] = RTE_PTYPE_L2_ETHER |
1187 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1188 RTE_PTYPE_INNER_L2_ETHER,
1189 [IXGBE_PACKET_TYPE_NVGRE_IPV4] = RTE_PTYPE_L2_ETHER |
1190 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1191 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1192 [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1193 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1194 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT,
1195 [IXGBE_PACKET_TYPE_NVGRE_IPV6] = RTE_PTYPE_L2_ETHER |
1196 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1197 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6,
1198 [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1199 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1200 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1201 [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1202 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1203 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT,
1204 [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1205 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1206 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1207 [IXGBE_PACKET_TYPE_NVGRE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1208 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1209 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1210 RTE_PTYPE_INNER_L4_TCP,
1211 [IXGBE_PACKET_TYPE_NVGRE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1212 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1213 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1214 RTE_PTYPE_INNER_L4_TCP,
1215 [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1216 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1217 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1218 [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1219 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1220 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1221 RTE_PTYPE_INNER_L4_TCP,
1222 [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_TCP] =
1223 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1224 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_INNER_L2_ETHER |
1225 RTE_PTYPE_INNER_L3_IPV4,
1226 [IXGBE_PACKET_TYPE_NVGRE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1227 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1228 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1229 RTE_PTYPE_INNER_L4_UDP,
1230 [IXGBE_PACKET_TYPE_NVGRE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1231 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1232 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1233 RTE_PTYPE_INNER_L4_UDP,
1234 [IXGBE_PACKET_TYPE_NVGRE_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1235 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1236 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1237 RTE_PTYPE_INNER_L4_SCTP,
1238 [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1239 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1240 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1241 [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1242 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1243 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1244 RTE_PTYPE_INNER_L4_UDP,
1245 [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1246 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1247 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1248 RTE_PTYPE_INNER_L4_SCTP,
1249 [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_UDP] =
1250 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1251 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_INNER_L2_ETHER |
1252 RTE_PTYPE_INNER_L3_IPV4,
1253 [IXGBE_PACKET_TYPE_NVGRE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1254 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1255 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1256 RTE_PTYPE_INNER_L4_SCTP,
1257 [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1258 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1259 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
1260 RTE_PTYPE_INNER_L4_SCTP,
1261 [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1262 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1263 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
1264 RTE_PTYPE_INNER_L4_TCP,
1265 [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1266 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1267 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
1268 RTE_PTYPE_INNER_L4_UDP,
1270 [IXGBE_PACKET_TYPE_VXLAN] = RTE_PTYPE_L2_ETHER |
1271 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1272 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER,
1273 [IXGBE_PACKET_TYPE_VXLAN_IPV4] = RTE_PTYPE_L2_ETHER |
1274 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1275 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1276 RTE_PTYPE_INNER_L3_IPV4,
1277 [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1278 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1279 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1280 RTE_PTYPE_INNER_L3_IPV4_EXT,
1281 [IXGBE_PACKET_TYPE_VXLAN_IPV6] = RTE_PTYPE_L2_ETHER |
1282 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1283 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1284 RTE_PTYPE_INNER_L3_IPV6,
1285 [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1286 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1287 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1288 RTE_PTYPE_INNER_L3_IPV4,
1289 [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1290 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1291 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1292 RTE_PTYPE_INNER_L3_IPV6_EXT,
1293 [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1294 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1295 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1296 RTE_PTYPE_INNER_L3_IPV4,
1297 [IXGBE_PACKET_TYPE_VXLAN_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1298 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1299 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1300 RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_TCP,
1301 [IXGBE_PACKET_TYPE_VXLAN_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1302 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1303 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1304 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1305 [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1306 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1307 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1308 RTE_PTYPE_INNER_L3_IPV4,
1309 [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1310 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1311 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1312 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1313 [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_TCP] =
1314 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1315 RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN |
1316 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1317 [IXGBE_PACKET_TYPE_VXLAN_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1318 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1319 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1320 RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_UDP,
1321 [IXGBE_PACKET_TYPE_VXLAN_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1322 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1323 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1324 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1325 [IXGBE_PACKET_TYPE_VXLAN_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1326 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1327 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1328 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
1329 [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1330 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1331 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1332 RTE_PTYPE_INNER_L3_IPV4,
1333 [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1334 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1335 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1336 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1337 [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1338 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1339 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1340 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
1341 [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_UDP] =
1342 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1343 RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN |
1344 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1345 [IXGBE_PACKET_TYPE_VXLAN_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1346 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1347 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1348 RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_SCTP,
1349 [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1350 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1351 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1352 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_SCTP,
1353 [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1354 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1355 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1356 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_TCP,
1357 [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1358 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1359 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1360 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
1363 /* @note: fix ixgbe_dev_supported_ptypes_get() if any change here. */
1364 static inline uint32_t
1365 ixgbe_rxd_pkt_info_to_pkt_type(uint32_t pkt_info, uint16_t ptype_mask)
1368 if (unlikely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
1369 return RTE_PTYPE_UNKNOWN;
1371 pkt_info = (pkt_info >> IXGBE_PACKET_TYPE_SHIFT) & ptype_mask;
1373 /* For tunnel packet */
1374 if (pkt_info & IXGBE_PACKET_TYPE_TUNNEL_BIT) {
1375 /* Remove the tunnel bit to save the space. */
1376 pkt_info &= IXGBE_PACKET_TYPE_MASK_TUNNEL;
1377 return ptype_table_tn[pkt_info];
1381 * For x550, if it's not tunnel,
1382 * tunnel type bit should be set to 0.
1383 * Reuse 82599's mask.
1385 pkt_info &= IXGBE_PACKET_TYPE_MASK_82599;
1387 return ptype_table[pkt_info];
1390 static inline uint64_t
1391 ixgbe_rxd_pkt_info_to_pkt_flags(uint16_t pkt_info)
1393 static uint64_t ip_rss_types_map[16] __rte_cache_aligned = {
1394 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
1395 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
1396 PKT_RX_RSS_HASH, 0, 0, 0,
1397 0, 0, 0, PKT_RX_FDIR,
1399 #ifdef RTE_LIBRTE_IEEE1588
1400 static uint64_t ip_pkt_etqf_map[8] = {
1401 0, 0, 0, PKT_RX_IEEE1588_PTP,
1405 if (likely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
1406 return ip_pkt_etqf_map[(pkt_info >> 4) & 0X07] |
1407 ip_rss_types_map[pkt_info & 0XF];
1409 return ip_rss_types_map[pkt_info & 0XF];
1411 return ip_rss_types_map[pkt_info & 0XF];
1415 static inline uint64_t
1416 rx_desc_status_to_pkt_flags(uint32_t rx_status, uint64_t vlan_flags)
1421 * Check if VLAN present only.
1422 * Do not check whether L3/L4 rx checksum done by NIC or not,
1423 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
1425 pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ? vlan_flags : 0;
1427 #ifdef RTE_LIBRTE_IEEE1588
1428 if (rx_status & IXGBE_RXD_STAT_TMST)
1429 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
1434 static inline uint64_t
1435 rx_desc_error_to_pkt_flags(uint32_t rx_status)
1440 * Bit 31: IPE, IPv4 checksum error
1441 * Bit 30: L4I, L4I integrity error
1443 static uint64_t error_to_pkt_flags_map[4] = {
1444 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD,
1445 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
1446 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD,
1447 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
1449 pkt_flags = error_to_pkt_flags_map[(rx_status >>
1450 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
1452 if ((rx_status & IXGBE_RXD_STAT_OUTERIPCS) &&
1453 (rx_status & IXGBE_RXDADV_ERR_OUTERIPER)) {
1454 pkt_flags |= PKT_RX_EIP_CKSUM_BAD;
1457 #ifdef RTE_LIBRTE_SECURITY
1458 if (rx_status & IXGBE_RXD_STAT_SECP) {
1459 pkt_flags |= PKT_RX_SEC_OFFLOAD;
1460 if (rx_status & IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG)
1461 pkt_flags |= PKT_RX_SEC_OFFLOAD_FAILED;
1469 * LOOK_AHEAD defines how many desc statuses to check beyond the
1470 * current descriptor.
1471 * It must be a pound define for optimal performance.
1472 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
1473 * function only works with LOOK_AHEAD=8.
1475 #define LOOK_AHEAD 8
1476 #if (LOOK_AHEAD != 8)
1477 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
1480 ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
1482 volatile union ixgbe_adv_rx_desc *rxdp;
1483 struct ixgbe_rx_entry *rxep;
1484 struct rte_mbuf *mb;
1488 uint32_t s[LOOK_AHEAD];
1489 uint32_t pkt_info[LOOK_AHEAD];
1490 int i, j, nb_rx = 0;
1492 uint64_t vlan_flags = rxq->vlan_flags;
1494 /* get references to current descriptor and S/W ring entry */
1495 rxdp = &rxq->rx_ring[rxq->rx_tail];
1496 rxep = &rxq->sw_ring[rxq->rx_tail];
1498 status = rxdp->wb.upper.status_error;
1499 /* check to make sure there is at least 1 packet to receive */
1500 if (!(status & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1504 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
1505 * reference packets that are ready to be received.
1507 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
1508 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD) {
1509 /* Read desc statuses backwards to avoid race condition */
1510 for (j = 0; j < LOOK_AHEAD; j++)
1511 s[j] = rte_le_to_cpu_32(rxdp[j].wb.upper.status_error);
1515 /* Compute how many status bits were set */
1516 for (nb_dd = 0; nb_dd < LOOK_AHEAD &&
1517 (s[nb_dd] & IXGBE_RXDADV_STAT_DD); nb_dd++)
1520 for (j = 0; j < nb_dd; j++)
1521 pkt_info[j] = rte_le_to_cpu_32(rxdp[j].wb.lower.
1526 /* Translate descriptor info to mbuf format */
1527 for (j = 0; j < nb_dd; ++j) {
1529 pkt_len = rte_le_to_cpu_16(rxdp[j].wb.upper.length) -
1531 mb->data_len = pkt_len;
1532 mb->pkt_len = pkt_len;
1533 mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
1535 /* convert descriptor fields to rte mbuf flags */
1536 pkt_flags = rx_desc_status_to_pkt_flags(s[j],
1538 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
1539 pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags
1540 ((uint16_t)pkt_info[j]);
1541 mb->ol_flags = pkt_flags;
1543 ixgbe_rxd_pkt_info_to_pkt_type
1544 (pkt_info[j], rxq->pkt_type_mask);
1546 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1547 mb->hash.rss = rte_le_to_cpu_32(
1548 rxdp[j].wb.lower.hi_dword.rss);
1549 else if (pkt_flags & PKT_RX_FDIR) {
1550 mb->hash.fdir.hash = rte_le_to_cpu_16(
1551 rxdp[j].wb.lower.hi_dword.csum_ip.csum) &
1552 IXGBE_ATR_HASH_MASK;
1553 mb->hash.fdir.id = rte_le_to_cpu_16(
1554 rxdp[j].wb.lower.hi_dword.csum_ip.ip_id);
1558 /* Move mbuf pointers from the S/W ring to the stage */
1559 for (j = 0; j < LOOK_AHEAD; ++j) {
1560 rxq->rx_stage[i + j] = rxep[j].mbuf;
1563 /* stop if all requested packets could not be received */
1564 if (nb_dd != LOOK_AHEAD)
1568 /* clear software ring entries so we can cleanup correctly */
1569 for (i = 0; i < nb_rx; ++i) {
1570 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1578 ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq, bool reset_mbuf)
1580 volatile union ixgbe_adv_rx_desc *rxdp;
1581 struct ixgbe_rx_entry *rxep;
1582 struct rte_mbuf *mb;
1587 /* allocate buffers in bulk directly into the S/W ring */
1588 alloc_idx = rxq->rx_free_trigger - (rxq->rx_free_thresh - 1);
1589 rxep = &rxq->sw_ring[alloc_idx];
1590 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1591 rxq->rx_free_thresh);
1592 if (unlikely(diag != 0))
1595 rxdp = &rxq->rx_ring[alloc_idx];
1596 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1597 /* populate the static rte mbuf fields */
1600 mb->port = rxq->port_id;
1603 rte_mbuf_refcnt_set(mb, 1);
1604 mb->data_off = RTE_PKTMBUF_HEADROOM;
1606 /* populate the descriptors */
1607 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1608 rxdp[i].read.hdr_addr = 0;
1609 rxdp[i].read.pkt_addr = dma_addr;
1612 /* update state of internal queue structure */
1613 rxq->rx_free_trigger = rxq->rx_free_trigger + rxq->rx_free_thresh;
1614 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1615 rxq->rx_free_trigger = rxq->rx_free_thresh - 1;
1621 static inline uint16_t
1622 ixgbe_rx_fill_from_stage(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1625 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1628 /* how many packets are ready to return? */
1629 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1631 /* copy mbuf pointers to the application's packet list */
1632 for (i = 0; i < nb_pkts; ++i)
1633 rx_pkts[i] = stage[i];
1635 /* update internal queue state */
1636 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1637 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1642 static inline uint16_t
1643 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1646 struct ixgbe_rx_queue *rxq = (struct ixgbe_rx_queue *)rx_queue;
1649 /* Any previously recv'd pkts will be returned from the Rx stage */
1650 if (rxq->rx_nb_avail)
1651 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1653 /* Scan the H/W ring for packets to receive */
1654 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1656 /* update internal queue state */
1657 rxq->rx_next_avail = 0;
1658 rxq->rx_nb_avail = nb_rx;
1659 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1661 /* if required, allocate new buffers to replenish descriptors */
1662 if (rxq->rx_tail > rxq->rx_free_trigger) {
1663 uint16_t cur_free_trigger = rxq->rx_free_trigger;
1665 if (ixgbe_rx_alloc_bufs(rxq, true) != 0) {
1668 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1669 "queue_id=%u", (unsigned) rxq->port_id,
1670 (unsigned) rxq->queue_id);
1672 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1673 rxq->rx_free_thresh;
1676 * Need to rewind any previous receives if we cannot
1677 * allocate new buffers to replenish the old ones.
1679 rxq->rx_nb_avail = 0;
1680 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1681 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1682 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1687 /* update tail pointer */
1689 IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr,
1693 if (rxq->rx_tail >= rxq->nb_rx_desc)
1696 /* received any packets this loop? */
1697 if (rxq->rx_nb_avail)
1698 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1703 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1705 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1710 if (unlikely(nb_pkts == 0))
1713 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1714 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1716 /* request is relatively large, chunk it up */
1721 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1722 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1723 nb_rx = (uint16_t)(nb_rx + ret);
1724 nb_pkts = (uint16_t)(nb_pkts - ret);
1733 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1736 struct ixgbe_rx_queue *rxq;
1737 volatile union ixgbe_adv_rx_desc *rx_ring;
1738 volatile union ixgbe_adv_rx_desc *rxdp;
1739 struct ixgbe_rx_entry *sw_ring;
1740 struct ixgbe_rx_entry *rxe;
1741 struct rte_mbuf *rxm;
1742 struct rte_mbuf *nmb;
1743 union ixgbe_adv_rx_desc rxd;
1752 uint64_t vlan_flags;
1757 rx_id = rxq->rx_tail;
1758 rx_ring = rxq->rx_ring;
1759 sw_ring = rxq->sw_ring;
1760 vlan_flags = rxq->vlan_flags;
1761 while (nb_rx < nb_pkts) {
1763 * The order of operations here is important as the DD status
1764 * bit must not be read after any other descriptor fields.
1765 * rx_ring and rxdp are pointing to volatile data so the order
1766 * of accesses cannot be reordered by the compiler. If they were
1767 * not volatile, they could be reordered which could lead to
1768 * using invalid descriptor fields when read from rxd.
1770 rxdp = &rx_ring[rx_id];
1771 staterr = rxdp->wb.upper.status_error;
1772 if (!(staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1779 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1780 * is likely to be invalid and to be dropped by the various
1781 * validation checks performed by the network stack.
1783 * Allocate a new mbuf to replenish the RX ring descriptor.
1784 * If the allocation fails:
1785 * - arrange for that RX descriptor to be the first one
1786 * being parsed the next time the receive function is
1787 * invoked [on the same queue].
1789 * - Stop parsing the RX ring and return immediately.
1791 * This policy do not drop the packet received in the RX
1792 * descriptor for which the allocation of a new mbuf failed.
1793 * Thus, it allows that packet to be later retrieved if
1794 * mbuf have been freed in the mean time.
1795 * As a side effect, holding RX descriptors instead of
1796 * systematically giving them back to the NIC may lead to
1797 * RX ring exhaustion situations.
1798 * However, the NIC can gracefully prevent such situations
1799 * to happen by sending specific "back-pressure" flow control
1800 * frames to its peer(s).
1802 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1803 "ext_err_stat=0x%08x pkt_len=%u",
1804 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1805 (unsigned) rx_id, (unsigned) staterr,
1806 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1808 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
1810 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1811 "queue_id=%u", (unsigned) rxq->port_id,
1812 (unsigned) rxq->queue_id);
1813 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1818 rxe = &sw_ring[rx_id];
1820 if (rx_id == rxq->nb_rx_desc)
1823 /* Prefetch next mbuf while processing current one. */
1824 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1827 * When next RX descriptor is on a cache-line boundary,
1828 * prefetch the next 4 RX descriptors and the next 8 pointers
1831 if ((rx_id & 0x3) == 0) {
1832 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1833 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1839 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1840 rxdp->read.hdr_addr = 0;
1841 rxdp->read.pkt_addr = dma_addr;
1844 * Initialize the returned mbuf.
1845 * 1) setup generic mbuf fields:
1846 * - number of segments,
1849 * - RX port identifier.
1850 * 2) integrate hardware offload data, if any:
1851 * - RSS flag & hash,
1852 * - IP checksum flag,
1853 * - VLAN TCI, if any,
1856 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1858 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1859 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1862 rxm->pkt_len = pkt_len;
1863 rxm->data_len = pkt_len;
1864 rxm->port = rxq->port_id;
1866 pkt_info = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1867 /* Only valid if PKT_RX_VLAN set in pkt_flags */
1868 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1870 pkt_flags = rx_desc_status_to_pkt_flags(staterr, vlan_flags);
1871 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1872 pkt_flags = pkt_flags |
1873 ixgbe_rxd_pkt_info_to_pkt_flags((uint16_t)pkt_info);
1874 rxm->ol_flags = pkt_flags;
1876 ixgbe_rxd_pkt_info_to_pkt_type(pkt_info,
1877 rxq->pkt_type_mask);
1879 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1880 rxm->hash.rss = rte_le_to_cpu_32(
1881 rxd.wb.lower.hi_dword.rss);
1882 else if (pkt_flags & PKT_RX_FDIR) {
1883 rxm->hash.fdir.hash = rte_le_to_cpu_16(
1884 rxd.wb.lower.hi_dword.csum_ip.csum) &
1885 IXGBE_ATR_HASH_MASK;
1886 rxm->hash.fdir.id = rte_le_to_cpu_16(
1887 rxd.wb.lower.hi_dword.csum_ip.ip_id);
1890 * Store the mbuf address into the next entry of the array
1891 * of returned packets.
1893 rx_pkts[nb_rx++] = rxm;
1895 rxq->rx_tail = rx_id;
1898 * If the number of free RX descriptors is greater than the RX free
1899 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1901 * Update the RDT with the value of the last processed RX descriptor
1902 * minus 1, to guarantee that the RDT register is never equal to the
1903 * RDH register, which creates a "full" ring situtation from the
1904 * hardware point of view...
1906 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1907 if (nb_hold > rxq->rx_free_thresh) {
1908 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1909 "nb_hold=%u nb_rx=%u",
1910 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1911 (unsigned) rx_id, (unsigned) nb_hold,
1913 rx_id = (uint16_t) ((rx_id == 0) ?
1914 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1915 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1918 rxq->nb_rx_hold = nb_hold;
1923 * Detect an RSC descriptor.
1925 static inline uint32_t
1926 ixgbe_rsc_count(union ixgbe_adv_rx_desc *rx)
1928 return (rte_le_to_cpu_32(rx->wb.lower.lo_dword.data) &
1929 IXGBE_RXDADV_RSCCNT_MASK) >> IXGBE_RXDADV_RSCCNT_SHIFT;
1933 * ixgbe_fill_cluster_head_buf - fill the first mbuf of the returned packet
1935 * Fill the following info in the HEAD buffer of the Rx cluster:
1936 * - RX port identifier
1937 * - hardware offload data, if any:
1939 * - IP checksum flag
1940 * - VLAN TCI, if any
1942 * @head HEAD of the packet cluster
1943 * @desc HW descriptor to get data from
1944 * @rxq Pointer to the Rx queue
1947 ixgbe_fill_cluster_head_buf(
1948 struct rte_mbuf *head,
1949 union ixgbe_adv_rx_desc *desc,
1950 struct ixgbe_rx_queue *rxq,
1956 head->port = rxq->port_id;
1958 /* The vlan_tci field is only valid when PKT_RX_VLAN is
1959 * set in the pkt_flags field.
1961 head->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);
1962 pkt_info = rte_le_to_cpu_32(desc->wb.lower.lo_dword.data);
1963 pkt_flags = rx_desc_status_to_pkt_flags(staterr, rxq->vlan_flags);
1964 pkt_flags |= rx_desc_error_to_pkt_flags(staterr);
1965 pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags((uint16_t)pkt_info);
1966 head->ol_flags = pkt_flags;
1968 ixgbe_rxd_pkt_info_to_pkt_type(pkt_info, rxq->pkt_type_mask);
1970 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1971 head->hash.rss = rte_le_to_cpu_32(desc->wb.lower.hi_dword.rss);
1972 else if (pkt_flags & PKT_RX_FDIR) {
1973 head->hash.fdir.hash =
1974 rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.csum)
1975 & IXGBE_ATR_HASH_MASK;
1976 head->hash.fdir.id =
1977 rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.ip_id);
1982 * ixgbe_recv_pkts_lro - receive handler for and LRO case.
1984 * @rx_queue Rx queue handle
1985 * @rx_pkts table of received packets
1986 * @nb_pkts size of rx_pkts table
1987 * @bulk_alloc if TRUE bulk allocation is used for a HW ring refilling
1989 * Handles the Rx HW ring completions when RSC feature is configured. Uses an
1990 * additional ring of ixgbe_rsc_entry's that will hold the relevant RSC info.
1992 * We use the same logic as in Linux and in FreeBSD ixgbe drivers:
1993 * 1) When non-EOP RSC completion arrives:
1994 * a) Update the HEAD of the current RSC aggregation cluster with the new
1995 * segment's data length.
1996 * b) Set the "next" pointer of the current segment to point to the segment
1997 * at the NEXTP index.
1998 * c) Pass the HEAD of RSC aggregation cluster on to the next NEXTP entry
1999 * in the sw_rsc_ring.
2000 * 2) When EOP arrives we just update the cluster's total length and offload
2001 * flags and deliver the cluster up to the upper layers. In our case - put it
2002 * in the rx_pkts table.
2004 * Returns the number of received packets/clusters (according to the "bulk
2005 * receive" interface).
2007 static inline uint16_t
2008 ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
2011 struct ixgbe_rx_queue *rxq = rx_queue;
2012 volatile union ixgbe_adv_rx_desc *rx_ring = rxq->rx_ring;
2013 struct ixgbe_rx_entry *sw_ring = rxq->sw_ring;
2014 struct ixgbe_scattered_rx_entry *sw_sc_ring = rxq->sw_sc_ring;
2015 uint16_t rx_id = rxq->rx_tail;
2017 uint16_t nb_hold = rxq->nb_rx_hold;
2018 uint16_t prev_id = rxq->rx_tail;
2020 while (nb_rx < nb_pkts) {
2022 struct ixgbe_rx_entry *rxe;
2023 struct ixgbe_scattered_rx_entry *sc_entry;
2024 struct ixgbe_scattered_rx_entry *next_sc_entry;
2025 struct ixgbe_rx_entry *next_rxe = NULL;
2026 struct rte_mbuf *first_seg;
2027 struct rte_mbuf *rxm;
2028 struct rte_mbuf *nmb;
2029 union ixgbe_adv_rx_desc rxd;
2032 volatile union ixgbe_adv_rx_desc *rxdp;
2037 * The code in this whole file uses the volatile pointer to
2038 * ensure the read ordering of the status and the rest of the
2039 * descriptor fields (on the compiler level only!!!). This is so
2040 * UGLY - why not to just use the compiler barrier instead? DPDK
2041 * even has the rte_compiler_barrier() for that.
2043 * But most importantly this is just wrong because this doesn't
2044 * ensure memory ordering in a general case at all. For
2045 * instance, DPDK is supposed to work on Power CPUs where
2046 * compiler barrier may just not be enough!
2048 * I tried to write only this function properly to have a
2049 * starting point (as a part of an LRO/RSC series) but the
2050 * compiler cursed at me when I tried to cast away the
2051 * "volatile" from rx_ring (yes, it's volatile too!!!). So, I'm
2052 * keeping it the way it is for now.
2054 * The code in this file is broken in so many other places and
2055 * will just not work on a big endian CPU anyway therefore the
2056 * lines below will have to be revisited together with the rest
2060 * - Get rid of "volatile" crap and let the compiler do its
2062 * - Use the proper memory barrier (rte_rmb()) to ensure the
2063 * memory ordering below.
2065 rxdp = &rx_ring[rx_id];
2066 staterr = rte_le_to_cpu_32(rxdp->wb.upper.status_error);
2068 if (!(staterr & IXGBE_RXDADV_STAT_DD))
2073 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
2074 "staterr=0x%x data_len=%u",
2075 rxq->port_id, rxq->queue_id, rx_id, staterr,
2076 rte_le_to_cpu_16(rxd.wb.upper.length));
2079 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
2081 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed "
2082 "port_id=%u queue_id=%u",
2083 rxq->port_id, rxq->queue_id);
2085 rte_eth_devices[rxq->port_id].data->
2086 rx_mbuf_alloc_failed++;
2089 } else if (nb_hold > rxq->rx_free_thresh) {
2090 uint16_t next_rdt = rxq->rx_free_trigger;
2092 if (!ixgbe_rx_alloc_bufs(rxq, false)) {
2094 IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr,
2096 nb_hold -= rxq->rx_free_thresh;
2098 PMD_RX_LOG(DEBUG, "RX bulk alloc failed "
2099 "port_id=%u queue_id=%u",
2100 rxq->port_id, rxq->queue_id);
2102 rte_eth_devices[rxq->port_id].data->
2103 rx_mbuf_alloc_failed++;
2109 rxe = &sw_ring[rx_id];
2110 eop = staterr & IXGBE_RXDADV_STAT_EOP;
2112 next_id = rx_id + 1;
2113 if (next_id == rxq->nb_rx_desc)
2116 /* Prefetch next mbuf while processing current one. */
2117 rte_ixgbe_prefetch(sw_ring[next_id].mbuf);
2120 * When next RX descriptor is on a cache-line boundary,
2121 * prefetch the next 4 RX descriptors and the next 4 pointers
2124 if ((next_id & 0x3) == 0) {
2125 rte_ixgbe_prefetch(&rx_ring[next_id]);
2126 rte_ixgbe_prefetch(&sw_ring[next_id]);
2133 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2135 * Update RX descriptor with the physical address of the
2136 * new data buffer of the new allocated mbuf.
2140 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2141 rxdp->read.hdr_addr = 0;
2142 rxdp->read.pkt_addr = dma;
2147 * Set data length & data buffer address of mbuf.
2149 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
2150 rxm->data_len = data_len;
2155 * Get next descriptor index:
2156 * - For RSC it's in the NEXTP field.
2157 * - For a scattered packet - it's just a following
2160 if (ixgbe_rsc_count(&rxd))
2162 (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
2163 IXGBE_RXDADV_NEXTP_SHIFT;
2167 next_sc_entry = &sw_sc_ring[nextp_id];
2168 next_rxe = &sw_ring[nextp_id];
2169 rte_ixgbe_prefetch(next_rxe);
2172 sc_entry = &sw_sc_ring[rx_id];
2173 first_seg = sc_entry->fbuf;
2174 sc_entry->fbuf = NULL;
2177 * If this is the first buffer of the received packet,
2178 * set the pointer to the first mbuf of the packet and
2179 * initialize its context.
2180 * Otherwise, update the total length and the number of segments
2181 * of the current scattered packet, and update the pointer to
2182 * the last mbuf of the current packet.
2184 if (first_seg == NULL) {
2186 first_seg->pkt_len = data_len;
2187 first_seg->nb_segs = 1;
2189 first_seg->pkt_len += data_len;
2190 first_seg->nb_segs++;
2197 * If this is not the last buffer of the received packet, update
2198 * the pointer to the first mbuf at the NEXTP entry in the
2199 * sw_sc_ring and continue to parse the RX ring.
2201 if (!eop && next_rxe) {
2202 rxm->next = next_rxe->mbuf;
2203 next_sc_entry->fbuf = first_seg;
2207 /* Initialize the first mbuf of the returned packet */
2208 ixgbe_fill_cluster_head_buf(first_seg, &rxd, rxq, staterr);
2211 * Deal with the case, when HW CRC srip is disabled.
2212 * That can't happen when LRO is enabled, but still could
2213 * happen for scattered RX mode.
2215 first_seg->pkt_len -= rxq->crc_len;
2216 if (unlikely(rxm->data_len <= rxq->crc_len)) {
2217 struct rte_mbuf *lp;
2219 for (lp = first_seg; lp->next != rxm; lp = lp->next)
2222 first_seg->nb_segs--;
2223 lp->data_len -= rxq->crc_len - rxm->data_len;
2225 rte_pktmbuf_free_seg(rxm);
2227 rxm->data_len -= rxq->crc_len;
2229 /* Prefetch data of first segment, if configured to do so. */
2230 rte_packet_prefetch((char *)first_seg->buf_addr +
2231 first_seg->data_off);
2234 * Store the mbuf address into the next entry of the array
2235 * of returned packets.
2237 rx_pkts[nb_rx++] = first_seg;
2241 * Record index of the next RX descriptor to probe.
2243 rxq->rx_tail = rx_id;
2246 * If the number of free RX descriptors is greater than the RX free
2247 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
2249 * Update the RDT with the value of the last processed RX descriptor
2250 * minus 1, to guarantee that the RDT register is never equal to the
2251 * RDH register, which creates a "full" ring situtation from the
2252 * hardware point of view...
2254 if (!bulk_alloc && nb_hold > rxq->rx_free_thresh) {
2255 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
2256 "nb_hold=%u nb_rx=%u",
2257 rxq->port_id, rxq->queue_id, rx_id, nb_hold, nb_rx);
2260 IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr, prev_id);
2264 rxq->nb_rx_hold = nb_hold;
2269 ixgbe_recv_pkts_lro_single_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
2272 return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, false);
2276 ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
2279 return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, true);
2282 /*********************************************************************
2284 * Queue management functions
2286 **********************************************************************/
2288 static void __attribute__((cold))
2289 ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)
2293 if (txq->sw_ring != NULL) {
2294 for (i = 0; i < txq->nb_tx_desc; i++) {
2295 if (txq->sw_ring[i].mbuf != NULL) {
2296 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2297 txq->sw_ring[i].mbuf = NULL;
2303 static void __attribute__((cold))
2304 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
2307 txq->sw_ring != NULL)
2308 rte_free(txq->sw_ring);
2311 static void __attribute__((cold))
2312 ixgbe_tx_queue_release(struct ixgbe_tx_queue *txq)
2314 if (txq != NULL && txq->ops != NULL) {
2315 txq->ops->release_mbufs(txq);
2316 txq->ops->free_swring(txq);
2321 void __attribute__((cold))
2322 ixgbe_dev_tx_queue_release(void *txq)
2324 ixgbe_tx_queue_release(txq);
2327 /* (Re)set dynamic ixgbe_tx_queue fields to defaults */
2328 static void __attribute__((cold))
2329 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
2331 static const union ixgbe_adv_tx_desc zeroed_desc = {{0}};
2332 struct ixgbe_tx_entry *txe = txq->sw_ring;
2335 /* Zero out HW ring memory */
2336 for (i = 0; i < txq->nb_tx_desc; i++) {
2337 txq->tx_ring[i] = zeroed_desc;
2340 /* Initialize SW ring entries */
2341 prev = (uint16_t) (txq->nb_tx_desc - 1);
2342 for (i = 0; i < txq->nb_tx_desc; i++) {
2343 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
2345 txd->wb.status = rte_cpu_to_le_32(IXGBE_TXD_STAT_DD);
2348 txe[prev].next_id = i;
2352 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2353 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2356 txq->nb_tx_used = 0;
2358 * Always allow 1 descriptor to be un-allocated to avoid
2359 * a H/W race condition
2361 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2362 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2364 memset((void *)&txq->ctx_cache, 0,
2365 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
2368 static const struct ixgbe_txq_ops def_txq_ops = {
2369 .release_mbufs = ixgbe_tx_queue_release_mbufs,
2370 .free_swring = ixgbe_tx_free_swring,
2371 .reset = ixgbe_reset_tx_queue,
2374 /* Takes an ethdev and a queue and sets up the tx function to be used based on
2375 * the queue parameters. Used in tx_queue_setup by primary process and then
2376 * in dev_init by secondary process when attaching to an existing ethdev.
2378 void __attribute__((cold))
2379 ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)
2381 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2382 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS) &&
2383 #ifdef RTE_LIBRTE_SECURITY
2384 !(txq->using_ipsec) &&
2386 (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
2387 PMD_INIT_LOG(DEBUG, "Using simple tx code path");
2388 dev->tx_pkt_prepare = NULL;
2389 #ifdef RTE_IXGBE_INC_VECTOR
2390 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
2391 (rte_eal_process_type() != RTE_PROC_PRIMARY ||
2392 ixgbe_txq_vec_setup(txq) == 0)) {
2393 PMD_INIT_LOG(DEBUG, "Vector tx enabled.");
2394 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
2397 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
2399 PMD_INIT_LOG(DEBUG, "Using full-featured tx code path");
2401 " - txq_flags = %lx " "[IXGBE_SIMPLE_FLAGS=%lx]",
2402 (unsigned long)txq->txq_flags,
2403 (unsigned long)IXGBE_SIMPLE_FLAGS);
2405 " - tx_rs_thresh = %lu " "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
2406 (unsigned long)txq->tx_rs_thresh,
2407 (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST);
2408 dev->tx_pkt_burst = ixgbe_xmit_pkts;
2409 dev->tx_pkt_prepare = ixgbe_prep_pkts;
2413 int __attribute__((cold))
2414 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
2417 unsigned int socket_id,
2418 const struct rte_eth_txconf *tx_conf)
2420 const struct rte_memzone *tz;
2421 struct ixgbe_tx_queue *txq;
2422 struct ixgbe_hw *hw;
2423 uint16_t tx_rs_thresh, tx_free_thresh;
2425 PMD_INIT_FUNC_TRACE();
2426 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2429 * Validate number of transmit descriptors.
2430 * It must not exceed hardware maximum, and must be multiple
2433 if (nb_desc % IXGBE_TXD_ALIGN != 0 ||
2434 (nb_desc > IXGBE_MAX_RING_DESC) ||
2435 (nb_desc < IXGBE_MIN_RING_DESC)) {
2440 * The following two parameters control the setting of the RS bit on
2441 * transmit descriptors.
2442 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
2443 * descriptors have been used.
2444 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
2445 * descriptors are used or if the number of descriptors required
2446 * to transmit a packet is greater than the number of free TX
2448 * The following constraints must be satisfied:
2449 * tx_rs_thresh must be greater than 0.
2450 * tx_rs_thresh must be less than the size of the ring minus 2.
2451 * tx_rs_thresh must be less than or equal to tx_free_thresh.
2452 * tx_rs_thresh must be a divisor of the ring size.
2453 * tx_free_thresh must be greater than 0.
2454 * tx_free_thresh must be less than the size of the ring minus 3.
2455 * One descriptor in the TX ring is used as a sentinel to avoid a
2456 * H/W race condition, hence the maximum threshold constraints.
2457 * When set to zero use default values.
2459 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2460 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2461 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2462 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2463 if (tx_rs_thresh >= (nb_desc - 2)) {
2464 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
2465 "of TX descriptors minus 2. (tx_rs_thresh=%u "
2466 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2467 (int)dev->data->port_id, (int)queue_idx);
2470 if (tx_rs_thresh > DEFAULT_TX_RS_THRESH) {
2471 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less or equal than %u. "
2472 "(tx_rs_thresh=%u port=%d queue=%d)",
2473 DEFAULT_TX_RS_THRESH, (unsigned int)tx_rs_thresh,
2474 (int)dev->data->port_id, (int)queue_idx);
2477 if (tx_free_thresh >= (nb_desc - 3)) {
2478 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2479 "tx_free_thresh must be less than the number of "
2480 "TX descriptors minus 3. (tx_free_thresh=%u "
2481 "port=%d queue=%d)",
2482 (unsigned int)tx_free_thresh,
2483 (int)dev->data->port_id, (int)queue_idx);
2486 if (tx_rs_thresh > tx_free_thresh) {
2487 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
2488 "tx_free_thresh. (tx_free_thresh=%u "
2489 "tx_rs_thresh=%u port=%d queue=%d)",
2490 (unsigned int)tx_free_thresh,
2491 (unsigned int)tx_rs_thresh,
2492 (int)dev->data->port_id,
2496 if ((nb_desc % tx_rs_thresh) != 0) {
2497 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2498 "number of TX descriptors. (tx_rs_thresh=%u "
2499 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2500 (int)dev->data->port_id, (int)queue_idx);
2505 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
2506 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
2507 * by the NIC and all descriptors are written back after the NIC
2508 * accumulates WTHRESH descriptors.
2510 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2511 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2512 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
2513 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2514 (int)dev->data->port_id, (int)queue_idx);
2518 /* Free memory prior to re-allocation if needed... */
2519 if (dev->data->tx_queues[queue_idx] != NULL) {
2520 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
2521 dev->data->tx_queues[queue_idx] = NULL;
2524 /* First allocate the tx queue data structure */
2525 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct ixgbe_tx_queue),
2526 RTE_CACHE_LINE_SIZE, socket_id);
2531 * Allocate TX ring hardware descriptors. A memzone large enough to
2532 * handle the maximum ring size is allocated in order to allow for
2533 * resizing in later calls to the queue setup function.
2535 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2536 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
2537 IXGBE_ALIGN, socket_id);
2539 ixgbe_tx_queue_release(txq);
2543 txq->nb_tx_desc = nb_desc;
2544 txq->tx_rs_thresh = tx_rs_thresh;
2545 txq->tx_free_thresh = tx_free_thresh;
2546 txq->pthresh = tx_conf->tx_thresh.pthresh;
2547 txq->hthresh = tx_conf->tx_thresh.hthresh;
2548 txq->wthresh = tx_conf->tx_thresh.wthresh;
2549 txq->queue_id = queue_idx;
2550 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2551 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2552 txq->port_id = dev->data->port_id;
2553 txq->txq_flags = tx_conf->txq_flags;
2554 txq->ops = &def_txq_ops;
2555 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2556 #ifdef RTE_LIBRTE_SECURITY
2557 txq->using_ipsec = !!(dev->data->dev_conf.txmode.offloads &
2558 DEV_TX_OFFLOAD_SECURITY);
2562 * Modification to set VFTDT for virtual function if vf is detected
2564 if (hw->mac.type == ixgbe_mac_82599_vf ||
2565 hw->mac.type == ixgbe_mac_X540_vf ||
2566 hw->mac.type == ixgbe_mac_X550_vf ||
2567 hw->mac.type == ixgbe_mac_X550EM_x_vf ||
2568 hw->mac.type == ixgbe_mac_X550EM_a_vf)
2569 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
2571 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
2573 txq->tx_ring_phys_addr = tz->iova;
2574 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
2576 /* Allocate software ring */
2577 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
2578 sizeof(struct ixgbe_tx_entry) * nb_desc,
2579 RTE_CACHE_LINE_SIZE, socket_id);
2580 if (txq->sw_ring == NULL) {
2581 ixgbe_tx_queue_release(txq);
2584 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2585 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
2587 /* set up vector or scalar TX function as appropriate */
2588 ixgbe_set_tx_function(dev, txq);
2590 txq->ops->reset(txq);
2592 dev->data->tx_queues[queue_idx] = txq;
2599 * ixgbe_free_sc_cluster - free the not-yet-completed scattered cluster
2601 * The "next" pointer of the last segment of (not-yet-completed) RSC clusters
2602 * in the sw_rsc_ring is not set to NULL but rather points to the next
2603 * mbuf of this RSC aggregation (that has not been completed yet and still
2604 * resides on the HW ring). So, instead of calling for rte_pktmbuf_free() we
2605 * will just free first "nb_segs" segments of the cluster explicitly by calling
2606 * an rte_pktmbuf_free_seg().
2608 * @m scattered cluster head
2610 static void __attribute__((cold))
2611 ixgbe_free_sc_cluster(struct rte_mbuf *m)
2613 uint16_t i, nb_segs = m->nb_segs;
2614 struct rte_mbuf *next_seg;
2616 for (i = 0; i < nb_segs; i++) {
2618 rte_pktmbuf_free_seg(m);
2623 static void __attribute__((cold))
2624 ixgbe_rx_queue_release_mbufs(struct ixgbe_rx_queue *rxq)
2628 #ifdef RTE_IXGBE_INC_VECTOR
2629 /* SSE Vector driver has a different way of releasing mbufs. */
2630 if (rxq->rx_using_sse) {
2631 ixgbe_rx_queue_release_mbufs_vec(rxq);
2636 if (rxq->sw_ring != NULL) {
2637 for (i = 0; i < rxq->nb_rx_desc; i++) {
2638 if (rxq->sw_ring[i].mbuf != NULL) {
2639 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2640 rxq->sw_ring[i].mbuf = NULL;
2643 if (rxq->rx_nb_avail) {
2644 for (i = 0; i < rxq->rx_nb_avail; ++i) {
2645 struct rte_mbuf *mb;
2647 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2648 rte_pktmbuf_free_seg(mb);
2650 rxq->rx_nb_avail = 0;
2654 if (rxq->sw_sc_ring)
2655 for (i = 0; i < rxq->nb_rx_desc; i++)
2656 if (rxq->sw_sc_ring[i].fbuf) {
2657 ixgbe_free_sc_cluster(rxq->sw_sc_ring[i].fbuf);
2658 rxq->sw_sc_ring[i].fbuf = NULL;
2662 static void __attribute__((cold))
2663 ixgbe_rx_queue_release(struct ixgbe_rx_queue *rxq)
2666 ixgbe_rx_queue_release_mbufs(rxq);
2667 rte_free(rxq->sw_ring);
2668 rte_free(rxq->sw_sc_ring);
2673 void __attribute__((cold))
2674 ixgbe_dev_rx_queue_release(void *rxq)
2676 ixgbe_rx_queue_release(rxq);
2680 * Check if Rx Burst Bulk Alloc function can be used.
2682 * 0: the preconditions are satisfied and the bulk allocation function
2684 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2685 * function must be used.
2687 static inline int __attribute__((cold))
2688 check_rx_burst_bulk_alloc_preconditions(struct ixgbe_rx_queue *rxq)
2693 * Make sure the following pre-conditions are satisfied:
2694 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2695 * rxq->rx_free_thresh < rxq->nb_rx_desc
2696 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2697 * Scattered packets are not supported. This should be checked
2698 * outside of this function.
2700 if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
2701 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2702 "rxq->rx_free_thresh=%d, "
2703 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2704 rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
2706 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
2707 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2708 "rxq->rx_free_thresh=%d, "
2709 "rxq->nb_rx_desc=%d",
2710 rxq->rx_free_thresh, rxq->nb_rx_desc);
2712 } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
2713 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2714 "rxq->nb_rx_desc=%d, "
2715 "rxq->rx_free_thresh=%d",
2716 rxq->nb_rx_desc, rxq->rx_free_thresh);
2723 /* Reset dynamic ixgbe_rx_queue fields back to defaults */
2724 static void __attribute__((cold))
2725 ixgbe_reset_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_rx_queue *rxq)
2727 static const union ixgbe_adv_rx_desc zeroed_desc = {{0}};
2729 uint16_t len = rxq->nb_rx_desc;
2732 * By default, the Rx queue setup function allocates enough memory for
2733 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2734 * extra memory at the end of the descriptor ring to be zero'd out.
2736 if (adapter->rx_bulk_alloc_allowed)
2737 /* zero out extra memory */
2738 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2741 * Zero out HW ring memory. Zero out extra memory at the end of
2742 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2743 * reads extra memory as zeros.
2745 for (i = 0; i < len; i++) {
2746 rxq->rx_ring[i] = zeroed_desc;
2750 * initialize extra software ring entries. Space for these extra
2751 * entries is always allocated
2753 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2754 for (i = rxq->nb_rx_desc; i < len; ++i) {
2755 rxq->sw_ring[i].mbuf = &rxq->fake_mbuf;
2758 rxq->rx_nb_avail = 0;
2759 rxq->rx_next_avail = 0;
2760 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2762 rxq->nb_rx_hold = 0;
2763 rxq->pkt_first_seg = NULL;
2764 rxq->pkt_last_seg = NULL;
2766 #ifdef RTE_IXGBE_INC_VECTOR
2767 rxq->rxrearm_start = 0;
2768 rxq->rxrearm_nb = 0;
2773 ixgbe_is_vf(struct rte_eth_dev *dev)
2775 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2777 switch (hw->mac.type) {
2778 case ixgbe_mac_82599_vf:
2779 case ixgbe_mac_X540_vf:
2780 case ixgbe_mac_X550_vf:
2781 case ixgbe_mac_X550EM_x_vf:
2782 case ixgbe_mac_X550EM_a_vf:
2790 ixgbe_get_rx_queue_offloads(struct rte_eth_dev *dev)
2792 uint64_t offloads = 0;
2793 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2795 if (hw->mac.type != ixgbe_mac_82598EB)
2796 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2802 ixgbe_get_rx_port_offloads(struct rte_eth_dev *dev)
2805 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2807 offloads = DEV_RX_OFFLOAD_IPV4_CKSUM |
2808 DEV_RX_OFFLOAD_UDP_CKSUM |
2809 DEV_RX_OFFLOAD_TCP_CKSUM |
2810 DEV_RX_OFFLOAD_CRC_STRIP |
2811 DEV_RX_OFFLOAD_JUMBO_FRAME |
2812 DEV_RX_OFFLOAD_SCATTER;
2814 if (hw->mac.type == ixgbe_mac_82598EB)
2815 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2817 if (ixgbe_is_vf(dev) == 0)
2818 offloads |= (DEV_RX_OFFLOAD_VLAN_FILTER |
2819 DEV_RX_OFFLOAD_VLAN_EXTEND);
2822 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2825 if ((hw->mac.type == ixgbe_mac_82599EB ||
2826 hw->mac.type == ixgbe_mac_X540) &&
2827 !RTE_ETH_DEV_SRIOV(dev).active)
2828 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
2830 if (hw->mac.type == ixgbe_mac_82599EB ||
2831 hw->mac.type == ixgbe_mac_X540)
2832 offloads |= DEV_RX_OFFLOAD_MACSEC_STRIP;
2834 if (hw->mac.type == ixgbe_mac_X550 ||
2835 hw->mac.type == ixgbe_mac_X550EM_x ||
2836 hw->mac.type == ixgbe_mac_X550EM_a)
2837 offloads |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2839 #ifdef RTE_LIBRTE_SECURITY
2840 if (dev->security_ctx)
2841 offloads |= DEV_RX_OFFLOAD_SECURITY;
2848 ixgbe_check_rx_queue_offloads(struct rte_eth_dev *dev, uint64_t requested)
2850 uint64_t port_offloads = dev->data->dev_conf.rxmode.offloads;
2851 uint64_t queue_supported = ixgbe_get_rx_queue_offloads(dev);
2852 uint64_t port_supported = ixgbe_get_rx_port_offloads(dev);
2854 if ((requested & (queue_supported | port_supported)) != requested)
2857 if ((port_offloads ^ requested) & port_supported)
2863 int __attribute__((cold))
2864 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2867 unsigned int socket_id,
2868 const struct rte_eth_rxconf *rx_conf,
2869 struct rte_mempool *mp)
2871 const struct rte_memzone *rz;
2872 struct ixgbe_rx_queue *rxq;
2873 struct ixgbe_hw *hw;
2875 struct ixgbe_adapter *adapter =
2876 (struct ixgbe_adapter *)dev->data->dev_private;
2878 PMD_INIT_FUNC_TRACE();
2879 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2881 if (!ixgbe_check_rx_queue_offloads(dev, rx_conf->offloads)) {
2882 PMD_INIT_LOG(ERR, "%p: Rx queue offloads 0x%" PRIx64
2883 " don't match port offloads 0x%" PRIx64
2884 " or supported port offloads 0x%" PRIx64
2885 " or supported queue offloads 0x%" PRIx64,
2886 (void *)dev, rx_conf->offloads,
2887 dev->data->dev_conf.rxmode.offloads,
2888 ixgbe_get_rx_port_offloads(dev),
2889 ixgbe_get_rx_queue_offloads(dev));
2894 * Validate number of receive descriptors.
2895 * It must not exceed hardware maximum, and must be multiple
2898 if (nb_desc % IXGBE_RXD_ALIGN != 0 ||
2899 (nb_desc > IXGBE_MAX_RING_DESC) ||
2900 (nb_desc < IXGBE_MIN_RING_DESC)) {
2904 /* Free memory prior to re-allocation if needed... */
2905 if (dev->data->rx_queues[queue_idx] != NULL) {
2906 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2907 dev->data->rx_queues[queue_idx] = NULL;
2910 /* First allocate the rx queue data structure */
2911 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct ixgbe_rx_queue),
2912 RTE_CACHE_LINE_SIZE, socket_id);
2916 rxq->nb_rx_desc = nb_desc;
2917 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2918 rxq->queue_id = queue_idx;
2919 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2920 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2921 rxq->port_id = dev->data->port_id;
2922 rxq->crc_len = (uint8_t)((dev->data->dev_conf.rxmode.offloads &
2923 DEV_RX_OFFLOAD_CRC_STRIP) ? 0 : ETHER_CRC_LEN);
2924 rxq->drop_en = rx_conf->rx_drop_en;
2925 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2926 rxq->offloads = rx_conf->offloads;
2929 * The packet type in RX descriptor is different for different NICs.
2930 * Some bits are used for x550 but reserved for other NICS.
2931 * So set different masks for different NICs.
2933 if (hw->mac.type == ixgbe_mac_X550 ||
2934 hw->mac.type == ixgbe_mac_X550EM_x ||
2935 hw->mac.type == ixgbe_mac_X550EM_a ||
2936 hw->mac.type == ixgbe_mac_X550_vf ||
2937 hw->mac.type == ixgbe_mac_X550EM_x_vf ||
2938 hw->mac.type == ixgbe_mac_X550EM_a_vf)
2939 rxq->pkt_type_mask = IXGBE_PACKET_TYPE_MASK_X550;
2941 rxq->pkt_type_mask = IXGBE_PACKET_TYPE_MASK_82599;
2944 * Allocate RX ring hardware descriptors. A memzone large enough to
2945 * handle the maximum ring size is allocated in order to allow for
2946 * resizing in later calls to the queue setup function.
2948 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2949 RX_RING_SZ, IXGBE_ALIGN, socket_id);
2951 ixgbe_rx_queue_release(rxq);
2956 * Zero init all the descriptors in the ring.
2958 memset(rz->addr, 0, RX_RING_SZ);
2961 * Modified to setup VFRDT for Virtual Function
2963 if (hw->mac.type == ixgbe_mac_82599_vf ||
2964 hw->mac.type == ixgbe_mac_X540_vf ||
2965 hw->mac.type == ixgbe_mac_X550_vf ||
2966 hw->mac.type == ixgbe_mac_X550EM_x_vf ||
2967 hw->mac.type == ixgbe_mac_X550EM_a_vf) {
2969 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2971 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2974 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2976 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2979 rxq->rx_ring_phys_addr = rz->iova;
2980 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2983 * Certain constraints must be met in order to use the bulk buffer
2984 * allocation Rx burst function. If any of Rx queues doesn't meet them
2985 * the feature should be disabled for the whole port.
2987 if (check_rx_burst_bulk_alloc_preconditions(rxq)) {
2988 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Rx Bulk Alloc "
2989 "preconditions - canceling the feature for "
2990 "the whole port[%d]",
2991 rxq->queue_id, rxq->port_id);
2992 adapter->rx_bulk_alloc_allowed = false;
2996 * Allocate software ring. Allow for space at the end of the
2997 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2998 * function does not access an invalid memory region.
3001 if (adapter->rx_bulk_alloc_allowed)
3002 len += RTE_PMD_IXGBE_RX_MAX_BURST;
3004 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
3005 sizeof(struct ixgbe_rx_entry) * len,
3006 RTE_CACHE_LINE_SIZE, socket_id);
3007 if (!rxq->sw_ring) {
3008 ixgbe_rx_queue_release(rxq);
3013 * Always allocate even if it's not going to be needed in order to
3014 * simplify the code.
3016 * This ring is used in LRO and Scattered Rx cases and Scattered Rx may
3017 * be requested in ixgbe_dev_rx_init(), which is called later from
3021 rte_zmalloc_socket("rxq->sw_sc_ring",
3022 sizeof(struct ixgbe_scattered_rx_entry) * len,
3023 RTE_CACHE_LINE_SIZE, socket_id);
3024 if (!rxq->sw_sc_ring) {
3025 ixgbe_rx_queue_release(rxq);
3029 PMD_INIT_LOG(DEBUG, "sw_ring=%p sw_sc_ring=%p hw_ring=%p "
3030 "dma_addr=0x%"PRIx64,
3031 rxq->sw_ring, rxq->sw_sc_ring, rxq->rx_ring,
3032 rxq->rx_ring_phys_addr);
3034 if (!rte_is_power_of_2(nb_desc)) {
3035 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
3036 "preconditions - canceling the feature for "
3037 "the whole port[%d]",
3038 rxq->queue_id, rxq->port_id);
3039 adapter->rx_vec_allowed = false;
3041 ixgbe_rxq_vec_setup(rxq);
3043 dev->data->rx_queues[queue_idx] = rxq;
3045 ixgbe_reset_rx_queue(adapter, rxq);
3051 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3053 #define IXGBE_RXQ_SCAN_INTERVAL 4
3054 volatile union ixgbe_adv_rx_desc *rxdp;
3055 struct ixgbe_rx_queue *rxq;
3058 rxq = dev->data->rx_queues[rx_queue_id];
3059 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
3061 while ((desc < rxq->nb_rx_desc) &&
3062 (rxdp->wb.upper.status_error &
3063 rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))) {
3064 desc += IXGBE_RXQ_SCAN_INTERVAL;
3065 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
3066 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
3067 rxdp = &(rxq->rx_ring[rxq->rx_tail +
3068 desc - rxq->nb_rx_desc]);
3075 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
3077 volatile union ixgbe_adv_rx_desc *rxdp;
3078 struct ixgbe_rx_queue *rxq = rx_queue;
3081 if (unlikely(offset >= rxq->nb_rx_desc))
3083 desc = rxq->rx_tail + offset;
3084 if (desc >= rxq->nb_rx_desc)
3085 desc -= rxq->nb_rx_desc;
3087 rxdp = &rxq->rx_ring[desc];
3088 return !!(rxdp->wb.upper.status_error &
3089 rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD));
3093 ixgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
3095 struct ixgbe_rx_queue *rxq = rx_queue;
3096 volatile uint32_t *status;
3097 uint32_t nb_hold, desc;
3099 if (unlikely(offset >= rxq->nb_rx_desc))
3102 #ifdef RTE_IXGBE_INC_VECTOR
3103 if (rxq->rx_using_sse)
3104 nb_hold = rxq->rxrearm_nb;
3107 nb_hold = rxq->nb_rx_hold;
3108 if (offset >= rxq->nb_rx_desc - nb_hold)
3109 return RTE_ETH_RX_DESC_UNAVAIL;
3111 desc = rxq->rx_tail + offset;
3112 if (desc >= rxq->nb_rx_desc)
3113 desc -= rxq->nb_rx_desc;
3115 status = &rxq->rx_ring[desc].wb.upper.status_error;
3116 if (*status & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))
3117 return RTE_ETH_RX_DESC_DONE;
3119 return RTE_ETH_RX_DESC_AVAIL;
3123 ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
3125 struct ixgbe_tx_queue *txq = tx_queue;
3126 volatile uint32_t *status;
3129 if (unlikely(offset >= txq->nb_tx_desc))
3132 desc = txq->tx_tail + offset;
3133 /* go to next desc that has the RS bit */
3134 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
3136 if (desc >= txq->nb_tx_desc) {
3137 desc -= txq->nb_tx_desc;
3138 if (desc >= txq->nb_tx_desc)
3139 desc -= txq->nb_tx_desc;
3142 status = &txq->tx_ring[desc].wb.status;
3143 if (*status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD))
3144 return RTE_ETH_TX_DESC_DONE;
3146 return RTE_ETH_TX_DESC_FULL;
3149 void __attribute__((cold))
3150 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
3153 struct ixgbe_adapter *adapter =
3154 (struct ixgbe_adapter *)dev->data->dev_private;
3156 PMD_INIT_FUNC_TRACE();
3158 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3159 struct ixgbe_tx_queue *txq = dev->data->tx_queues[i];
3162 txq->ops->release_mbufs(txq);
3163 txq->ops->reset(txq);
3167 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3168 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
3171 ixgbe_rx_queue_release_mbufs(rxq);
3172 ixgbe_reset_rx_queue(adapter, rxq);
3178 ixgbe_dev_free_queues(struct rte_eth_dev *dev)
3182 PMD_INIT_FUNC_TRACE();
3184 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3185 ixgbe_dev_rx_queue_release(dev->data->rx_queues[i]);
3186 dev->data->rx_queues[i] = NULL;
3188 dev->data->nb_rx_queues = 0;
3190 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3191 ixgbe_dev_tx_queue_release(dev->data->tx_queues[i]);
3192 dev->data->tx_queues[i] = NULL;
3194 dev->data->nb_tx_queues = 0;
3197 /*********************************************************************
3199 * Device RX/TX init functions
3201 **********************************************************************/
3204 * Receive Side Scaling (RSS)
3205 * See section 7.1.2.8 in the following document:
3206 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
3209 * The source and destination IP addresses of the IP header and the source
3210 * and destination ports of TCP/UDP headers, if any, of received packets are
3211 * hashed against a configurable random key to compute a 32-bit RSS hash result.
3212 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
3213 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
3214 * RSS output index which is used as the RX queue index where to store the
3216 * The following output is supplied in the RX write-back descriptor:
3217 * - 32-bit result of the Microsoft RSS hash function,
3218 * - 4-bit RSS type field.
3222 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
3223 * Used as the default key.
3225 static uint8_t rss_intel_key[40] = {
3226 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
3227 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
3228 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
3229 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
3230 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
3234 ixgbe_rss_disable(struct rte_eth_dev *dev)
3236 struct ixgbe_hw *hw;
3240 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3241 mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3242 mrqc = IXGBE_READ_REG(hw, mrqc_reg);
3243 mrqc &= ~IXGBE_MRQC_RSSEN;
3244 IXGBE_WRITE_REG(hw, mrqc_reg, mrqc);
3248 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
3258 mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3259 rssrk_reg = ixgbe_rssrk_reg_get(hw->mac.type, 0);
3261 hash_key = rss_conf->rss_key;
3262 if (hash_key != NULL) {
3263 /* Fill in RSS hash key */
3264 for (i = 0; i < 10; i++) {
3265 rss_key = hash_key[(i * 4)];
3266 rss_key |= hash_key[(i * 4) + 1] << 8;
3267 rss_key |= hash_key[(i * 4) + 2] << 16;
3268 rss_key |= hash_key[(i * 4) + 3] << 24;
3269 IXGBE_WRITE_REG_ARRAY(hw, rssrk_reg, i, rss_key);
3273 /* Set configured hashing protocols in MRQC register */
3274 rss_hf = rss_conf->rss_hf;
3275 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
3276 if (rss_hf & ETH_RSS_IPV4)
3277 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
3278 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
3279 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
3280 if (rss_hf & ETH_RSS_IPV6)
3281 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
3282 if (rss_hf & ETH_RSS_IPV6_EX)
3283 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
3284 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
3285 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3286 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
3287 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
3288 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
3289 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3290 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
3291 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3292 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
3293 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
3294 IXGBE_WRITE_REG(hw, mrqc_reg, mrqc);
3298 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
3299 struct rte_eth_rss_conf *rss_conf)
3301 struct ixgbe_hw *hw;
3306 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3308 if (!ixgbe_rss_update_sp(hw->mac.type)) {
3309 PMD_DRV_LOG(ERR, "RSS hash update is not supported on this "
3313 mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3316 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
3317 * "RSS enabling cannot be done dynamically while it must be
3318 * preceded by a software reset"
3319 * Before changing anything, first check that the update RSS operation
3320 * does not attempt to disable RSS, if RSS was enabled at
3321 * initialization time, or does not attempt to enable RSS, if RSS was
3322 * disabled at initialization time.
3324 rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
3325 mrqc = IXGBE_READ_REG(hw, mrqc_reg);
3326 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
3327 if (rss_hf != 0) /* Enable RSS */
3329 return 0; /* Nothing to do */
3332 if (rss_hf == 0) /* Disable RSS */
3334 ixgbe_hw_rss_hash_set(hw, rss_conf);
3339 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
3340 struct rte_eth_rss_conf *rss_conf)
3342 struct ixgbe_hw *hw;
3351 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3352 mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3353 rssrk_reg = ixgbe_rssrk_reg_get(hw->mac.type, 0);
3354 hash_key = rss_conf->rss_key;
3355 if (hash_key != NULL) {
3356 /* Return RSS hash key */
3357 for (i = 0; i < 10; i++) {
3358 rss_key = IXGBE_READ_REG_ARRAY(hw, rssrk_reg, i);
3359 hash_key[(i * 4)] = rss_key & 0x000000FF;
3360 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
3361 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
3362 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
3366 /* Get RSS functions configured in MRQC register */
3367 mrqc = IXGBE_READ_REG(hw, mrqc_reg);
3368 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
3369 rss_conf->rss_hf = 0;
3373 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
3374 rss_hf |= ETH_RSS_IPV4;
3375 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
3376 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
3377 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
3378 rss_hf |= ETH_RSS_IPV6;
3379 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
3380 rss_hf |= ETH_RSS_IPV6_EX;
3381 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
3382 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
3383 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
3384 rss_hf |= ETH_RSS_IPV6_TCP_EX;
3385 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
3386 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
3387 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
3388 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
3389 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
3390 rss_hf |= ETH_RSS_IPV6_UDP_EX;
3391 rss_conf->rss_hf = rss_hf;
3396 ixgbe_rss_configure(struct rte_eth_dev *dev)
3398 struct rte_eth_rss_conf rss_conf;
3399 struct ixgbe_hw *hw;
3403 uint16_t sp_reta_size;
3406 PMD_INIT_FUNC_TRACE();
3407 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3409 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3412 * Fill in redirection table
3413 * The byte-swap is needed because NIC registers are in
3414 * little-endian order.
3417 for (i = 0, j = 0; i < sp_reta_size; i++, j++) {
3418 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3420 if (j == dev->data->nb_rx_queues)
3422 reta = (reta << 8) | j;
3424 IXGBE_WRITE_REG(hw, reta_reg,
3429 * Configure the RSS key and the RSS protocols used to compute
3430 * the RSS hash of input packets.
3432 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
3433 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
3434 ixgbe_rss_disable(dev);
3437 if (rss_conf.rss_key == NULL)
3438 rss_conf.rss_key = rss_intel_key; /* Default hash key */
3439 ixgbe_hw_rss_hash_set(hw, &rss_conf);
3442 #define NUM_VFTA_REGISTERS 128
3443 #define NIC_RX_BUFFER_SIZE 0x200
3444 #define X550_RX_BUFFER_SIZE 0x180
3447 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
3449 struct rte_eth_vmdq_dcb_conf *cfg;
3450 struct ixgbe_hw *hw;
3451 enum rte_eth_nb_pools num_pools;
3452 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
3454 uint8_t nb_tcs; /* number of traffic classes */
3457 PMD_INIT_FUNC_TRACE();
3458 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3459 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3460 num_pools = cfg->nb_queue_pools;
3461 /* Check we have a valid number of pools */
3462 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
3463 ixgbe_rss_disable(dev);
3466 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
3467 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
3471 * split rx buffer up into sections, each for 1 traffic class
3473 switch (hw->mac.type) {
3474 case ixgbe_mac_X550:
3475 case ixgbe_mac_X550EM_x:
3476 case ixgbe_mac_X550EM_a:
3477 pbsize = (uint16_t)(X550_RX_BUFFER_SIZE / nb_tcs);
3480 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3483 for (i = 0; i < nb_tcs; i++) {
3484 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
3486 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
3487 /* clear 10 bits. */
3488 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
3489 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3491 /* zero alloc all unused TCs */
3492 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3493 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
3495 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
3496 /* clear 10 bits. */
3497 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3500 /* MRQC: enable vmdq and dcb */
3501 mrqc = (num_pools == ETH_16_POOLS) ?
3502 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN;
3503 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3505 /* PFVTCTL: turn on virtualisation and set the default pool */
3506 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3507 if (cfg->enable_default_pool) {
3508 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3510 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3513 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3515 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
3517 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
3519 * mapping is done with 3 bits per priority,
3520 * so shift by i*3 each time
3522 queue_mapping |= ((cfg->dcb_tc[i] & 0x07) << (i * 3));
3524 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
3526 /* RTRPCS: DCB related */
3527 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
3529 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3530 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3531 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
3532 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3534 /* VFTA - enable all vlan filters */
3535 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3536 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3539 /* VFRE: pool enabling for receive - 16 or 32 */
3540 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0),
3541 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3544 * MPSAR - allow pools to read specific mac addresses
3545 * In this case, all pools should be able to read from mac addr 0
3547 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
3548 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
3550 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3551 for (i = 0; i < cfg->nb_pool_maps; i++) {
3552 /* set vlan id in VF register and set the valid bit */
3553 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN |
3554 (cfg->pool_map[i].vlan_id & 0xFFF)));
3556 * Put the allowed pools in VFB reg. As we only have 16 or 32
3557 * pools, we only need to use the first half of the register
3560 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
3565 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
3566 * @dev: pointer to eth_dev structure
3567 * @dcb_config: pointer to ixgbe_dcb_config structure
3570 ixgbe_dcb_tx_hw_config(struct rte_eth_dev *dev,
3571 struct ixgbe_dcb_config *dcb_config)
3574 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3576 PMD_INIT_FUNC_TRACE();
3577 if (hw->mac.type != ixgbe_mac_82598EB) {
3578 /* Disable the Tx desc arbiter so that MTQC can be changed */
3579 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3580 reg |= IXGBE_RTTDCS_ARBDIS;
3581 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3583 /* Enable DCB for Tx with 8 TCs */
3584 if (dcb_config->num_tcs.pg_tcs == 8) {
3585 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3587 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3589 if (dcb_config->vt_mode)
3590 reg |= IXGBE_MTQC_VT_ENA;
3591 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3593 /* Enable the Tx desc arbiter */
3594 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3595 reg &= ~IXGBE_RTTDCS_ARBDIS;
3596 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3598 /* Enable Security TX Buffer IFG for DCB */
3599 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3600 reg |= IXGBE_SECTX_DCB;
3601 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
3606 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
3607 * @dev: pointer to rte_eth_dev structure
3608 * @dcb_config: pointer to ixgbe_dcb_config structure
3611 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
3612 struct ixgbe_dcb_config *dcb_config)
3614 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3615 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3616 struct ixgbe_hw *hw =
3617 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3619 PMD_INIT_FUNC_TRACE();
3620 if (hw->mac.type != ixgbe_mac_82598EB)
3621 /*PF VF Transmit Enable*/
3622 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
3623 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3625 /*Configure general DCB TX parameters*/
3626 ixgbe_dcb_tx_hw_config(dev, dcb_config);
3630 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
3631 struct ixgbe_dcb_config *dcb_config)
3633 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
3634 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3635 struct ixgbe_dcb_tc_config *tc;
3638 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3639 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS) {
3640 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3641 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3643 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3644 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3647 /* Initialize User Priority to Traffic Class mapping */
3648 for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3649 tc = &dcb_config->tc_config[j];
3650 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0;
3653 /* User Priority to Traffic Class mapping */
3654 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3655 j = vmdq_rx_conf->dcb_tc[i];
3656 tc = &dcb_config->tc_config[j];
3657 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap |=
3663 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
3664 struct ixgbe_dcb_config *dcb_config)
3666 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3667 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3668 struct ixgbe_dcb_tc_config *tc;
3671 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3672 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS) {
3673 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3674 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3676 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3677 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3680 /* Initialize User Priority to Traffic Class mapping */
3681 for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3682 tc = &dcb_config->tc_config[j];
3683 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0;
3686 /* User Priority to Traffic Class mapping */
3687 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3688 j = vmdq_tx_conf->dcb_tc[i];
3689 tc = &dcb_config->tc_config[j];
3690 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap |=
3696 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
3697 struct ixgbe_dcb_config *dcb_config)
3699 struct rte_eth_dcb_rx_conf *rx_conf =
3700 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
3701 struct ixgbe_dcb_tc_config *tc;
3704 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
3705 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
3707 /* Initialize User Priority to Traffic Class mapping */
3708 for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3709 tc = &dcb_config->tc_config[j];
3710 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0;
3713 /* User Priority to Traffic Class mapping */
3714 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3715 j = rx_conf->dcb_tc[i];
3716 tc = &dcb_config->tc_config[j];
3717 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap |=
3723 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
3724 struct ixgbe_dcb_config *dcb_config)
3726 struct rte_eth_dcb_tx_conf *tx_conf =
3727 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
3728 struct ixgbe_dcb_tc_config *tc;
3731 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
3732 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
3734 /* Initialize User Priority to Traffic Class mapping */
3735 for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3736 tc = &dcb_config->tc_config[j];
3737 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0;
3740 /* User Priority to Traffic Class mapping */
3741 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3742 j = tx_conf->dcb_tc[i];
3743 tc = &dcb_config->tc_config[j];
3744 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap |=
3750 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
3751 * @dev: pointer to eth_dev structure
3752 * @dcb_config: pointer to ixgbe_dcb_config structure
3755 ixgbe_dcb_rx_hw_config(struct rte_eth_dev *dev,
3756 struct ixgbe_dcb_config *dcb_config)
3762 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3764 PMD_INIT_FUNC_TRACE();
3766 * Disable the arbiter before changing parameters
3767 * (always enable recycle mode; WSP)
3769 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
3770 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3772 if (hw->mac.type != ixgbe_mac_82598EB) {
3773 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
3774 if (dcb_config->num_tcs.pg_tcs == 4) {
3775 if (dcb_config->vt_mode)
3776 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3777 IXGBE_MRQC_VMDQRT4TCEN;
3779 /* no matter the mode is DCB or DCB_RSS, just
3780 * set the MRQE to RSSXTCEN. RSS is controlled
3783 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3784 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3785 IXGBE_MRQC_RTRSS4TCEN;
3788 if (dcb_config->num_tcs.pg_tcs == 8) {
3789 if (dcb_config->vt_mode)
3790 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3791 IXGBE_MRQC_VMDQRT8TCEN;
3793 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3794 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3795 IXGBE_MRQC_RTRSS8TCEN;
3799 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
3801 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3802 /* Disable drop for all queues in VMDQ mode*/
3803 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3804 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3806 (q << IXGBE_QDE_IDX_SHIFT)));
3808 /* Enable drop for all queues in SRIOV mode */
3809 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3810 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3812 (q << IXGBE_QDE_IDX_SHIFT) |
3817 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3818 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3819 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
3820 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3822 /* VFTA - enable all vlan filters */
3823 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3824 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3828 * Configure Rx packet plane (recycle mode; WSP) and
3831 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
3832 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3836 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
3837 uint16_t *max, uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3839 switch (hw->mac.type) {
3840 case ixgbe_mac_82598EB:
3841 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
3843 case ixgbe_mac_82599EB:
3844 case ixgbe_mac_X540:
3845 case ixgbe_mac_X550:
3846 case ixgbe_mac_X550EM_x:
3847 case ixgbe_mac_X550EM_a:
3848 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
3857 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
3858 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3860 switch (hw->mac.type) {
3861 case ixgbe_mac_82598EB:
3862 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id, tsa);
3863 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id, tsa);
3865 case ixgbe_mac_82599EB:
3866 case ixgbe_mac_X540:
3867 case ixgbe_mac_X550:
3868 case ixgbe_mac_X550EM_x:
3869 case ixgbe_mac_X550EM_a:
3870 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id, tsa);
3871 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id, tsa, map);
3878 #define DCB_RX_CONFIG 1
3879 #define DCB_TX_CONFIG 1
3880 #define DCB_TX_PB 1024
3882 * ixgbe_dcb_hw_configure - Enable DCB and configure
3883 * general DCB in VT mode and non-VT mode parameters
3884 * @dev: pointer to rte_eth_dev structure
3885 * @dcb_config: pointer to ixgbe_dcb_config structure
3888 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
3889 struct ixgbe_dcb_config *dcb_config)
3892 uint8_t i, pfc_en, nb_tcs;
3893 uint16_t pbsize, rx_buffer_size;
3894 uint8_t config_dcb_rx = 0;
3895 uint8_t config_dcb_tx = 0;
3896 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3897 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3898 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3899 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3900 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3901 struct ixgbe_dcb_tc_config *tc;
3902 uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3903 struct ixgbe_hw *hw =
3904 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3905 struct ixgbe_bw_conf *bw_conf =
3906 IXGBE_DEV_PRIVATE_TO_BW_CONF(dev->data->dev_private);
3908 switch (dev->data->dev_conf.rxmode.mq_mode) {
3909 case ETH_MQ_RX_VMDQ_DCB:
3910 dcb_config->vt_mode = true;
3911 if (hw->mac.type != ixgbe_mac_82598EB) {
3912 config_dcb_rx = DCB_RX_CONFIG;
3914 *get dcb and VT rx configuration parameters
3917 ixgbe_vmdq_dcb_rx_config(dev, dcb_config);
3918 /*Configure general VMDQ and DCB RX parameters*/
3919 ixgbe_vmdq_dcb_configure(dev);
3923 case ETH_MQ_RX_DCB_RSS:
3924 dcb_config->vt_mode = false;
3925 config_dcb_rx = DCB_RX_CONFIG;
3926 /* Get dcb TX configuration parameters from rte_eth_conf */
3927 ixgbe_dcb_rx_config(dev, dcb_config);
3928 /*Configure general DCB RX parameters*/
3929 ixgbe_dcb_rx_hw_config(dev, dcb_config);
3932 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
3935 switch (dev->data->dev_conf.txmode.mq_mode) {
3936 case ETH_MQ_TX_VMDQ_DCB:
3937 dcb_config->vt_mode = true;
3938 config_dcb_tx = DCB_TX_CONFIG;
3939 /* get DCB and VT TX configuration parameters
3942 ixgbe_dcb_vt_tx_config(dev, dcb_config);
3943 /*Configure general VMDQ and DCB TX parameters*/
3944 ixgbe_vmdq_dcb_hw_tx_config(dev, dcb_config);
3948 dcb_config->vt_mode = false;
3949 config_dcb_tx = DCB_TX_CONFIG;
3950 /*get DCB TX configuration parameters from rte_eth_conf*/
3951 ixgbe_dcb_tx_config(dev, dcb_config);
3952 /*Configure general DCB TX parameters*/
3953 ixgbe_dcb_tx_hw_config(dev, dcb_config);
3956 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
3960 nb_tcs = dcb_config->num_tcs.pfc_tcs;
3962 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3963 if (nb_tcs == ETH_4_TCS) {
3964 /* Avoid un-configured priority mapping to TC0 */
3966 uint8_t mask = 0xFF;
3968 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
3969 mask = (uint8_t)(mask & (~(1 << map[i])));
3970 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
3971 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
3975 /* Re-configure 4 TCs BW */
3976 for (i = 0; i < nb_tcs; i++) {
3977 tc = &dcb_config->tc_config[i];
3978 if (bw_conf->tc_num != nb_tcs)
3979 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
3980 (uint8_t)(100 / nb_tcs);
3981 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
3982 (uint8_t)(100 / nb_tcs);
3984 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3985 tc = &dcb_config->tc_config[i];
3986 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
3987 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
3990 /* Re-configure 8 TCs BW */
3991 for (i = 0; i < nb_tcs; i++) {
3992 tc = &dcb_config->tc_config[i];
3993 if (bw_conf->tc_num != nb_tcs)
3994 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
3995 (uint8_t)(100 / nb_tcs + (i & 1));
3996 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
3997 (uint8_t)(100 / nb_tcs + (i & 1));
4001 switch (hw->mac.type) {
4002 case ixgbe_mac_X550:
4003 case ixgbe_mac_X550EM_x:
4004 case ixgbe_mac_X550EM_a:
4005 rx_buffer_size = X550_RX_BUFFER_SIZE;
4008 rx_buffer_size = NIC_RX_BUFFER_SIZE;
4012 if (config_dcb_rx) {
4013 /* Set RX buffer size */
4014 pbsize = (uint16_t)(rx_buffer_size / nb_tcs);
4015 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
4017 for (i = 0; i < nb_tcs; i++) {
4018 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
4020 /* zero alloc all unused TCs */
4021 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
4022 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4025 if (config_dcb_tx) {
4026 /* Only support an equally distributed
4027 * Tx packet buffer strategy.
4029 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
4030 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
4032 for (i = 0; i < nb_tcs; i++) {
4033 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4034 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4036 /* Clear unused TCs, if any, to zero buffer size*/
4037 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
4038 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4039 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4043 /*Calculates traffic class credits*/
4044 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config, max_frame,
4045 IXGBE_DCB_TX_CONFIG);
4046 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config, max_frame,
4047 IXGBE_DCB_RX_CONFIG);
4049 if (config_dcb_rx) {
4050 /* Unpack CEE standard containers */
4051 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
4052 ixgbe_dcb_unpack_max_cee(dcb_config, max);
4053 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
4054 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
4055 /* Configure PG(ETS) RX */
4056 ixgbe_dcb_hw_arbite_rx_config(hw, refill, max, bwgid, tsa, map);
4059 if (config_dcb_tx) {
4060 /* Unpack CEE standard containers */
4061 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
4062 ixgbe_dcb_unpack_max_cee(dcb_config, max);
4063 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
4064 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
4065 /* Configure PG(ETS) TX */
4066 ixgbe_dcb_hw_arbite_tx_config(hw, refill, max, bwgid, tsa, map);
4069 /*Configure queue statistics registers*/
4070 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
4072 /* Check if the PFC is supported */
4073 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
4074 pbsize = (uint16_t)(rx_buffer_size / nb_tcs);
4075 for (i = 0; i < nb_tcs; i++) {
4077 * If the TC count is 8,and the default high_water is 48,
4078 * the low_water is 16 as default.
4080 hw->fc.high_water[i] = (pbsize * 3) / 4;
4081 hw->fc.low_water[i] = pbsize / 4;
4082 /* Enable pfc for this TC */
4083 tc = &dcb_config->tc_config[i];
4084 tc->pfc = ixgbe_dcb_pfc_enabled;
4086 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
4087 if (dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
4089 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
4096 * ixgbe_configure_dcb - Configure DCB Hardware
4097 * @dev: pointer to rte_eth_dev
4099 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
4101 struct ixgbe_dcb_config *dcb_cfg =
4102 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4103 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
4105 PMD_INIT_FUNC_TRACE();
4107 /* check support mq_mode for DCB */
4108 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
4109 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB) &&
4110 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB_RSS))
4113 if (dev->data->nb_rx_queues > ETH_DCB_NUM_QUEUES)
4116 /** Configure DCB hardware **/
4117 ixgbe_dcb_hw_configure(dev, dcb_cfg);
4121 * VMDq only support for 10 GbE NIC.
4124 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
4126 struct rte_eth_vmdq_rx_conf *cfg;
4127 struct ixgbe_hw *hw;
4128 enum rte_eth_nb_pools num_pools;
4129 uint32_t mrqc, vt_ctl, vlanctrl;
4133 PMD_INIT_FUNC_TRACE();
4134 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4135 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
4136 num_pools = cfg->nb_queue_pools;
4138 ixgbe_rss_disable(dev);
4140 /* MRQC: enable vmdq */
4141 mrqc = IXGBE_MRQC_VMDQEN;
4142 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
4144 /* PFVTCTL: turn on virtualisation and set the default pool */
4145 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
4146 if (cfg->enable_default_pool)
4147 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
4149 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
4151 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
4153 for (i = 0; i < (int)num_pools; i++) {
4154 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
4155 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
4158 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
4159 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4160 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
4161 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
4163 /* VFTA - enable all vlan filters */
4164 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
4165 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
4167 /* VFRE: pool enabling for receive - 64 */
4168 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
4169 if (num_pools == ETH_64_POOLS)
4170 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
4173 * MPSAR - allow pools to read specific mac addresses
4174 * In this case, all pools should be able to read from mac addr 0
4176 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
4177 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
4179 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
4180 for (i = 0; i < cfg->nb_pool_maps; i++) {
4181 /* set vlan id in VF register and set the valid bit */
4182 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN |
4183 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
4185 * Put the allowed pools in VFB reg. As we only have 16 or 64
4186 * pools, we only need to use the first half of the register
4189 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
4190 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i * 2),
4191 (cfg->pool_map[i].pools & UINT32_MAX));
4193 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i * 2 + 1)),
4194 ((cfg->pool_map[i].pools >> 32) & UINT32_MAX));
4198 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
4199 if (cfg->enable_loop_back) {
4200 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
4201 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
4202 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
4205 IXGBE_WRITE_FLUSH(hw);
4209 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
4210 * @hw: pointer to hardware structure
4213 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
4218 PMD_INIT_FUNC_TRACE();
4219 /*PF VF Transmit Enable*/
4220 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
4221 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
4223 /* Disable the Tx desc arbiter so that MTQC can be changed */
4224 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
4225 reg |= IXGBE_RTTDCS_ARBDIS;
4226 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
4228 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
4229 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
4231 /* Disable drop for all queues */
4232 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
4233 IXGBE_WRITE_REG(hw, IXGBE_QDE,
4234 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
4236 /* Enable the Tx desc arbiter */
4237 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
4238 reg &= ~IXGBE_RTTDCS_ARBDIS;
4239 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
4241 IXGBE_WRITE_FLUSH(hw);
4244 static int __attribute__((cold))
4245 ixgbe_alloc_rx_queue_mbufs(struct ixgbe_rx_queue *rxq)
4247 struct ixgbe_rx_entry *rxe = rxq->sw_ring;
4251 /* Initialize software ring entries */
4252 for (i = 0; i < rxq->nb_rx_desc; i++) {
4253 volatile union ixgbe_adv_rx_desc *rxd;
4254 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
4257 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
4258 (unsigned) rxq->queue_id);
4262 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
4263 mbuf->port = rxq->port_id;
4266 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
4267 rxd = &rxq->rx_ring[i];
4268 rxd->read.hdr_addr = 0;
4269 rxd->read.pkt_addr = dma_addr;
4277 ixgbe_config_vf_rss(struct rte_eth_dev *dev)
4279 struct ixgbe_hw *hw;
4282 ixgbe_rss_configure(dev);
4284 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4286 /* MRQC: enable VF RSS */
4287 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
4288 mrqc &= ~IXGBE_MRQC_MRQE_MASK;
4289 switch (RTE_ETH_DEV_SRIOV(dev).active) {
4291 mrqc |= IXGBE_MRQC_VMDQRSS64EN;
4295 mrqc |= IXGBE_MRQC_VMDQRSS32EN;
4299 PMD_INIT_LOG(ERR, "Invalid pool number in IOV mode with VMDQ RSS");
4303 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
4309 ixgbe_config_vf_default(struct rte_eth_dev *dev)
4311 struct ixgbe_hw *hw =
4312 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4314 switch (RTE_ETH_DEV_SRIOV(dev).active) {
4316 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
4321 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
4322 IXGBE_MRQC_VMDQRT4TCEN);
4326 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
4327 IXGBE_MRQC_VMDQRT8TCEN);
4331 "invalid pool number in IOV mode");
4338 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
4340 struct ixgbe_hw *hw =
4341 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4343 if (hw->mac.type == ixgbe_mac_82598EB)
4346 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
4348 * SRIOV inactive scheme
4349 * any DCB/RSS w/o VMDq multi-queue setting
4351 switch (dev->data->dev_conf.rxmode.mq_mode) {
4353 case ETH_MQ_RX_DCB_RSS:
4354 case ETH_MQ_RX_VMDQ_RSS:
4355 ixgbe_rss_configure(dev);
4358 case ETH_MQ_RX_VMDQ_DCB:
4359 ixgbe_vmdq_dcb_configure(dev);
4362 case ETH_MQ_RX_VMDQ_ONLY:
4363 ixgbe_vmdq_rx_hw_configure(dev);
4366 case ETH_MQ_RX_NONE:
4368 /* if mq_mode is none, disable rss mode.*/
4369 ixgbe_rss_disable(dev);
4373 /* SRIOV active scheme
4374 * Support RSS together with SRIOV.
4376 switch (dev->data->dev_conf.rxmode.mq_mode) {
4378 case ETH_MQ_RX_VMDQ_RSS:
4379 ixgbe_config_vf_rss(dev);
4381 case ETH_MQ_RX_VMDQ_DCB:
4383 /* In SRIOV, the configuration is the same as VMDq case */
4384 ixgbe_vmdq_dcb_configure(dev);
4386 /* DCB/RSS together with SRIOV is not supported */
4387 case ETH_MQ_RX_VMDQ_DCB_RSS:
4388 case ETH_MQ_RX_DCB_RSS:
4390 "Could not support DCB/RSS with VMDq & SRIOV");
4393 ixgbe_config_vf_default(dev);
4402 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
4404 struct ixgbe_hw *hw =
4405 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4409 if (hw->mac.type == ixgbe_mac_82598EB)
4412 /* disable arbiter before setting MTQC */
4413 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
4414 rttdcs |= IXGBE_RTTDCS_ARBDIS;
4415 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
4417 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
4419 * SRIOV inactive scheme
4420 * any DCB w/o VMDq multi-queue setting
4422 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
4423 ixgbe_vmdq_tx_hw_configure(hw);
4425 mtqc = IXGBE_MTQC_64Q_1PB;
4426 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
4429 switch (RTE_ETH_DEV_SRIOV(dev).active) {
4432 * SRIOV active scheme
4433 * FIXME if support DCB together with VMDq & SRIOV
4436 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
4439 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
4442 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
4446 mtqc = IXGBE_MTQC_64Q_1PB;
4447 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
4449 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
4452 /* re-enable arbiter */
4453 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
4454 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
4460 * ixgbe_get_rscctl_maxdesc - Calculate the RSCCTL[n].MAXDESC for PF
4462 * Return the RSCCTL[n].MAXDESC for 82599 and x540 PF devices according to the
4463 * spec rev. 3.0 chapter 8.2.3.8.13.
4465 * @pool Memory pool of the Rx queue
4467 static inline uint32_t
4468 ixgbe_get_rscctl_maxdesc(struct rte_mempool *pool)
4470 struct rte_pktmbuf_pool_private *mp_priv = rte_mempool_get_priv(pool);
4472 /* MAXDESC * SRRCTL.BSIZEPKT must not exceed 64 KB minus one */
4475 (mp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM);
4478 return IXGBE_RSCCTL_MAXDESC_16;
4479 else if (maxdesc >= 8)
4480 return IXGBE_RSCCTL_MAXDESC_8;
4481 else if (maxdesc >= 4)
4482 return IXGBE_RSCCTL_MAXDESC_4;
4484 return IXGBE_RSCCTL_MAXDESC_1;
4488 * ixgbe_set_ivar - Setup the correct IVAR register for a particular MSIX
4491 * (Taken from FreeBSD tree)
4492 * (yes this is all very magic and confusing :)
4495 * @entry the register array entry
4496 * @vector the MSIX vector for this queue
4500 ixgbe_set_ivar(struct rte_eth_dev *dev, u8 entry, u8 vector, s8 type)
4502 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4505 vector |= IXGBE_IVAR_ALLOC_VAL;
4507 switch (hw->mac.type) {
4509 case ixgbe_mac_82598EB:
4511 entry = IXGBE_IVAR_OTHER_CAUSES_INDEX;
4513 entry += (type * 64);
4514 index = (entry >> 2) & 0x1F;
4515 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
4516 ivar &= ~(0xFF << (8 * (entry & 0x3)));
4517 ivar |= (vector << (8 * (entry & 0x3)));
4518 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
4521 case ixgbe_mac_82599EB:
4522 case ixgbe_mac_X540:
4523 if (type == -1) { /* MISC IVAR */
4524 index = (entry & 1) * 8;
4525 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4526 ivar &= ~(0xFF << index);
4527 ivar |= (vector << index);
4528 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
4529 } else { /* RX/TX IVARS */
4530 index = (16 * (entry & 1)) + (8 * type);
4531 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1));
4532 ivar &= ~(0xFF << index);
4533 ivar |= (vector << index);
4534 IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar);
4544 void __attribute__((cold))
4545 ixgbe_set_rx_function(struct rte_eth_dev *dev)
4547 uint16_t i, rx_using_sse;
4548 struct ixgbe_adapter *adapter =
4549 (struct ixgbe_adapter *)dev->data->dev_private;
4552 * In order to allow Vector Rx there are a few configuration
4553 * conditions to be met and Rx Bulk Allocation should be allowed.
4555 if (ixgbe_rx_vec_dev_conf_condition_check(dev) ||
4556 !adapter->rx_bulk_alloc_allowed) {
4557 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx "
4558 "preconditions or RTE_IXGBE_INC_VECTOR is "
4560 dev->data->port_id);
4562 adapter->rx_vec_allowed = false;
4566 * Initialize the appropriate LRO callback.
4568 * If all queues satisfy the bulk allocation preconditions
4569 * (hw->rx_bulk_alloc_allowed is TRUE) then we may use bulk allocation.
4570 * Otherwise use a single allocation version.
4572 if (dev->data->lro) {
4573 if (adapter->rx_bulk_alloc_allowed) {
4574 PMD_INIT_LOG(DEBUG, "LRO is requested. Using a bulk "
4575 "allocation version");
4576 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
4578 PMD_INIT_LOG(DEBUG, "LRO is requested. Using a single "
4579 "allocation version");
4580 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
4582 } else if (dev->data->scattered_rx) {
4584 * Set the non-LRO scattered callback: there are Vector and
4585 * single allocation versions.
4587 if (adapter->rx_vec_allowed) {
4588 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
4589 "callback (port=%d).",
4590 dev->data->port_id);
4592 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
4593 } else if (adapter->rx_bulk_alloc_allowed) {
4594 PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
4595 "allocation callback (port=%d).",
4596 dev->data->port_id);
4597 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
4599 PMD_INIT_LOG(DEBUG, "Using Regualr (non-vector, "
4600 "single allocation) "
4601 "Scattered Rx callback "
4603 dev->data->port_id);
4605 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
4608 * Below we set "simple" callbacks according to port/queues parameters.
4609 * If parameters allow we are going to choose between the following
4613 * - Single buffer allocation (the simplest one)
4615 } else if (adapter->rx_vec_allowed) {
4616 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
4617 "burst size no less than %d (port=%d).",
4618 RTE_IXGBE_DESCS_PER_LOOP,
4619 dev->data->port_id);
4621 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
4622 } else if (adapter->rx_bulk_alloc_allowed) {
4623 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
4624 "satisfied. Rx Burst Bulk Alloc function "
4625 "will be used on port=%d.",
4626 dev->data->port_id);
4628 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
4630 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
4631 "satisfied, or Scattered Rx is requested "
4633 dev->data->port_id);
4635 dev->rx_pkt_burst = ixgbe_recv_pkts;
4638 /* Propagate information about RX function choice through all queues. */
4641 (dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec ||
4642 dev->rx_pkt_burst == ixgbe_recv_pkts_vec);
4644 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4645 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4647 rxq->rx_using_sse = rx_using_sse;
4648 #ifdef RTE_LIBRTE_SECURITY
4649 rxq->using_ipsec = !!(dev->data->dev_conf.rxmode.offloads &
4650 DEV_RX_OFFLOAD_SECURITY);
4656 * ixgbe_set_rsc - configure RSC related port HW registers
4658 * Configures the port's RSC related registers according to the 4.6.7.2 chapter
4659 * of 82599 Spec (x540 configuration is virtually the same).
4663 * Returns 0 in case of success or a non-zero error code
4666 ixgbe_set_rsc(struct rte_eth_dev *dev)
4668 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4669 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4670 struct rte_eth_dev_info dev_info = { 0 };
4671 bool rsc_capable = false;
4677 dev->dev_ops->dev_infos_get(dev, &dev_info);
4678 if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_TCP_LRO)
4681 if (!rsc_capable && (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO)) {
4682 PMD_INIT_LOG(CRIT, "LRO is requested on HW that doesn't "
4687 /* RSC global configuration (chapter 4.6.7.2.1 of 82599 Spec) */
4689 if (!(rx_conf->offloads & DEV_RX_OFFLOAD_CRC_STRIP) &&
4690 (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO)) {
4692 * According to chapter of 4.6.7.2.1 of the Spec Rev.
4693 * 3.0 RSC configuration requires HW CRC stripping being
4694 * enabled. If user requested both HW CRC stripping off
4695 * and RSC on - return an error.
4697 PMD_INIT_LOG(CRIT, "LRO can't be enabled when HW CRC "
4702 /* RFCTL configuration */
4703 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4704 if ((rsc_capable) && (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO))
4706 * Since NFS packets coalescing is not supported - clear
4707 * RFCTL.NFSW_DIS and RFCTL.NFSR_DIS when RSC is
4710 rfctl &= ~(IXGBE_RFCTL_RSC_DIS | IXGBE_RFCTL_NFSW_DIS |
4711 IXGBE_RFCTL_NFSR_DIS);
4713 rfctl |= IXGBE_RFCTL_RSC_DIS;
4714 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4716 /* If LRO hasn't been requested - we are done here. */
4717 if (!(rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO))
4720 /* Set RDRXCTL.RSCACKC bit */
4721 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4722 rdrxctl |= IXGBE_RDRXCTL_RSCACKC;
4723 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4725 /* Per-queue RSC configuration (chapter 4.6.7.2.2 of 82599 Spec) */
4726 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4727 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4729 IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxq->reg_idx));
4731 IXGBE_READ_REG(hw, IXGBE_RSCCTL(rxq->reg_idx));
4733 IXGBE_READ_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx));
4735 IXGBE_READ_REG(hw, IXGBE_EITR(rxq->reg_idx));
4738 * ixgbe PMD doesn't support header-split at the moment.
4740 * Following the 4.6.7.2.1 chapter of the 82599/x540
4741 * Spec if RSC is enabled the SRRCTL[n].BSIZEHEADER
4742 * should be configured even if header split is not
4743 * enabled. We will configure it 128 bytes following the
4744 * recommendation in the spec.
4746 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
4747 srrctl |= (128 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4748 IXGBE_SRRCTL_BSIZEHDR_MASK;
4751 * TODO: Consider setting the Receive Descriptor Minimum
4752 * Threshold Size for an RSC case. This is not an obviously
4753 * beneficiary option but the one worth considering...
4756 rscctl |= IXGBE_RSCCTL_RSCEN;
4757 rscctl |= ixgbe_get_rscctl_maxdesc(rxq->mb_pool);
4758 psrtype |= IXGBE_PSRTYPE_TCPHDR;
4761 * RSC: Set ITR interval corresponding to 2K ints/s.
4763 * Full-sized RSC aggregations for a 10Gb/s link will
4764 * arrive at about 20K aggregation/s rate.
4766 * 2K inst/s rate will make only 10% of the
4767 * aggregations to be closed due to the interrupt timer
4768 * expiration for a streaming at wire-speed case.
4770 * For a sparse streaming case this setting will yield
4771 * at most 500us latency for a single RSC aggregation.
4773 eitr &= ~IXGBE_EITR_ITR_INT_MASK;
4774 eitr |= IXGBE_EITR_INTERVAL_US(500) | IXGBE_EITR_CNT_WDIS;
4776 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4777 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(rxq->reg_idx), rscctl);
4778 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
4779 IXGBE_WRITE_REG(hw, IXGBE_EITR(rxq->reg_idx), eitr);
4782 * RSC requires the mapping of the queue to the
4785 ixgbe_set_ivar(dev, rxq->reg_idx, i, 0);
4790 PMD_INIT_LOG(DEBUG, "enabling LRO mode");
4796 * Initializes Receive Unit.
4798 int __attribute__((cold))
4799 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
4801 struct ixgbe_hw *hw;
4802 struct ixgbe_rx_queue *rxq;
4813 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4816 PMD_INIT_FUNC_TRACE();
4817 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4820 * Make sure receives are disabled while setting
4821 * up the RX context (registers, descriptor rings, etc.).
4823 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4824 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4826 /* Enable receipt of broadcasted frames */
4827 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4828 fctrl |= IXGBE_FCTRL_BAM;
4829 fctrl |= IXGBE_FCTRL_DPF;
4830 fctrl |= IXGBE_FCTRL_PMCF;
4831 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4834 * Configure CRC stripping, if any.
4836 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4837 if (rx_conf->offloads & DEV_RX_OFFLOAD_CRC_STRIP)
4838 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
4840 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
4843 * Configure jumbo frame support, if any.
4845 if (rx_conf->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
4846 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4847 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4848 maxfrs &= 0x0000FFFF;
4849 maxfrs |= (rx_conf->max_rx_pkt_len << 16);
4850 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4852 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4855 * If loopback mode is configured for 82599, set LPBK bit.
4857 if (hw->mac.type == ixgbe_mac_82599EB &&
4858 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
4859 hlreg0 |= IXGBE_HLREG0_LPBK;
4861 hlreg0 &= ~IXGBE_HLREG0_LPBK;
4863 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4866 * Assume no header split and no VLAN strip support
4867 * on any Rx queue first .
4869 rx_conf->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
4870 /* Setup RX queues */
4871 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4872 rxq = dev->data->rx_queues[i];
4875 * Reset crc_len in case it was changed after queue setup by a
4876 * call to configure.
4878 rxq->crc_len = (rx_conf->offloads & DEV_RX_OFFLOAD_CRC_STRIP) ?
4881 /* Setup the Base and Length of the Rx Descriptor Rings */
4882 bus_addr = rxq->rx_ring_phys_addr;
4883 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
4884 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4885 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
4886 (uint32_t)(bus_addr >> 32));
4887 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
4888 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4889 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
4890 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
4892 /* Configure the SRRCTL register */
4893 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4895 /* Set if packets are dropped when no descriptors available */
4897 srrctl |= IXGBE_SRRCTL_DROP_EN;
4900 * Configure the RX buffer size in the BSIZEPACKET field of
4901 * the SRRCTL register of the queue.
4902 * The value is in 1 KB resolution. Valid values can be from
4905 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
4906 RTE_PKTMBUF_HEADROOM);
4907 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4908 IXGBE_SRRCTL_BSIZEPKT_MASK);
4910 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4912 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4913 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4915 /* It adds dual VLAN length for supporting dual VLAN */
4916 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4917 2 * IXGBE_VLAN_TAG_SIZE > buf_size)
4918 dev->data->scattered_rx = 1;
4919 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4920 rx_conf->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
4923 if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)
4924 dev->data->scattered_rx = 1;
4927 * Device configured with multiple RX queues.
4929 ixgbe_dev_mq_rx_configure(dev);
4932 * Setup the Checksum Register.
4933 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
4934 * Enable IP/L4 checkum computation by hardware if requested to do so.
4936 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
4937 rxcsum |= IXGBE_RXCSUM_PCSD;
4938 if (rx_conf->offloads & DEV_RX_OFFLOAD_CHECKSUM)
4939 rxcsum |= IXGBE_RXCSUM_IPPCSE;
4941 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
4943 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
4945 if (hw->mac.type == ixgbe_mac_82599EB ||
4946 hw->mac.type == ixgbe_mac_X540) {
4947 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4948 if (rx_conf->offloads & DEV_RX_OFFLOAD_CRC_STRIP)
4949 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4951 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
4952 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4953 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4956 rc = ixgbe_set_rsc(dev);
4960 ixgbe_set_rx_function(dev);
4966 * Initializes Transmit Unit.
4968 void __attribute__((cold))
4969 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
4971 struct ixgbe_hw *hw;
4972 struct ixgbe_tx_queue *txq;
4978 PMD_INIT_FUNC_TRACE();
4979 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4981 /* Enable TX CRC (checksum offload requirement) and hw padding
4984 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4985 hlreg0 |= (IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);
4986 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4988 /* Setup the Base and Length of the Tx Descriptor Rings */
4989 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4990 txq = dev->data->tx_queues[i];
4992 bus_addr = txq->tx_ring_phys_addr;
4993 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
4994 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4995 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
4996 (uint32_t)(bus_addr >> 32));
4997 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
4998 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4999 /* Setup the HW Tx Head and TX Tail descriptor pointers */
5000 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
5001 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
5004 * Disable Tx Head Writeback RO bit, since this hoses
5005 * bookkeeping if things aren't delivered in order.
5007 switch (hw->mac.type) {
5008 case ixgbe_mac_82598EB:
5009 txctrl = IXGBE_READ_REG(hw,
5010 IXGBE_DCA_TXCTRL(txq->reg_idx));
5011 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
5012 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
5016 case ixgbe_mac_82599EB:
5017 case ixgbe_mac_X540:
5018 case ixgbe_mac_X550:
5019 case ixgbe_mac_X550EM_x:
5020 case ixgbe_mac_X550EM_a:
5022 txctrl = IXGBE_READ_REG(hw,
5023 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
5024 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
5025 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
5031 /* Device configured with multiple TX queues. */
5032 ixgbe_dev_mq_tx_configure(dev);
5036 * Set up link for 82599 loopback mode Tx->Rx.
5038 static inline void __attribute__((cold))
5039 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
5041 PMD_INIT_FUNC_TRACE();
5043 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
5044 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
5046 PMD_INIT_LOG(ERR, "Could not enable loopback mode");
5055 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
5056 ixgbe_reset_pipeline_82599(hw);
5058 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
5064 * Start Transmit and Receive Units.
5066 int __attribute__((cold))
5067 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
5069 struct ixgbe_hw *hw;
5070 struct ixgbe_tx_queue *txq;
5071 struct ixgbe_rx_queue *rxq;
5078 PMD_INIT_FUNC_TRACE();
5079 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5081 for (i = 0; i < dev->data->nb_tx_queues; i++) {
5082 txq = dev->data->tx_queues[i];
5083 /* Setup Transmit Threshold Registers */
5084 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
5085 txdctl |= txq->pthresh & 0x7F;
5086 txdctl |= ((txq->hthresh & 0x7F) << 8);
5087 txdctl |= ((txq->wthresh & 0x7F) << 16);
5088 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
5091 if (hw->mac.type != ixgbe_mac_82598EB) {
5092 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
5093 dmatxctl |= IXGBE_DMATXCTL_TE;
5094 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
5097 for (i = 0; i < dev->data->nb_tx_queues; i++) {
5098 txq = dev->data->tx_queues[i];
5099 if (!txq->tx_deferred_start) {
5100 ret = ixgbe_dev_tx_queue_start(dev, i);
5106 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5107 rxq = dev->data->rx_queues[i];
5108 if (!rxq->rx_deferred_start) {
5109 ret = ixgbe_dev_rx_queue_start(dev, i);
5115 /* Enable Receive engine */
5116 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5117 if (hw->mac.type == ixgbe_mac_82598EB)
5118 rxctrl |= IXGBE_RXCTRL_DMBYPS;
5119 rxctrl |= IXGBE_RXCTRL_RXEN;
5120 hw->mac.ops.enable_rx_dma(hw, rxctrl);
5122 /* If loopback mode is enabled for 82599, set up the link accordingly */
5123 if (hw->mac.type == ixgbe_mac_82599EB &&
5124 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
5125 ixgbe_setup_loopback_link_82599(hw);
5127 #ifdef RTE_LIBRTE_SECURITY
5128 if ((dev->data->dev_conf.rxmode.offloads &
5129 DEV_RX_OFFLOAD_SECURITY) ||
5130 (dev->data->dev_conf.txmode.offloads &
5131 DEV_TX_OFFLOAD_SECURITY)) {
5132 ret = ixgbe_crypto_enable_ipsec(dev);
5135 "ixgbe_crypto_enable_ipsec fails with %d.",
5146 * Start Receive Units for specified queue.
5148 int __attribute__((cold))
5149 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
5151 struct ixgbe_hw *hw;
5152 struct ixgbe_rx_queue *rxq;
5156 PMD_INIT_FUNC_TRACE();
5157 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5159 if (rx_queue_id < dev->data->nb_rx_queues) {
5160 rxq = dev->data->rx_queues[rx_queue_id];
5162 /* Allocate buffers for descriptor rings */
5163 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
5164 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
5168 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5169 rxdctl |= IXGBE_RXDCTL_ENABLE;
5170 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
5172 /* Wait until RX Enable ready */
5173 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5176 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5177 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
5179 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d",
5182 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
5183 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
5184 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
5192 * Stop Receive Units for specified queue.
5194 int __attribute__((cold))
5195 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
5197 struct ixgbe_hw *hw;
5198 struct ixgbe_adapter *adapter =
5199 (struct ixgbe_adapter *)dev->data->dev_private;
5200 struct ixgbe_rx_queue *rxq;
5204 PMD_INIT_FUNC_TRACE();
5205 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5207 if (rx_queue_id < dev->data->nb_rx_queues) {
5208 rxq = dev->data->rx_queues[rx_queue_id];
5210 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5211 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
5212 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
5214 /* Wait until RX Enable bit clear */
5215 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5218 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5219 } while (--poll_ms && (rxdctl & IXGBE_RXDCTL_ENABLE));
5221 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d",
5224 rte_delay_us(RTE_IXGBE_WAIT_100_US);
5226 ixgbe_rx_queue_release_mbufs(rxq);
5227 ixgbe_reset_rx_queue(adapter, rxq);
5228 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
5237 * Start Transmit Units for specified queue.
5239 int __attribute__((cold))
5240 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
5242 struct ixgbe_hw *hw;
5243 struct ixgbe_tx_queue *txq;
5247 PMD_INIT_FUNC_TRACE();
5248 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5250 if (tx_queue_id < dev->data->nb_tx_queues) {
5251 txq = dev->data->tx_queues[tx_queue_id];
5252 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
5253 txdctl |= IXGBE_TXDCTL_ENABLE;
5254 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
5256 /* Wait until TX Enable ready */
5257 if (hw->mac.type == ixgbe_mac_82599EB) {
5258 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5261 txdctl = IXGBE_READ_REG(hw,
5262 IXGBE_TXDCTL(txq->reg_idx));
5263 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
5265 PMD_INIT_LOG(ERR, "Could not enable "
5266 "Tx Queue %d", tx_queue_id);
5269 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
5270 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
5271 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
5279 * Stop Transmit Units for specified queue.
5281 int __attribute__((cold))
5282 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
5284 struct ixgbe_hw *hw;
5285 struct ixgbe_tx_queue *txq;
5287 uint32_t txtdh, txtdt;
5290 PMD_INIT_FUNC_TRACE();
5291 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5293 if (tx_queue_id >= dev->data->nb_tx_queues)
5296 txq = dev->data->tx_queues[tx_queue_id];
5298 /* Wait until TX queue is empty */
5299 if (hw->mac.type == ixgbe_mac_82599EB) {
5300 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5302 rte_delay_us(RTE_IXGBE_WAIT_100_US);
5303 txtdh = IXGBE_READ_REG(hw,
5304 IXGBE_TDH(txq->reg_idx));
5305 txtdt = IXGBE_READ_REG(hw,
5306 IXGBE_TDT(txq->reg_idx));
5307 } while (--poll_ms && (txtdh != txtdt));
5309 PMD_INIT_LOG(ERR, "Tx Queue %d is not empty "
5310 "when stopping.", tx_queue_id);
5313 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
5314 txdctl &= ~IXGBE_TXDCTL_ENABLE;
5315 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
5317 /* Wait until TX Enable bit clear */
5318 if (hw->mac.type == ixgbe_mac_82599EB) {
5319 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5322 txdctl = IXGBE_READ_REG(hw,
5323 IXGBE_TXDCTL(txq->reg_idx));
5324 } while (--poll_ms && (txdctl & IXGBE_TXDCTL_ENABLE));
5326 PMD_INIT_LOG(ERR, "Could not disable "
5327 "Tx Queue %d", tx_queue_id);
5330 if (txq->ops != NULL) {
5331 txq->ops->release_mbufs(txq);
5332 txq->ops->reset(txq);
5334 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
5340 ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
5341 struct rte_eth_rxq_info *qinfo)
5343 struct ixgbe_rx_queue *rxq;
5345 rxq = dev->data->rx_queues[queue_id];
5347 qinfo->mp = rxq->mb_pool;
5348 qinfo->scattered_rx = dev->data->scattered_rx;
5349 qinfo->nb_desc = rxq->nb_rx_desc;
5351 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
5352 qinfo->conf.rx_drop_en = rxq->drop_en;
5353 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
5354 qinfo->conf.offloads = rxq->offloads;
5358 ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
5359 struct rte_eth_txq_info *qinfo)
5361 struct ixgbe_tx_queue *txq;
5363 txq = dev->data->tx_queues[queue_id];
5365 qinfo->nb_desc = txq->nb_tx_desc;
5367 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
5368 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
5369 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
5371 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
5372 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
5373 qinfo->conf.txq_flags = txq->txq_flags;
5374 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
5378 * [VF] Initializes Receive Unit.
5380 int __attribute__((cold))
5381 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
5383 struct ixgbe_hw *hw;
5384 struct ixgbe_rx_queue *rxq;
5385 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
5387 uint32_t srrctl, psrtype = 0;
5392 PMD_INIT_FUNC_TRACE();
5393 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5395 if (rte_is_power_of_2(dev->data->nb_rx_queues) == 0) {
5396 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
5397 "it should be power of 2");
5401 if (dev->data->nb_rx_queues > hw->mac.max_rx_queues) {
5402 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
5403 "it should be equal to or less than %d",
5404 hw->mac.max_rx_queues);
5409 * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
5410 * disables the VF receipt of packets if the PF MTU is > 1500.
5411 * This is done to deal with 82599 limitations that imposes
5412 * the PF and all VFs to share the same MTU.
5413 * Then, the PF driver enables again the VF receipt of packet when
5414 * the VF driver issues a IXGBE_VF_SET_LPE request.
5415 * In the meantime, the VF device cannot be used, even if the VF driver
5416 * and the Guest VM network stack are ready to accept packets with a
5417 * size up to the PF MTU.
5418 * As a work-around to this PF behaviour, force the call to
5419 * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
5420 * VF packets received can work in all cases.
5422 ixgbevf_rlpml_set_vf(hw,
5423 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
5426 * Assume no header split and no VLAN strip support
5427 * on any Rx queue first .
5429 rxmode->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
5430 /* Setup RX queues */
5431 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5432 rxq = dev->data->rx_queues[i];
5434 /* Allocate buffers for descriptor rings */
5435 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
5439 /* Setup the Base and Length of the Rx Descriptor Rings */
5440 bus_addr = rxq->rx_ring_phys_addr;
5442 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
5443 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
5444 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
5445 (uint32_t)(bus_addr >> 32));
5446 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
5447 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
5448 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
5449 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
5452 /* Configure the SRRCTL register */
5453 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
5455 /* Set if packets are dropped when no descriptors available */
5457 srrctl |= IXGBE_SRRCTL_DROP_EN;
5460 * Configure the RX buffer size in the BSIZEPACKET field of
5461 * the SRRCTL register of the queue.
5462 * The value is in 1 KB resolution. Valid values can be from
5465 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
5466 RTE_PKTMBUF_HEADROOM);
5467 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
5468 IXGBE_SRRCTL_BSIZEPKT_MASK);
5471 * VF modification to write virtual function SRRCTL register
5473 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
5475 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
5476 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
5478 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER ||
5479 /* It adds dual VLAN length for supporting dual VLAN */
5480 (rxmode->max_rx_pkt_len +
5481 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
5482 if (!dev->data->scattered_rx)
5483 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
5484 dev->data->scattered_rx = 1;
5487 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
5488 rxmode->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
5491 /* Set RQPL for VF RSS according to max Rx queue */
5492 psrtype |= (dev->data->nb_rx_queues >> 1) <<
5493 IXGBE_PSRTYPE_RQPL_SHIFT;
5494 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
5496 ixgbe_set_rx_function(dev);
5502 * [VF] Initializes Transmit Unit.
5504 void __attribute__((cold))
5505 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
5507 struct ixgbe_hw *hw;
5508 struct ixgbe_tx_queue *txq;
5513 PMD_INIT_FUNC_TRACE();
5514 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5516 /* Setup the Base and Length of the Tx Descriptor Rings */
5517 for (i = 0; i < dev->data->nb_tx_queues; i++) {
5518 txq = dev->data->tx_queues[i];
5519 bus_addr = txq->tx_ring_phys_addr;
5520 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
5521 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
5522 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
5523 (uint32_t)(bus_addr >> 32));
5524 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
5525 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
5526 /* Setup the HW Tx Head and TX Tail descriptor pointers */
5527 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
5528 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
5531 * Disable Tx Head Writeback RO bit, since this hoses
5532 * bookkeeping if things aren't delivered in order.
5534 txctrl = IXGBE_READ_REG(hw,
5535 IXGBE_VFDCA_TXCTRL(i));
5536 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
5537 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
5543 * [VF] Start Transmit and Receive Units.
5545 void __attribute__((cold))
5546 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
5548 struct ixgbe_hw *hw;
5549 struct ixgbe_tx_queue *txq;
5550 struct ixgbe_rx_queue *rxq;
5556 PMD_INIT_FUNC_TRACE();
5557 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5559 for (i = 0; i < dev->data->nb_tx_queues; i++) {
5560 txq = dev->data->tx_queues[i];
5561 /* Setup Transmit Threshold Registers */
5562 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5563 txdctl |= txq->pthresh & 0x7F;
5564 txdctl |= ((txq->hthresh & 0x7F) << 8);
5565 txdctl |= ((txq->wthresh & 0x7F) << 16);
5566 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
5569 for (i = 0; i < dev->data->nb_tx_queues; i++) {
5571 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5572 txdctl |= IXGBE_TXDCTL_ENABLE;
5573 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
5576 /* Wait until TX Enable ready */
5579 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5580 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
5582 PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
5584 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5586 rxq = dev->data->rx_queues[i];
5588 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
5589 rxdctl |= IXGBE_RXDCTL_ENABLE;
5590 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
5592 /* Wait until RX Enable ready */
5596 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
5597 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
5599 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
5601 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);
5607 ixgbe_config_rss_filter(struct rte_eth_dev *dev,
5608 struct ixgbe_rte_flow_rss_conf *conf, bool add)
5610 struct ixgbe_hw *hw;
5614 uint16_t sp_reta_size;
5616 struct rte_eth_rss_conf rss_conf = conf->rss_conf;
5617 struct ixgbe_filter_info *filter_info =
5618 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5620 PMD_INIT_FUNC_TRACE();
5621 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5623 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5626 if (memcmp(conf, &filter_info->rss_info,
5627 sizeof(struct ixgbe_rte_flow_rss_conf)) == 0) {
5628 ixgbe_rss_disable(dev);
5629 memset(&filter_info->rss_info, 0,
5630 sizeof(struct ixgbe_rte_flow_rss_conf));
5636 if (filter_info->rss_info.num)
5638 /* Fill in redirection table
5639 * The byte-swap is needed because NIC registers are in
5640 * little-endian order.
5643 for (i = 0, j = 0; i < sp_reta_size; i++, j++) {
5644 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5648 reta = (reta << 8) | conf->queue[j];
5650 IXGBE_WRITE_REG(hw, reta_reg,
5654 /* Configure the RSS key and the RSS protocols used to compute
5655 * the RSS hash of input packets.
5657 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
5658 ixgbe_rss_disable(dev);
5661 if (rss_conf.rss_key == NULL)
5662 rss_conf.rss_key = rss_intel_key; /* Default hash key */
5663 ixgbe_hw_rss_hash_set(hw, &rss_conf);
5665 rte_memcpy(&filter_info->rss_info,
5666 conf, sizeof(struct ixgbe_rte_flow_rss_conf));
5671 /* Stubs needed for linkage when CONFIG_RTE_IXGBE_INC_VECTOR is set to 'n' */
5672 int __attribute__((weak))
5673 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
5678 uint16_t __attribute__((weak))
5679 ixgbe_recv_pkts_vec(
5680 void __rte_unused *rx_queue,
5681 struct rte_mbuf __rte_unused **rx_pkts,
5682 uint16_t __rte_unused nb_pkts)
5687 uint16_t __attribute__((weak))
5688 ixgbe_recv_scattered_pkts_vec(
5689 void __rte_unused *rx_queue,
5690 struct rte_mbuf __rte_unused **rx_pkts,
5691 uint16_t __rte_unused nb_pkts)
5696 int __attribute__((weak))
5697 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue __rte_unused *rxq)