drivers/net/ixgbe/ixgbe_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation.
   3  * Copyright 2014 6WIND S.A.
   4  */
   5
   6 #include <sys/queue.h>
   7
   8 #include <stdio.h>
   9 #include <stdlib.h>
  10 #include <string.h>
  11 #include <errno.h>
  12 #include <stdint.h>
  13 #include <stdarg.h>
  14 #include <unistd.h>
  15 #include <inttypes.h>
  16
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_interrupts.h>
  23 #include <rte_pci.h>
  24 #include <rte_memory.h>
  25 #include <rte_memzone.h>
  26 #include <rte_launch.h>
  27 #include <rte_eal.h>
  28 #include <rte_per_lcore.h>
  29 #include <rte_lcore.h>
  30 #include <rte_atomic.h>
  31 #include <rte_branch_prediction.h>
  32 #include <rte_mempool.h>
  33 #include <rte_malloc.h>
  34 #include <rte_mbuf.h>
  35 #include <rte_ether.h>
  36 #include <ethdev_driver.h>
  37 #include <rte_security_driver.h>
  38 #include <rte_prefetch.h>
  39 #include <rte_udp.h>
  40 #include <rte_tcp.h>
  41 #include <rte_sctp.h>
  42 #include <rte_string_fns.h>
  43 #include <rte_errno.h>
  44 #include <rte_ip.h>
  45 #include <rte_net.h>
  46 #include <rte_vect.h>
  47
  48 #include "ixgbe_logs.h"
  49 #include "base/ixgbe_api.h"
  50 #include "base/ixgbe_vf.h"
  51 #include "ixgbe_ethdev.h"
  52 #include "base/ixgbe_dcb.h"
  53 #include "base/ixgbe_common.h"
  54 #include "ixgbe_rxtx.h"
  55
  56 #ifdef RTE_LIBRTE_IEEE1588
  57 #define IXGBE_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
  58 #else
  59 #define IXGBE_TX_IEEE1588_TMST 0
  60 #endif
  61 /* Bit Mask to indicate what bits required for building TX context */
  62 #define IXGBE_TX_OFFLOAD_MASK (                  \
  63                 PKT_TX_OUTER_IPV6 |              \
  64                 PKT_TX_OUTER_IPV4 |              \
  65                 PKT_TX_IPV6 |                    \
  66                 PKT_TX_IPV4 |                    \
  67                 PKT_TX_VLAN_PKT |                \
  68                 PKT_TX_IP_CKSUM |                \
  69                 PKT_TX_L4_MASK |                 \
  70                 PKT_TX_TCP_SEG |                 \
  71                 PKT_TX_MACSEC |                  \
  72                 PKT_TX_OUTER_IP_CKSUM |          \
  73                 PKT_TX_SEC_OFFLOAD |     \
  74                 IXGBE_TX_IEEE1588_TMST)
  75
  76 #define IXGBE_TX_OFFLOAD_NOTSUP_MASK \
  77                 (PKT_TX_OFFLOAD_MASK ^ IXGBE_TX_OFFLOAD_MASK)
  78
  79 #if 1
  80 #define RTE_PMD_USE_PREFETCH
  81 #endif
  82
  83 #ifdef RTE_PMD_USE_PREFETCH
  84 /*
  85  * Prefetch a cache line into all cache levels.
  86  */
  87 #define rte_ixgbe_prefetch(p)   rte_prefetch0(p)
  88 #else
  89 #define rte_ixgbe_prefetch(p)   do {} while (0)
  90 #endif
  91
  92 /*********************************************************************
  93  *
  94  *  TX functions
  95  *
  96  **********************************************************************/
  97
  98 /*
  99  * Check for descriptors with their DD bit set and free mbufs.
 100  * Return the total number of buffers freed.
 101  */
 102 static __rte_always_inline int
 103 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
 104 {
 105         struct ixgbe_tx_entry *txep;
 106         uint32_t status;
 107         int i, nb_free = 0;
 108         struct rte_mbuf *m, *free[RTE_IXGBE_TX_MAX_FREE_BUF_SZ];
 109
 110         /* check DD bit on threshold descriptor */
 111         status = txq->tx_ring[txq->tx_next_dd].wb.status;
 112         if (!(status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD)))
 113                 return 0;
 114
 115         /*
 116          * first buffer to free from S/W ring is at index
 117          * tx_next_dd - (tx_rs_thresh-1)
 118          */
 119         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
 120
 121         for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
 122                 /* free buffers one at a time */
 123                 m = rte_pktmbuf_prefree_seg(txep->mbuf);
 124                 txep->mbuf = NULL;
 125
 126                 if (unlikely(m == NULL))
 127                         continue;
 128
 129                 if (nb_free >= RTE_IXGBE_TX_MAX_FREE_BUF_SZ ||
 130                     (nb_free > 0 && m->pool != free[0]->pool)) {
 131                         rte_mempool_put_bulk(free[0]->pool,
 132                                              (void **)free, nb_free);
 133                         nb_free = 0;
 134                 }
 135
 136                 free[nb_free++] = m;
 137         }
 138
 139         if (nb_free > 0)
 140                 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
 141
 142         /* buffers were freed, update counters */
 143         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
 144         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
 145         if (txq->tx_next_dd >= txq->nb_tx_desc)
 146                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 147
 148         return txq->tx_rs_thresh;
 149 }
 150
 151 /* Populate 4 descriptors with data from 4 mbufs */
 152 static inline void
 153 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
 154 {
 155         uint64_t buf_dma_addr;
 156         uint32_t pkt_len;
 157         int i;
 158
 159         for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
 160                 buf_dma_addr = rte_mbuf_data_iova(*pkts);
 161                 pkt_len = (*pkts)->data_len;
 162
 163                 /* write data to descriptor */
 164                 txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
 165
 166                 txdp->read.cmd_type_len =
 167                         rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
 168
 169                 txdp->read.olinfo_status =
 170                         rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
 171
 172                 rte_prefetch0(&(*pkts)->pool);
 173         }
 174 }
 175
 176 /* Populate 1 descriptor with data from 1 mbuf */
 177 static inline void
 178 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
 179 {
 180         uint64_t buf_dma_addr;
 181         uint32_t pkt_len;
 182
 183         buf_dma_addr = rte_mbuf_data_iova(*pkts);
 184         pkt_len = (*pkts)->data_len;
 185
 186         /* write data to descriptor */
 187         txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
 188         txdp->read.cmd_type_len =
 189                         rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
 190         txdp->read.olinfo_status =
 191                         rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
 192         rte_prefetch0(&(*pkts)->pool);
 193 }
 194
 195 /*
 196  * Fill H/W descriptor ring with mbuf data.
 197  * Copy mbuf pointers to the S/W ring.
 198  */
 199 static inline void
 200 ixgbe_tx_fill_hw_ring(struct ixgbe_tx_queue *txq, struct rte_mbuf **pkts,
 201                       uint16_t nb_pkts)
 202 {
 203         volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
 204         struct ixgbe_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
 205         const int N_PER_LOOP = 4;
 206         const int N_PER_LOOP_MASK = N_PER_LOOP-1;
 207         int mainpart, leftover;
 208         int i, j;
 209
 210         /*
 211          * Process most of the packets in chunks of N pkts.  Any
 212          * leftover packets will get processed one at a time.
 213          */
 214         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
 215         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
 216         for (i = 0; i < mainpart; i += N_PER_LOOP) {
 217                 /* Copy N mbuf pointers to the S/W ring */
 218                 for (j = 0; j < N_PER_LOOP; ++j) {
 219                         (txep + i + j)->mbuf = *(pkts + i + j);
 220                 }
 221                 tx4(txdp + i, pkts + i);
 222         }
 223
 224         if (unlikely(leftover > 0)) {
 225                 for (i = 0; i < leftover; ++i) {
 226                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
 227                         tx1(txdp + mainpart + i, pkts + mainpart + i);
 228                 }
 229         }
 230 }
 231
 232 static inline uint16_t
 233 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 234              uint16_t nb_pkts)
 235 {
 236         struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
 237         volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
 238         uint16_t n = 0;
 239
 240         /*
 241          * Begin scanning the H/W ring for done descriptors when the
 242          * number of available descriptors drops below tx_free_thresh.  For
 243          * each done descriptor, free the associated buffer.
 244          */
 245         if (txq->nb_tx_free < txq->tx_free_thresh)
 246                 ixgbe_tx_free_bufs(txq);
 247
 248         /* Only use descriptors that are available */
 249         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
 250         if (unlikely(nb_pkts == 0))
 251                 return 0;
 252
 253         /* Use exactly nb_pkts descriptors */
 254         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
 255
 256         /*
 257          * At this point, we know there are enough descriptors in the
 258          * ring to transmit all the packets.  This assumes that each
 259          * mbuf contains a single segment, and that no new offloads
 260          * are expected, which would require a new context descriptor.
 261          */
 262
 263         /*
 264          * See if we're going to wrap-around. If so, handle the top
 265          * of the descriptor ring first, then do the bottom.  If not,
 266          * the processing looks just like the "bottom" part anyway...
 267          */
 268         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
 269                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
 270                 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
 271
 272                 /*
 273                  * We know that the last descriptor in the ring will need to
 274                  * have its RS bit set because tx_rs_thresh has to be
 275                  * a divisor of the ring size
 276                  */
 277                 tx_r[txq->tx_next_rs].read.cmd_type_len |=
 278                         rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
 279                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 280
 281                 txq->tx_tail = 0;
 282         }
 283
 284         /* Fill H/W descriptor ring with mbuf data */
 285         ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
 286         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
 287
 288         /*
 289          * Determine if RS bit should be set
 290          * This is what we actually want:
 291          *   if ((txq->tx_tail - 1) >= txq->tx_next_rs)
 292          * but instead of subtracting 1 and doing >=, we can just do
 293          * greater than without subtracting.
 294          */
 295         if (txq->tx_tail > txq->tx_next_rs) {
 296                 tx_r[txq->tx_next_rs].read.cmd_type_len |=
 297                         rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
 298                 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
 299                                                 txq->tx_rs_thresh);
 300                 if (txq->tx_next_rs >= txq->nb_tx_desc)
 301                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 302         }
 303
 304         /*
 305          * Check for wrap-around. This would only happen if we used
 306          * up to the last descriptor in the ring, no more, no less.
 307          */
 308         if (txq->tx_tail >= txq->nb_tx_desc)
 309                 txq->tx_tail = 0;
 310
 311         /* update tail pointer */
 312         rte_wmb();
 313         IXGBE_PCI_REG_WC_WRITE_RELAXED(txq->tdt_reg_addr, txq->tx_tail);
 314
 315         return nb_pkts;
 316 }
 317
 318 uint16_t
 319 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
 320                        uint16_t nb_pkts)
 321 {
 322         uint16_t nb_tx;
 323
 324         /* Try to transmit at least chunks of TX_MAX_BURST pkts */
 325         if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
 326                 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
 327
 328         /* transmit more than the max burst, in chunks of TX_MAX_BURST */
 329         nb_tx = 0;
 330         while (nb_pkts) {
 331                 uint16_t ret, n;
 332
 333                 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
 334                 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
 335                 nb_tx = (uint16_t)(nb_tx + ret);
 336                 nb_pkts = (uint16_t)(nb_pkts - ret);
 337                 if (ret < n)
 338                         break;
 339         }
 340
 341         return nb_tx;
 342 }
 343
 344 static uint16_t
 345 ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 346                     uint16_t nb_pkts)
 347 {
 348         uint16_t nb_tx = 0;
 349         struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
 350
 351         while (nb_pkts) {
 352                 uint16_t ret, num;
 353
 354                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
 355                 ret = ixgbe_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
 356                                                  num);
 357                 nb_tx += ret;
 358                 nb_pkts -= ret;
 359                 if (ret < num)
 360                         break;
 361         }
 362
 363         return nb_tx;
 364 }
 365
 366 static inline void
 367 ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,
 368                 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
 369                 uint64_t ol_flags, union ixgbe_tx_offload tx_offload,
 370                 __rte_unused uint64_t *mdata)
 371 {
 372         uint32_t type_tucmd_mlhl;
 373         uint32_t mss_l4len_idx = 0;
 374         uint32_t ctx_idx;
 375         uint32_t vlan_macip_lens;
 376         union ixgbe_tx_offload tx_offload_mask;
 377         uint32_t seqnum_seed = 0;
 378
 379         ctx_idx = txq->ctx_curr;
 380         tx_offload_mask.data[0] = 0;
 381         tx_offload_mask.data[1] = 0;
 382         type_tucmd_mlhl = 0;
 383
 384         /* Specify which HW CTX to upload. */
 385         mss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
 386
 387         if (ol_flags & PKT_TX_VLAN_PKT) {
 388                 tx_offload_mask.vlan_tci |= ~0;
 389         }
 390
 391         /* check if TCP segmentation required for this packet */
 392         if (ol_flags & PKT_TX_TCP_SEG) {
 393                 /* implies IP cksum in IPv4 */
 394                 if (ol_flags & PKT_TX_IP_CKSUM)
 395                         type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |
 396                                 IXGBE_ADVTXD_TUCMD_L4T_TCP |
 397                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 398                 else
 399                         type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV6 |
 400                                 IXGBE_ADVTXD_TUCMD_L4T_TCP |
 401                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 402
 403                 tx_offload_mask.l2_len |= ~0;
 404                 tx_offload_mask.l3_len |= ~0;
 405                 tx_offload_mask.l4_len |= ~0;
 406                 tx_offload_mask.tso_segsz |= ~0;
 407                 mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
 408                 mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;
 409         } else { /* no TSO, check if hardware checksum is needed */
 410                 if (ol_flags & PKT_TX_IP_CKSUM) {
 411                         type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
 412                         tx_offload_mask.l2_len |= ~0;
 413                         tx_offload_mask.l3_len |= ~0;
 414                 }
 415
 416                 switch (ol_flags & PKT_TX_L4_MASK) {
 417                 case PKT_TX_UDP_CKSUM:
 418                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
 419                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 420                         mss_l4len_idx |= sizeof(struct rte_udp_hdr)
 421                                 << IXGBE_ADVTXD_L4LEN_SHIFT;
 422                         tx_offload_mask.l2_len |= ~0;
 423                         tx_offload_mask.l3_len |= ~0;
 424                         break;
 425                 case PKT_TX_TCP_CKSUM:
 426                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
 427                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 428                         mss_l4len_idx |= sizeof(struct rte_tcp_hdr)
 429                                 << IXGBE_ADVTXD_L4LEN_SHIFT;
 430                         tx_offload_mask.l2_len |= ~0;
 431                         tx_offload_mask.l3_len |= ~0;
 432                         break;
 433                 case PKT_TX_SCTP_CKSUM:
 434                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
 435                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 436                         mss_l4len_idx |= sizeof(struct rte_sctp_hdr)
 437                                 << IXGBE_ADVTXD_L4LEN_SHIFT;
 438                         tx_offload_mask.l2_len |= ~0;
 439                         tx_offload_mask.l3_len |= ~0;
 440                         break;
 441                 default:
 442                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
 443                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 444                         break;
 445                 }
 446         }
 447
 448         if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
 449                 tx_offload_mask.outer_l2_len |= ~0;
 450                 tx_offload_mask.outer_l3_len |= ~0;
 451                 tx_offload_mask.l2_len |= ~0;
 452                 seqnum_seed |= tx_offload.outer_l3_len
 453                                << IXGBE_ADVTXD_OUTER_IPLEN;
 454                 seqnum_seed |= tx_offload.l2_len
 455                                << IXGBE_ADVTXD_TUNNEL_LEN;
 456         }
 457 #ifdef RTE_LIB_SECURITY
 458         if (ol_flags & PKT_TX_SEC_OFFLOAD) {
 459                 union ixgbe_crypto_tx_desc_md *md =
 460                                 (union ixgbe_crypto_tx_desc_md *)mdata;
 461                 seqnum_seed |=
 462                         (IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK & md->sa_idx);
 463                 type_tucmd_mlhl |= md->enc ?
 464                                 (IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP |
 465                                 IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN) : 0;
 466                 type_tucmd_mlhl |=
 467                         (md->pad_len & IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK);
 468                 tx_offload_mask.sa_idx |= ~0;
 469                 tx_offload_mask.sec_pad_len |= ~0;
 470         }
 471 #endif
 472
 473         txq->ctx_cache[ctx_idx].flags = ol_flags;
 474         txq->ctx_cache[ctx_idx].tx_offload.data[0]  =
 475                 tx_offload_mask.data[0] & tx_offload.data[0];
 476         txq->ctx_cache[ctx_idx].tx_offload.data[1]  =
 477                 tx_offload_mask.data[1] & tx_offload.data[1];
 478         txq->ctx_cache[ctx_idx].tx_offload_mask    = tx_offload_mask;
 479
 480         ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
 481         vlan_macip_lens = tx_offload.l3_len;
 482         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 483                 vlan_macip_lens |= (tx_offload.outer_l2_len <<
 484                                     IXGBE_ADVTXD_MACLEN_SHIFT);
 485         else
 486                 vlan_macip_lens |= (tx_offload.l2_len <<
 487                                     IXGBE_ADVTXD_MACLEN_SHIFT);
 488         vlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);
 489         ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
 490         ctx_txd->mss_l4len_idx   = rte_cpu_to_le_32(mss_l4len_idx);
 491         ctx_txd->seqnum_seed     = seqnum_seed;
 492 }
 493
 494 /*
 495  * Check which hardware context can be used. Use the existing match
 496  * or create a new context descriptor.
 497  */
 498 static inline uint32_t
 499 what_advctx_update(struct ixgbe_tx_queue *txq, uint64_t flags,
 500                    union ixgbe_tx_offload tx_offload)
 501 {
 502         /* If match with the current used context */
 503         if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
 504                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] ==
 505                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0]
 506                      & tx_offload.data[0])) &&
 507                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] ==
 508                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1]
 509                      & tx_offload.data[1]))))
 510                 return txq->ctx_curr;
 511
 512         /* What if match with the next context  */
 513         txq->ctx_curr ^= 1;
 514         if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
 515                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] ==
 516                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0]
 517                      & tx_offload.data[0])) &&
 518                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] ==
 519                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1]
 520                      & tx_offload.data[1]))))
 521                 return txq->ctx_curr;
 522
 523         /* Mismatch, use the previous context */
 524         return IXGBE_CTX_NUM;
 525 }
 526
 527 static inline uint32_t
 528 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
 529 {
 530         uint32_t tmp = 0;
 531
 532         if ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM)
 533                 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
 534         if (ol_flags & PKT_TX_IP_CKSUM)
 535                 tmp |= IXGBE_ADVTXD_POPTS_IXSM;
 536         if (ol_flags & PKT_TX_TCP_SEG)
 537                 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
 538         return tmp;
 539 }
 540
 541 static inline uint32_t
 542 tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)
 543 {
 544         uint32_t cmdtype = 0;
 545
 546         if (ol_flags & PKT_TX_VLAN_PKT)
 547                 cmdtype |= IXGBE_ADVTXD_DCMD_VLE;
 548         if (ol_flags & PKT_TX_TCP_SEG)
 549                 cmdtype |= IXGBE_ADVTXD_DCMD_TSE;
 550         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 551                 cmdtype |= (1 << IXGBE_ADVTXD_OUTERIPCS_SHIFT);
 552         if (ol_flags & PKT_TX_MACSEC)
 553                 cmdtype |= IXGBE_ADVTXD_MAC_LINKSEC;
 554         return cmdtype;
 555 }
 556
 557 /* Default RS bit threshold values */
 558 #ifndef DEFAULT_TX_RS_THRESH
 559 #define DEFAULT_TX_RS_THRESH   32
 560 #endif
 561 #ifndef DEFAULT_TX_FREE_THRESH
 562 #define DEFAULT_TX_FREE_THRESH 32
 563 #endif
 564
 565 /* Reset transmit descriptors after they have been used */
 566 static inline int
 567 ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)
 568 {
 569         struct ixgbe_tx_entry *sw_ring = txq->sw_ring;
 570         volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
 571         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 572         uint16_t nb_tx_desc = txq->nb_tx_desc;
 573         uint16_t desc_to_clean_to;
 574         uint16_t nb_tx_to_clean;
 575         uint32_t status;
 576
 577         /* Determine the last descriptor needing to be cleaned */
 578         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 579         if (desc_to_clean_to >= nb_tx_desc)
 580                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 581
 582         /* Check to make sure the last descriptor to clean is done */
 583         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 584         status = txr[desc_to_clean_to].wb.status;
 585         if (!(status & rte_cpu_to_le_32(IXGBE_TXD_STAT_DD))) {
 586                 PMD_TX_LOG(DEBUG,
 587                            "TX descriptor %4u is not done"
 588                            "(port=%d queue=%d)",
 589                            desc_to_clean_to,
 590                            txq->port_id, txq->queue_id);
 591                 /* Failed to clean any descriptors, better luck next time */
 592                 return -(1);
 593         }
 594
 595         /* Figure out how many descriptors will be cleaned */
 596         if (last_desc_cleaned > desc_to_clean_to)
 597                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 598                                                         desc_to_clean_to);
 599         else
 600                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 601                                                 last_desc_cleaned);
 602
 603         PMD_TX_LOG(DEBUG,
 604                    "Cleaning %4u TX descriptors: %4u to %4u "
 605                    "(port=%d queue=%d)",
 606                    nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
 607                    txq->port_id, txq->queue_id);
 608
 609         /*
 610          * The last descriptor to clean is done, so that means all the
 611          * descriptors from the last descriptor that was cleaned
 612          * up to the last descriptor with the RS bit set
 613          * are done. Only reset the threshold descriptor.
 614          */
 615         txr[desc_to_clean_to].wb.status = 0;
 616
 617         /* Update the txq to reflect the last descriptor that was cleaned */
 618         txq->last_desc_cleaned = desc_to_clean_to;
 619         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 620
 621         /* No Error */
 622         return 0;
 623 }
 624
 625 uint16_t
 626 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 627                 uint16_t nb_pkts)
 628 {
 629         struct ixgbe_tx_queue *txq;
 630         struct ixgbe_tx_entry *sw_ring;
 631         struct ixgbe_tx_entry *txe, *txn;
 632         volatile union ixgbe_adv_tx_desc *txr;
 633         volatile union ixgbe_adv_tx_desc *txd, *txp;
 634         struct rte_mbuf     *tx_pkt;
 635         struct rte_mbuf     *m_seg;
 636         uint64_t buf_dma_addr;
 637         uint32_t olinfo_status;
 638         uint32_t cmd_type_len;
 639         uint32_t pkt_len;
 640         uint16_t slen;
 641         uint64_t ol_flags;
 642         uint16_t tx_id;
 643         uint16_t tx_last;
 644         uint16_t nb_tx;
 645         uint16_t nb_used;
 646         uint64_t tx_ol_req;
 647         uint32_t ctx = 0;
 648         uint32_t new_ctx;
 649         union ixgbe_tx_offload tx_offload;
 650 #ifdef RTE_LIB_SECURITY
 651         uint8_t use_ipsec;
 652 #endif
 653
 654         tx_offload.data[0] = 0;
 655         tx_offload.data[1] = 0;
 656         txq = tx_queue;
 657         sw_ring = txq->sw_ring;
 658         txr     = txq->tx_ring;
 659         tx_id   = txq->tx_tail;
 660         txe = &sw_ring[tx_id];
 661         txp = NULL;
 662
 663         /* Determine if the descriptor ring needs to be cleaned. */
 664         if (txq->nb_tx_free < txq->tx_free_thresh)
 665                 ixgbe_xmit_cleanup(txq);
 666
 667         rte_prefetch0(&txe->mbuf->pool);
 668
 669         /* TX loop */
 670         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
 671                 new_ctx = 0;
 672                 tx_pkt = *tx_pkts++;
 673                 pkt_len = tx_pkt->pkt_len;
 674
 675                 /*
 676                  * Determine how many (if any) context descriptors
 677                  * are needed for offload functionality.
 678                  */
 679                 ol_flags = tx_pkt->ol_flags;
 680 #ifdef RTE_LIB_SECURITY
 681                 use_ipsec = txq->using_ipsec && (ol_flags & PKT_TX_SEC_OFFLOAD);
 682 #endif
 683
 684                 /* If hardware offload required */
 685                 tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
 686                 if (tx_ol_req) {
 687                         tx_offload.l2_len = tx_pkt->l2_len;
 688                         tx_offload.l3_len = tx_pkt->l3_len;
 689                         tx_offload.l4_len = tx_pkt->l4_len;
 690                         tx_offload.vlan_tci = tx_pkt->vlan_tci;
 691                         tx_offload.tso_segsz = tx_pkt->tso_segsz;
 692                         tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
 693                         tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
 694 #ifdef RTE_LIB_SECURITY
 695                         if (use_ipsec) {
 696                                 union ixgbe_crypto_tx_desc_md *ipsec_mdata =
 697                                         (union ixgbe_crypto_tx_desc_md *)
 698                                                 rte_security_dynfield(tx_pkt);
 699                                 tx_offload.sa_idx = ipsec_mdata->sa_idx;
 700                                 tx_offload.sec_pad_len = ipsec_mdata->pad_len;
 701                         }
 702 #endif
 703
 704                         /* If new context need be built or reuse the exist ctx. */
 705                         ctx = what_advctx_update(txq, tx_ol_req,
 706                                 tx_offload);
 707                         /* Only allocate context descriptor if required*/
 708                         new_ctx = (ctx == IXGBE_CTX_NUM);
 709                         ctx = txq->ctx_curr;
 710                 }
 711
 712                 /*
 713                  * Keep track of how many descriptors are used this loop
 714                  * This will always be the number of segments + the number of
 715                  * Context descriptors required to transmit the packet
 716                  */
 717                 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
 718
 719                 if (txp != NULL &&
 720                                 nb_used + txq->nb_tx_used >= txq->tx_rs_thresh)
 721                         /* set RS on the previous packet in the burst */
 722                         txp->read.cmd_type_len |=
 723                                 rte_cpu_to_le_32(IXGBE_TXD_CMD_RS);
 724
 725                 /*
 726                  * The number of descriptors that must be allocated for a
 727                  * packet is the number of segments of that packet, plus 1
 728                  * Context Descriptor for the hardware offload, if any.
 729                  * Determine the last TX descriptor to allocate in the TX ring
 730                  * for the packet, starting from the current position (tx_id)
 731                  * in the ring.
 732                  */
 733                 tx_last = (uint16_t) (tx_id + nb_used - 1);
 734
 735                 /* Circular ring */
 736                 if (tx_last >= txq->nb_tx_desc)
 737                         tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
 738
 739                 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
 740                            " tx_first=%u tx_last=%u",
 741                            (unsigned) txq->port_id,
 742                            (unsigned) txq->queue_id,
 743                            (unsigned) pkt_len,
 744                            (unsigned) tx_id,
 745                            (unsigned) tx_last);
 746
 747                 /*
 748                  * Make sure there are enough TX descriptors available to
 749                  * transmit the entire packet.
 750                  * nb_used better be less than or equal to txq->tx_rs_thresh
 751                  */
 752                 if (nb_used > txq->nb_tx_free) {
 753                         PMD_TX_LOG(DEBUG,
 754                                    "Not enough free TX descriptors "
 755                                    "nb_used=%4u nb_free=%4u "
 756                                    "(port=%d queue=%d)",
 757                                    nb_used, txq->nb_tx_free,
 758                                    txq->port_id, txq->queue_id);
 759
 760                         if (ixgbe_xmit_cleanup(txq) != 0) {
 761                                 /* Could not clean any descriptors */
 762                                 if (nb_tx == 0)
 763                                         return 0;
 764                                 goto end_of_tx;
 765                         }
 766
 767                         /* nb_used better be <= txq->tx_rs_thresh */
 768                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
 769                                 PMD_TX_LOG(DEBUG,
 770                                            "The number of descriptors needed to "
 771                                            "transmit the packet exceeds the "
 772                                            "RS bit threshold. This will impact "
 773                                            "performance."
 774                                            "nb_used=%4u nb_free=%4u "
 775                                            "tx_rs_thresh=%4u. "
 776                                            "(port=%d queue=%d)",
 777                                            nb_used, txq->nb_tx_free,
 778                                            txq->tx_rs_thresh,
 779                                            txq->port_id, txq->queue_id);
 780                                 /*
 781                                  * Loop here until there are enough TX
 782                                  * descriptors or until the ring cannot be
 783                                  * cleaned.
 784                                  */
 785                                 while (nb_used > txq->nb_tx_free) {
 786                                         if (ixgbe_xmit_cleanup(txq) != 0) {
 787                                                 /*
 788                                                  * Could not clean any
 789                                                  * descriptors
 790                                                  */
 791                                                 if (nb_tx == 0)
 792                                                         return 0;
 793                                                 goto end_of_tx;
 794                                         }
 795                                 }
 796                         }
 797                 }
 798
 799                 /*
 800                  * By now there are enough free TX descriptors to transmit
 801                  * the packet.
 802                  */
 803
 804                 /*
 805                  * Set common flags of all TX Data Descriptors.
 806                  *
 807                  * The following bits must be set in all Data Descriptors:
 808                  *   - IXGBE_ADVTXD_DTYP_DATA
 809                  *   - IXGBE_ADVTXD_DCMD_DEXT
 810                  *
 811                  * The following bits must be set in the first Data Descriptor
 812                  * and are ignored in the other ones:
 813                  *   - IXGBE_ADVTXD_DCMD_IFCS
 814                  *   - IXGBE_ADVTXD_MAC_1588
 815                  *   - IXGBE_ADVTXD_DCMD_VLE
 816                  *
 817                  * The following bits must only be set in the last Data
 818                  * Descriptor:
 819                  *   - IXGBE_TXD_CMD_EOP
 820                  *
 821                  * The following bits can be set in any Data Descriptor, but
 822                  * are only set in the last Data Descriptor:
 823                  *   - IXGBE_TXD_CMD_RS
 824                  */
 825                 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
 826                         IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
 827
 828 #ifdef RTE_LIBRTE_IEEE1588
 829                 if (ol_flags & PKT_TX_IEEE1588_TMST)
 830                         cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
 831 #endif
 832
 833                 olinfo_status = 0;
 834                 if (tx_ol_req) {
 835
 836                         if (ol_flags & PKT_TX_TCP_SEG) {
 837                                 /* when TSO is on, paylen in descriptor is the
 838                                  * not the packet len but the tcp payload len */
 839                                 pkt_len -= (tx_offload.l2_len +
 840                                         tx_offload.l3_len + tx_offload.l4_len);
 841                         }
 842
 843                         /*
 844                          * Setup the TX Advanced Context Descriptor if required
 845                          */
 846                         if (new_ctx) {
 847                                 volatile struct ixgbe_adv_tx_context_desc *
 848                                     ctx_txd;
 849
 850                                 ctx_txd = (volatile struct
 851                                     ixgbe_adv_tx_context_desc *)
 852                                     &txr[tx_id];
 853
 854                                 txn = &sw_ring[txe->next_id];
 855                                 rte_prefetch0(&txn->mbuf->pool);
 856
 857                                 if (txe->mbuf != NULL) {
 858                                         rte_pktmbuf_free_seg(txe->mbuf);
 859                                         txe->mbuf = NULL;
 860                                 }
 861
 862                                 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
 863                                         tx_offload,
 864                                         rte_security_dynfield(tx_pkt));
 865
 866                                 txe->last_id = tx_last;
 867                                 tx_id = txe->next_id;
 868                                 txe = txn;
 869                         }
 870
 871                         /*
 872                          * Setup the TX Advanced Data Descriptor,
 873                          * This path will go through
 874                          * whatever new/reuse the context descriptor
 875                          */
 876                         cmd_type_len  |= tx_desc_ol_flags_to_cmdtype(ol_flags);
 877                         olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
 878                         olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
 879                 }
 880
 881                 olinfo_status |= (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
 882 #ifdef RTE_LIB_SECURITY
 883                 if (use_ipsec)
 884                         olinfo_status |= IXGBE_ADVTXD_POPTS_IPSEC;
 885 #endif
 886
 887                 m_seg = tx_pkt;
 888                 do {
 889                         txd = &txr[tx_id];
 890                         txn = &sw_ring[txe->next_id];
 891                         rte_prefetch0(&txn->mbuf->pool);
 892
 893                         if (txe->mbuf != NULL)
 894                                 rte_pktmbuf_free_seg(txe->mbuf);
 895                         txe->mbuf = m_seg;
 896
 897                         /*
 898                          * Set up Transmit Data Descriptor.
 899                          */
 900                         slen = m_seg->data_len;
 901                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
 902                         txd->read.buffer_addr =
 903                                 rte_cpu_to_le_64(buf_dma_addr);
 904                         txd->read.cmd_type_len =
 905                                 rte_cpu_to_le_32(cmd_type_len | slen);
 906                         txd->read.olinfo_status =
 907                                 rte_cpu_to_le_32(olinfo_status);
 908                         txe->last_id = tx_last;
 909                         tx_id = txe->next_id;
 910                         txe = txn;
 911                         m_seg = m_seg->next;
 912                 } while (m_seg != NULL);
 913
 914                 /*
 915                  * The last packet data descriptor needs End Of Packet (EOP)
 916                  */
 917                 cmd_type_len |= IXGBE_TXD_CMD_EOP;
 918                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
 919                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
 920
 921                 /* Set RS bit only on threshold packets' last descriptor */
 922                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
 923                         PMD_TX_LOG(DEBUG,
 924                                    "Setting RS bit on TXD id="
 925                                    "%4u (port=%d queue=%d)",
 926                                    tx_last, txq->port_id, txq->queue_id);
 927
 928                         cmd_type_len |= IXGBE_TXD_CMD_RS;
 929
 930                         /* Update txq RS bit counters */
 931                         txq->nb_tx_used = 0;
 932                         txp = NULL;
 933                 } else
 934                         txp = txd;
 935
 936                 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
 937         }
 938
 939 end_of_tx:
 940         /* set RS on last packet in the burst */
 941         if (txp != NULL)
 942                 txp->read.cmd_type_len |= rte_cpu_to_le_32(IXGBE_TXD_CMD_RS);
 943
 944         rte_wmb();
 945
 946         /*
 947          * Set the Transmit Descriptor Tail (TDT)
 948          */
 949         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
 950                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
 951                    (unsigned) tx_id, (unsigned) nb_tx);
 952         IXGBE_PCI_REG_WC_WRITE_RELAXED(txq->tdt_reg_addr, tx_id);
 953         txq->tx_tail = tx_id;
 954
 955         return nb_tx;
 956 }
 957
 958 /*********************************************************************
 959  *
 960  *  TX prep functions
 961  *
 962  **********************************************************************/
 963 uint16_t
 964 ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 965 {
 966         int i, ret;
 967         uint64_t ol_flags;
 968         struct rte_mbuf *m;
 969         struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
 970
 971         for (i = 0; i < nb_pkts; i++) {
 972                 m = tx_pkts[i];
 973                 ol_flags = m->ol_flags;
 974
 975                 /**
 976                  * Check if packet meets requirements for number of segments
 977                  *
 978                  * NOTE: for ixgbe it's always (40 - WTHRESH) for both TSO and
 979                  *       non-TSO
 980                  */
 981
 982                 if (m->nb_segs > IXGBE_TX_MAX_SEG - txq->wthresh) {
 983                         rte_errno = EINVAL;
 984                         return i;
 985                 }
 986
 987                 if (ol_flags & IXGBE_TX_OFFLOAD_NOTSUP_MASK) {
 988                         rte_errno = ENOTSUP;
 989                         return i;
 990                 }
 991
 992                 /* check the size of packet */
 993                 if (m->pkt_len < IXGBE_TX_MIN_PKT_LEN) {
 994                         rte_errno = EINVAL;
 995                         return i;
 996                 }
 997
 998 #ifdef RTE_ETHDEV_DEBUG_TX
 999                 ret = rte_validate_tx_offload(m);
1000                 if (ret != 0) {
1001                         rte_errno = -ret;
1002                         return i;
1003                 }
1004 #endif
1005                 ret = rte_net_intel_cksum_prepare(m);
1006                 if (ret != 0) {
1007                         rte_errno = -ret;
1008                         return i;
1009                 }
1010         }
1011
1012         return i;
1013 }
1014
1015 /*********************************************************************
1016  *
1017  *  RX functions
1018  *
1019  **********************************************************************/
1020
1021 #define IXGBE_PACKET_TYPE_ETHER                         0X00
1022 #define IXGBE_PACKET_TYPE_IPV4                          0X01
1023 #define IXGBE_PACKET_TYPE_IPV4_TCP                      0X11
1024 #define IXGBE_PACKET_TYPE_IPV4_UDP                      0X21
1025 #define IXGBE_PACKET_TYPE_IPV4_SCTP                     0X41
1026 #define IXGBE_PACKET_TYPE_IPV4_EXT                      0X03
1027 #define IXGBE_PACKET_TYPE_IPV4_EXT_TCP                  0X13
1028 #define IXGBE_PACKET_TYPE_IPV4_EXT_UDP                  0X23
1029 #define IXGBE_PACKET_TYPE_IPV4_EXT_SCTP                 0X43
1030 #define IXGBE_PACKET_TYPE_IPV6                          0X04
1031 #define IXGBE_PACKET_TYPE_IPV6_TCP                      0X14
1032 #define IXGBE_PACKET_TYPE_IPV6_UDP                      0X24
1033 #define IXGBE_PACKET_TYPE_IPV6_SCTP                     0X44
1034 #define IXGBE_PACKET_TYPE_IPV6_EXT                      0X0C
1035 #define IXGBE_PACKET_TYPE_IPV6_EXT_TCP                  0X1C
1036 #define IXGBE_PACKET_TYPE_IPV6_EXT_UDP                  0X2C
1037 #define IXGBE_PACKET_TYPE_IPV6_EXT_SCTP                 0X4C
1038 #define IXGBE_PACKET_TYPE_IPV4_IPV6                     0X05
1039 #define IXGBE_PACKET_TYPE_IPV4_IPV6_TCP                 0X15
1040 #define IXGBE_PACKET_TYPE_IPV4_IPV6_UDP                 0X25
1041 #define IXGBE_PACKET_TYPE_IPV4_IPV6_SCTP                0X45
1042 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6                 0X07
1043 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_TCP             0X17
1044 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_UDP             0X27
1045 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_SCTP            0X47
1046 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT                 0X0D
1047 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP             0X1D
1048 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP             0X2D
1049 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_SCTP            0X4D
1050 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT             0X0F
1051 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_TCP         0X1F
1052 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_UDP         0X2F
1053 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_SCTP        0X4F
1054
1055 #define IXGBE_PACKET_TYPE_NVGRE                   0X00
1056 #define IXGBE_PACKET_TYPE_NVGRE_IPV4              0X01
1057 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_TCP          0X11
1058 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_UDP          0X21
1059 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_SCTP         0X41
1060 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT          0X03
1061 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_TCP      0X13
1062 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_UDP      0X23
1063 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_SCTP     0X43
1064 #define IXGBE_PACKET_TYPE_NVGRE_IPV6              0X04
1065 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_TCP          0X14
1066 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_UDP          0X24
1067 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_SCTP         0X44
1068 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT          0X0C
1069 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_TCP      0X1C
1070 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_UDP      0X2C
1071 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_SCTP     0X4C
1072 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6         0X05
1073 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_TCP     0X15
1074 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_UDP     0X25
1075 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT     0X0D
1076 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_TCP 0X1D
1077 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_UDP 0X2D
1078
1079 #define IXGBE_PACKET_TYPE_VXLAN                   0X80
1080 #define IXGBE_PACKET_TYPE_VXLAN_IPV4              0X81
1081 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_TCP          0x91
1082 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_UDP          0xA1
1083 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_SCTP         0xC1
1084 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT          0x83
1085 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_TCP      0X93
1086 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_UDP      0XA3
1087 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_SCTP     0XC3
1088 #define IXGBE_PACKET_TYPE_VXLAN_IPV6              0X84
1089 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_TCP          0X94
1090 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_UDP          0XA4
1091 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_SCTP         0XC4
1092 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT          0X8C
1093 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_TCP      0X9C
1094 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_UDP      0XAC
1095 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_SCTP     0XCC
1096 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6         0X85
1097 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_TCP     0X95
1098 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_UDP     0XA5
1099 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT     0X8D
1100 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_TCP 0X9D
1101 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_UDP 0XAD
1102
1103 /**
1104  * Use 2 different table for normal packet and tunnel packet
1105  * to save the space.
1106  */
1107 const uint32_t
1108         ptype_table[IXGBE_PACKET_TYPE_MAX] __rte_cache_aligned = {
1109         [IXGBE_PACKET_TYPE_ETHER] = RTE_PTYPE_L2_ETHER,
1110         [IXGBE_PACKET_TYPE_IPV4] = RTE_PTYPE_L2_ETHER |
1111                 RTE_PTYPE_L3_IPV4,
1112         [IXGBE_PACKET_TYPE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1113                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
1114         [IXGBE_PACKET_TYPE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1115                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
1116         [IXGBE_PACKET_TYPE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1117                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP,
1118         [IXGBE_PACKET_TYPE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1119                 RTE_PTYPE_L3_IPV4_EXT,
1120         [IXGBE_PACKET_TYPE_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1121                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_TCP,
1122         [IXGBE_PACKET_TYPE_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1123                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_UDP,
1124         [IXGBE_PACKET_TYPE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1125                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_SCTP,
1126         [IXGBE_PACKET_TYPE_IPV6] = RTE_PTYPE_L2_ETHER |
1127                 RTE_PTYPE_L3_IPV6,
1128         [IXGBE_PACKET_TYPE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1129                 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
1130         [IXGBE_PACKET_TYPE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1131                 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
1132         [IXGBE_PACKET_TYPE_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1133                 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_SCTP,
1134         [IXGBE_PACKET_TYPE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1135                 RTE_PTYPE_L3_IPV6_EXT,
1136         [IXGBE_PACKET_TYPE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1137                 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,
1138         [IXGBE_PACKET_TYPE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1139                 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
1140         [IXGBE_PACKET_TYPE_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1141                 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_SCTP,
1142         [IXGBE_PACKET_TYPE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1143                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1144                 RTE_PTYPE_INNER_L3_IPV6,
1145         [IXGBE_PACKET_TYPE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1146                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1147                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1148         [IXGBE_PACKET_TYPE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1149                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1150         RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1151         [IXGBE_PACKET_TYPE_IPV4_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1152                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1153                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
1154         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6] = RTE_PTYPE_L2_ETHER |
1155                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1156                 RTE_PTYPE_INNER_L3_IPV6,
1157         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1158                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1159                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1160         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1161                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1162                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1163         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1164                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1165                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
1166         [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1167                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1168                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1169         [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1170                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1171                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1172         [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1173                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1174                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1175         [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1176                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1177                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
1178         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1179                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1180                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1181         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1182                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1183                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1184         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1185                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1186                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1187         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_SCTP] =
1188                 RTE_PTYPE_L2_ETHER |
1189                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1190                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
1191 };
1192
1193 const uint32_t
1194         ptype_table_tn[IXGBE_PACKET_TYPE_TN_MAX] __rte_cache_aligned = {
1195         [IXGBE_PACKET_TYPE_NVGRE] = RTE_PTYPE_L2_ETHER |
1196                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1197                 RTE_PTYPE_INNER_L2_ETHER,
1198         [IXGBE_PACKET_TYPE_NVGRE_IPV4] = RTE_PTYPE_L2_ETHER |
1199                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1200                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1201         [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1202                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1203                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT,
1204         [IXGBE_PACKET_TYPE_NVGRE_IPV6] = RTE_PTYPE_L2_ETHER |
1205                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1206                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6,
1207         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1208                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1209                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1210         [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1211                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1212                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT,
1213         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1214                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1215                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1216         [IXGBE_PACKET_TYPE_NVGRE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1217                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1218                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1219                 RTE_PTYPE_INNER_L4_TCP,
1220         [IXGBE_PACKET_TYPE_NVGRE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1221                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1222                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1223                 RTE_PTYPE_INNER_L4_TCP,
1224         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1225                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1226                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1227         [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1228                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1229                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1230                 RTE_PTYPE_INNER_L4_TCP,
1231         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_TCP] =
1232                 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1233                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_INNER_L2_ETHER |
1234                 RTE_PTYPE_INNER_L3_IPV4,
1235         [IXGBE_PACKET_TYPE_NVGRE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1236                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1237                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1238                 RTE_PTYPE_INNER_L4_UDP,
1239         [IXGBE_PACKET_TYPE_NVGRE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1240                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1241                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1242                 RTE_PTYPE_INNER_L4_UDP,
1243         [IXGBE_PACKET_TYPE_NVGRE_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1244                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1245                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1246                 RTE_PTYPE_INNER_L4_SCTP,
1247         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1248                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1249                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1250         [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1251                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1252                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1253                 RTE_PTYPE_INNER_L4_UDP,
1254         [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1255                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1256                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1257                 RTE_PTYPE_INNER_L4_SCTP,
1258         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_UDP] =
1259                 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1260                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_INNER_L2_ETHER |
1261                 RTE_PTYPE_INNER_L3_IPV4,
1262         [IXGBE_PACKET_TYPE_NVGRE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1263                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1264                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1265                 RTE_PTYPE_INNER_L4_SCTP,
1266         [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1267                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1268                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
1269                 RTE_PTYPE_INNER_L4_SCTP,
1270         [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1271                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1272                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
1273                 RTE_PTYPE_INNER_L4_TCP,
1274         [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1275                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1276                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
1277                 RTE_PTYPE_INNER_L4_UDP,
1278
1279         [IXGBE_PACKET_TYPE_VXLAN] = RTE_PTYPE_L2_ETHER |
1280                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1281                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER,
1282         [IXGBE_PACKET_TYPE_VXLAN_IPV4] = RTE_PTYPE_L2_ETHER |
1283                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1284                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1285                 RTE_PTYPE_INNER_L3_IPV4,
1286         [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1287                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1288                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1289                 RTE_PTYPE_INNER_L3_IPV4_EXT,
1290         [IXGBE_PACKET_TYPE_VXLAN_IPV6] = RTE_PTYPE_L2_ETHER |
1291                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1292                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1293                 RTE_PTYPE_INNER_L3_IPV6,
1294         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1295                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1296                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1297                 RTE_PTYPE_INNER_L3_IPV4,
1298         [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1299                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1300                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1301                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1302         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1303                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1304                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1305                 RTE_PTYPE_INNER_L3_IPV4,
1306         [IXGBE_PACKET_TYPE_VXLAN_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1307                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1308                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1309                 RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_TCP,
1310         [IXGBE_PACKET_TYPE_VXLAN_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1311                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1312                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1313                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1314         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1315                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1316                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1317                 RTE_PTYPE_INNER_L3_IPV4,
1318         [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1319                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1320                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1321                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1322         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_TCP] =
1323                 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1324                 RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN |
1325                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1326         [IXGBE_PACKET_TYPE_VXLAN_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1327                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1328                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1329                 RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_UDP,
1330         [IXGBE_PACKET_TYPE_VXLAN_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1331                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1332                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1333                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1334         [IXGBE_PACKET_TYPE_VXLAN_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1335                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1336                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1337                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
1338         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1339                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1340                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1341                 RTE_PTYPE_INNER_L3_IPV4,
1342         [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1343                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1344                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1345                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1346         [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1347                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1348                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1349                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
1350         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_UDP] =
1351                 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1352                 RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN |
1353                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1354         [IXGBE_PACKET_TYPE_VXLAN_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1355                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1356                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1357                 RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_SCTP,
1358         [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1359                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1360                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1361                 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_SCTP,
1362         [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1363                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1364                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1365                 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_TCP,
1366         [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1367                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1368                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1369                 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
1370 };
1371
1372 static int
1373 ixgbe_monitor_callback(const uint64_t value,
1374                 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
1375 {
1376         const uint64_t m = rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD);
1377         /*
1378          * we expect the DD bit to be set to 1 if this descriptor was already
1379          * written to.
1380          */
1381         return (value & m) == m ? -1 : 0;
1382 }
1383
1384 int
1385 ixgbe_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
1386 {
1387         volatile union ixgbe_adv_rx_desc *rxdp;
1388         struct ixgbe_rx_queue *rxq = rx_queue;
1389         uint16_t desc;
1390
1391         desc = rxq->rx_tail;
1392         rxdp = &rxq->rx_ring[desc];
1393         /* watch for changes in status bit */
1394         pmc->addr = &rxdp->wb.upper.status_error;
1395
1396         /* comparison callback */
1397         pmc->fn = ixgbe_monitor_callback;
1398
1399         /* the registers are 32-bit */
1400         pmc->size = sizeof(uint32_t);
1401
1402         return 0;
1403 }
1404
1405 /* @note: fix ixgbe_dev_supported_ptypes_get() if any change here. */
1406 static inline uint32_t
1407 ixgbe_rxd_pkt_info_to_pkt_type(uint32_t pkt_info, uint16_t ptype_mask)
1408 {
1409
1410         if (unlikely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
1411                 return RTE_PTYPE_UNKNOWN;
1412
1413         pkt_info = (pkt_info >> IXGBE_PACKET_TYPE_SHIFT) & ptype_mask;
1414
1415         /* For tunnel packet */
1416         if (pkt_info & IXGBE_PACKET_TYPE_TUNNEL_BIT) {
1417                 /* Remove the tunnel bit to save the space. */
1418                 pkt_info &= IXGBE_PACKET_TYPE_MASK_TUNNEL;
1419                 return ptype_table_tn[pkt_info];
1420         }
1421
1422         /**
1423          * For x550, if it's not tunnel,
1424          * tunnel type bit should be set to 0.
1425          * Reuse 82599's mask.
1426          */
1427         pkt_info &= IXGBE_PACKET_TYPE_MASK_82599;
1428
1429         return ptype_table[pkt_info];
1430 }
1431
1432 static inline uint64_t
1433 ixgbe_rxd_pkt_info_to_pkt_flags(uint16_t pkt_info)
1434 {
1435         static uint64_t ip_rss_types_map[16] __rte_cache_aligned = {
1436                 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
1437                 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
1438                 PKT_RX_RSS_HASH, 0, 0, 0,
1439                 0, 0, 0,  PKT_RX_FDIR,
1440         };
1441 #ifdef RTE_LIBRTE_IEEE1588
1442         static uint64_t ip_pkt_etqf_map[8] = {
1443                 0, 0, 0, PKT_RX_IEEE1588_PTP,
1444                 0, 0, 0, 0,
1445         };
1446
1447         if (likely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
1448                 return ip_pkt_etqf_map[(pkt_info >> 4) & 0X07] |
1449                                 ip_rss_types_map[pkt_info & 0XF];
1450         else
1451                 return ip_rss_types_map[pkt_info & 0XF];
1452 #else
1453         return ip_rss_types_map[pkt_info & 0XF];
1454 #endif
1455 }
1456
1457 static inline uint64_t
1458 rx_desc_status_to_pkt_flags(uint32_t rx_status, uint64_t vlan_flags)
1459 {
1460         uint64_t pkt_flags;
1461
1462         /*
1463          * Check if VLAN present only.
1464          * Do not check whether L3/L4 rx checksum done by NIC or not,
1465          * That can be found from rte_eth_rxmode.offloads flag
1466          */
1467         pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ?  vlan_flags : 0;
1468
1469 #ifdef RTE_LIBRTE_IEEE1588
1470         if (rx_status & IXGBE_RXD_STAT_TMST)
1471                 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
1472 #endif
1473         return pkt_flags;
1474 }
1475
1476 static inline uint64_t
1477 rx_desc_error_to_pkt_flags(uint32_t rx_status, uint16_t pkt_info,
1478                            uint8_t rx_udp_csum_zero_err)
1479 {
1480         uint64_t pkt_flags;
1481
1482         /*
1483          * Bit 31: IPE, IPv4 checksum error
1484          * Bit 30: L4I, L4I integrity error
1485          */
1486         static uint64_t error_to_pkt_flags_map[4] = {
1487                 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD,
1488                 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
1489                 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD,
1490                 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
1491         };
1492         pkt_flags = error_to_pkt_flags_map[(rx_status >>
1493                 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
1494
1495         /* Mask out the bad UDP checksum error if the hardware has UDP zero
1496          * checksum error issue, so that the software application will then
1497          * have to recompute the checksum itself if needed.
1498          */
1499         if ((rx_status & IXGBE_RXDADV_ERR_TCPE) &&
1500             (pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1501             rx_udp_csum_zero_err)
1502                 pkt_flags &= ~PKT_RX_L4_CKSUM_BAD;
1503
1504         if ((rx_status & IXGBE_RXD_STAT_OUTERIPCS) &&
1505             (rx_status & IXGBE_RXDADV_ERR_OUTERIPER)) {
1506                 pkt_flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
1507         }
1508
1509 #ifdef RTE_LIB_SECURITY
1510         if (rx_status & IXGBE_RXD_STAT_SECP) {
1511                 pkt_flags |= PKT_RX_SEC_OFFLOAD;
1512                 if (rx_status & IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG)
1513                         pkt_flags |= PKT_RX_SEC_OFFLOAD_FAILED;
1514         }
1515 #endif
1516
1517         return pkt_flags;
1518 }
1519
1520 /*
1521  * LOOK_AHEAD defines how many desc statuses to check beyond the
1522  * current descriptor.
1523  * It must be a pound define for optimal performance.
1524  * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
1525  * function only works with LOOK_AHEAD=8.
1526  */
1527 #define LOOK_AHEAD 8
1528 #if (LOOK_AHEAD != 8)
1529 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
1530 #endif
1531 static inline int
1532 ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
1533 {
1534         volatile union ixgbe_adv_rx_desc *rxdp;
1535         struct ixgbe_rx_entry *rxep;
1536         struct rte_mbuf *mb;
1537         uint16_t pkt_len;
1538         uint64_t pkt_flags;
1539         int nb_dd;
1540         uint32_t s[LOOK_AHEAD];
1541         uint32_t pkt_info[LOOK_AHEAD];
1542         int i, j, nb_rx = 0;
1543         uint32_t status;
1544         uint64_t vlan_flags = rxq->vlan_flags;
1545
1546         /* get references to current descriptor and S/W ring entry */
1547         rxdp = &rxq->rx_ring[rxq->rx_tail];
1548         rxep = &rxq->sw_ring[rxq->rx_tail];
1549
1550         status = rxdp->wb.upper.status_error;
1551         /* check to make sure there is at least 1 packet to receive */
1552         if (!(status & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1553                 return 0;
1554
1555         /*
1556          * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
1557          * reference packets that are ready to be received.
1558          */
1559         for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
1560              i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD) {
1561                 /* Read desc statuses backwards to avoid race condition */
1562                 for (j = 0; j < LOOK_AHEAD; j++)
1563                         s[j] = rte_le_to_cpu_32(rxdp[j].wb.upper.status_error);
1564
1565                 rte_smp_rmb();
1566
1567                 /* Compute how many status bits were set */
1568                 for (nb_dd = 0; nb_dd < LOOK_AHEAD &&
1569                                 (s[nb_dd] & IXGBE_RXDADV_STAT_DD); nb_dd++)
1570                         ;
1571
1572                 for (j = 0; j < nb_dd; j++)
1573                         pkt_info[j] = rte_le_to_cpu_32(rxdp[j].wb.lower.
1574                                                        lo_dword.data);
1575
1576                 nb_rx += nb_dd;
1577
1578                 /* Translate descriptor info to mbuf format */
1579                 for (j = 0; j < nb_dd; ++j) {
1580                         mb = rxep[j].mbuf;
1581                         pkt_len = rte_le_to_cpu_16(rxdp[j].wb.upper.length) -
1582                                   rxq->crc_len;
1583                         mb->data_len = pkt_len;
1584                         mb->pkt_len = pkt_len;
1585                         mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
1586
1587                         /* convert descriptor fields to rte mbuf flags */
1588                         pkt_flags = rx_desc_status_to_pkt_flags(s[j],
1589                                 vlan_flags);
1590                         pkt_flags |= rx_desc_error_to_pkt_flags(s[j],
1591                                         (uint16_t)pkt_info[j],
1592                                         rxq->rx_udp_csum_zero_err);
1593                         pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags
1594                                         ((uint16_t)pkt_info[j]);
1595                         mb->ol_flags = pkt_flags;
1596                         mb->packet_type =
1597                                 ixgbe_rxd_pkt_info_to_pkt_type
1598                                         (pkt_info[j], rxq->pkt_type_mask);
1599
1600                         if (likely(pkt_flags & PKT_RX_RSS_HASH))
1601                                 mb->hash.rss = rte_le_to_cpu_32(
1602                                     rxdp[j].wb.lower.hi_dword.rss);
1603                         else if (pkt_flags & PKT_RX_FDIR) {
1604                                 mb->hash.fdir.hash = rte_le_to_cpu_16(
1605                                     rxdp[j].wb.lower.hi_dword.csum_ip.csum) &
1606                                     IXGBE_ATR_HASH_MASK;
1607                                 mb->hash.fdir.id = rte_le_to_cpu_16(
1608                                     rxdp[j].wb.lower.hi_dword.csum_ip.ip_id);
1609                         }
1610                 }
1611
1612                 /* Move mbuf pointers from the S/W ring to the stage */
1613                 for (j = 0; j < LOOK_AHEAD; ++j) {
1614                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1615                 }
1616
1617                 /* stop if all requested packets could not be received */
1618                 if (nb_dd != LOOK_AHEAD)
1619                         break;
1620         }
1621
1622         /* clear software ring entries so we can cleanup correctly */
1623         for (i = 0; i < nb_rx; ++i) {
1624                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1625         }
1626
1627
1628         return nb_rx;
1629 }
1630
1631 static inline int
1632 ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq, bool reset_mbuf)
1633 {
1634         volatile union ixgbe_adv_rx_desc *rxdp;
1635         struct ixgbe_rx_entry *rxep;
1636         struct rte_mbuf *mb;
1637         uint16_t alloc_idx;
1638         __le64 dma_addr;
1639         int diag, i;
1640
1641         /* allocate buffers in bulk directly into the S/W ring */
1642         alloc_idx = rxq->rx_free_trigger - (rxq->rx_free_thresh - 1);
1643         rxep = &rxq->sw_ring[alloc_idx];
1644         diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1645                                     rxq->rx_free_thresh);
1646         if (unlikely(diag != 0))
1647                 return -ENOMEM;
1648
1649         rxdp = &rxq->rx_ring[alloc_idx];
1650         for (i = 0; i < rxq->rx_free_thresh; ++i) {
1651                 /* populate the static rte mbuf fields */
1652                 mb = rxep[i].mbuf;
1653                 if (reset_mbuf) {
1654                         mb->port = rxq->port_id;
1655                 }
1656
1657                 rte_mbuf_refcnt_set(mb, 1);
1658                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1659
1660                 /* populate the descriptors */
1661                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1662                 rxdp[i].read.hdr_addr = 0;
1663                 rxdp[i].read.pkt_addr = dma_addr;
1664         }
1665
1666         /* update state of internal queue structure */
1667         rxq->rx_free_trigger = rxq->rx_free_trigger + rxq->rx_free_thresh;
1668         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1669                 rxq->rx_free_trigger = rxq->rx_free_thresh - 1;
1670
1671         /* no errors */
1672         return 0;
1673 }
1674
1675 static inline uint16_t
1676 ixgbe_rx_fill_from_stage(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1677                          uint16_t nb_pkts)
1678 {
1679         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1680         int i;
1681
1682         /* how many packets are ready to return? */
1683         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1684
1685         /* copy mbuf pointers to the application's packet list */
1686         for (i = 0; i < nb_pkts; ++i)
1687                 rx_pkts[i] = stage[i];
1688
1689         /* update internal queue state */
1690         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1691         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1692
1693         return nb_pkts;
1694 }
1695
1696 static inline uint16_t
1697 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1698              uint16_t nb_pkts)
1699 {
1700         struct ixgbe_rx_queue *rxq = (struct ixgbe_rx_queue *)rx_queue;
1701         uint16_t nb_rx = 0;
1702
1703         /* Any previously recv'd pkts will be returned from the Rx stage */
1704         if (rxq->rx_nb_avail)
1705                 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1706
1707         /* Scan the H/W ring for packets to receive */
1708         nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1709
1710         /* update internal queue state */
1711         rxq->rx_next_avail = 0;
1712         rxq->rx_nb_avail = nb_rx;
1713         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1714
1715         /* if required, allocate new buffers to replenish descriptors */
1716         if (rxq->rx_tail > rxq->rx_free_trigger) {
1717                 uint16_t cur_free_trigger = rxq->rx_free_trigger;
1718
1719                 if (ixgbe_rx_alloc_bufs(rxq, true) != 0) {
1720                         int i, j;
1721
1722                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1723                                    "queue_id=%u", (unsigned) rxq->port_id,
1724                                    (unsigned) rxq->queue_id);
1725
1726                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1727                                 rxq->rx_free_thresh;
1728
1729                         /*
1730                          * Need to rewind any previous receives if we cannot
1731                          * allocate new buffers to replenish the old ones.
1732                          */
1733                         rxq->rx_nb_avail = 0;
1734                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1735                         for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1736                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1737
1738                         return 0;
1739                 }
1740
1741                 /* update tail pointer */
1742                 rte_wmb();
1743                 IXGBE_PCI_REG_WC_WRITE_RELAXED(rxq->rdt_reg_addr,
1744                                             cur_free_trigger);
1745         }
1746
1747         if (rxq->rx_tail >= rxq->nb_rx_desc)
1748                 rxq->rx_tail = 0;
1749
1750         /* received any packets this loop? */
1751         if (rxq->rx_nb_avail)
1752                 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1753
1754         return 0;
1755 }
1756
1757 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1758 uint16_t
1759 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1760                            uint16_t nb_pkts)
1761 {
1762         uint16_t nb_rx;
1763
1764         if (unlikely(nb_pkts == 0))
1765                 return 0;
1766
1767         if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1768                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1769
1770         /* request is relatively large, chunk it up */
1771         nb_rx = 0;
1772         while (nb_pkts) {
1773                 uint16_t ret, n;
1774
1775                 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1776                 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1777                 nb_rx = (uint16_t)(nb_rx + ret);
1778                 nb_pkts = (uint16_t)(nb_pkts - ret);
1779                 if (ret < n)
1780                         break;
1781         }
1782
1783         return nb_rx;
1784 }
1785
1786 uint16_t
1787 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1788                 uint16_t nb_pkts)
1789 {
1790         struct ixgbe_rx_queue *rxq;
1791         volatile union ixgbe_adv_rx_desc *rx_ring;
1792         volatile union ixgbe_adv_rx_desc *rxdp;
1793         struct ixgbe_rx_entry *sw_ring;
1794         struct ixgbe_rx_entry *rxe;
1795         struct rte_mbuf *rxm;
1796         struct rte_mbuf *nmb;
1797         union ixgbe_adv_rx_desc rxd;
1798         uint64_t dma_addr;
1799         uint32_t staterr;
1800         uint32_t pkt_info;
1801         uint16_t pkt_len;
1802         uint16_t rx_id;
1803         uint16_t nb_rx;
1804         uint16_t nb_hold;
1805         uint64_t pkt_flags;
1806         uint64_t vlan_flags;
1807
1808         nb_rx = 0;
1809         nb_hold = 0;
1810         rxq = rx_queue;
1811         rx_id = rxq->rx_tail;
1812         rx_ring = rxq->rx_ring;
1813         sw_ring = rxq->sw_ring;
1814         vlan_flags = rxq->vlan_flags;
1815         while (nb_rx < nb_pkts) {
1816                 /*
1817                  * The order of operations here is important as the DD status
1818                  * bit must not be read after any other descriptor fields.
1819                  * rx_ring and rxdp are pointing to volatile data so the order
1820                  * of accesses cannot be reordered by the compiler. If they were
1821                  * not volatile, they could be reordered which could lead to
1822                  * using invalid descriptor fields when read from rxd.
1823                  */
1824                 rxdp = &rx_ring[rx_id];
1825                 staterr = rxdp->wb.upper.status_error;
1826                 if (!(staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1827                         break;
1828                 rxd = *rxdp;
1829
1830                 /*
1831                  * End of packet.
1832                  *
1833                  * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1834                  * is likely to be invalid and to be dropped by the various
1835                  * validation checks performed by the network stack.
1836                  *
1837                  * Allocate a new mbuf to replenish the RX ring descriptor.
1838                  * If the allocation fails:
1839                  *    - arrange for that RX descriptor to be the first one
1840                  *      being parsed the next time the receive function is
1841                  *      invoked [on the same queue].
1842                  *
1843                  *    - Stop parsing the RX ring and return immediately.
1844                  *
1845                  * This policy do not drop the packet received in the RX
1846                  * descriptor for which the allocation of a new mbuf failed.
1847                  * Thus, it allows that packet to be later retrieved if
1848                  * mbuf have been freed in the mean time.
1849                  * As a side effect, holding RX descriptors instead of
1850                  * systematically giving them back to the NIC may lead to
1851                  * RX ring exhaustion situations.
1852                  * However, the NIC can gracefully prevent such situations
1853                  * to happen by sending specific "back-pressure" flow control
1854                  * frames to its peer(s).
1855                  */
1856                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1857                            "ext_err_stat=0x%08x pkt_len=%u",
1858                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1859                            (unsigned) rx_id, (unsigned) staterr,
1860                            (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1861
1862                 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
1863                 if (nmb == NULL) {
1864                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1865                                    "queue_id=%u", (unsigned) rxq->port_id,
1866                                    (unsigned) rxq->queue_id);
1867                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1868                         break;
1869                 }
1870
1871                 nb_hold++;
1872                 rxe = &sw_ring[rx_id];
1873                 rx_id++;
1874                 if (rx_id == rxq->nb_rx_desc)
1875                         rx_id = 0;
1876
1877                 /* Prefetch next mbuf while processing current one. */
1878                 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1879
1880                 /*
1881                  * When next RX descriptor is on a cache-line boundary,
1882                  * prefetch the next 4 RX descriptors and the next 8 pointers
1883                  * to mbufs.
1884                  */
1885                 if ((rx_id & 0x3) == 0) {
1886                         rte_ixgbe_prefetch(&rx_ring[rx_id]);
1887                         rte_ixgbe_prefetch(&sw_ring[rx_id]);
1888                 }
1889
1890                 rxm = rxe->mbuf;
1891                 rxe->mbuf = nmb;
1892                 dma_addr =
1893                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1894                 rxdp->read.hdr_addr = 0;
1895                 rxdp->read.pkt_addr = dma_addr;
1896
1897                 /*
1898                  * Initialize the returned mbuf.
1899                  * 1) setup generic mbuf fields:
1900                  *    - number of segments,
1901                  *    - next segment,
1902                  *    - packet length,
1903                  *    - RX port identifier.
1904                  * 2) integrate hardware offload data, if any:
1905                  *    - RSS flag & hash,
1906                  *    - IP checksum flag,
1907                  *    - VLAN TCI, if any,
1908                  *    - error flags.
1909                  */
1910                 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1911                                       rxq->crc_len);
1912                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1913                 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1914                 rxm->nb_segs = 1;
1915                 rxm->next = NULL;
1916                 rxm->pkt_len = pkt_len;
1917                 rxm->data_len = pkt_len;
1918                 rxm->port = rxq->port_id;
1919
1920                 pkt_info = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1921                 /* Only valid if PKT_RX_VLAN set in pkt_flags */
1922                 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1923
1924                 pkt_flags = rx_desc_status_to_pkt_flags(staterr, vlan_flags);
1925                 pkt_flags = pkt_flags |
1926                         rx_desc_error_to_pkt_flags(staterr, (uint16_t)pkt_info,
1927                                                    rxq->rx_udp_csum_zero_err);
1928                 pkt_flags = pkt_flags |
1929                         ixgbe_rxd_pkt_info_to_pkt_flags((uint16_t)pkt_info);
1930                 rxm->ol_flags = pkt_flags;
1931                 rxm->packet_type =
1932                         ixgbe_rxd_pkt_info_to_pkt_type(pkt_info,
1933                                                        rxq->pkt_type_mask);
1934
1935                 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1936                         rxm->hash.rss = rte_le_to_cpu_32(
1937                                                 rxd.wb.lower.hi_dword.rss);
1938                 else if (pkt_flags & PKT_RX_FDIR) {
1939                         rxm->hash.fdir.hash = rte_le_to_cpu_16(
1940                                         rxd.wb.lower.hi_dword.csum_ip.csum) &
1941                                         IXGBE_ATR_HASH_MASK;
1942                         rxm->hash.fdir.id = rte_le_to_cpu_16(
1943                                         rxd.wb.lower.hi_dword.csum_ip.ip_id);
1944                 }
1945                 /*
1946                  * Store the mbuf address into the next entry of the array
1947                  * of returned packets.
1948                  */
1949                 rx_pkts[nb_rx++] = rxm;
1950         }
1951         rxq->rx_tail = rx_id;
1952
1953         /*
1954          * If the number of free RX descriptors is greater than the RX free
1955          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1956          * register.
1957          * Update the RDT with the value of the last processed RX descriptor
1958          * minus 1, to guarantee that the RDT register is never equal to the
1959          * RDH register, which creates a "full" ring situtation from the
1960          * hardware point of view...
1961          */
1962         nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1963         if (nb_hold > rxq->rx_free_thresh) {
1964                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1965                            "nb_hold=%u nb_rx=%u",
1966                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1967                            (unsigned) rx_id, (unsigned) nb_hold,
1968                            (unsigned) nb_rx);
1969                 rx_id = (uint16_t) ((rx_id == 0) ?
1970                                      (rxq->nb_rx_desc - 1) : (rx_id - 1));
1971                 IXGBE_PCI_REG_WC_WRITE(rxq->rdt_reg_addr, rx_id);
1972                 nb_hold = 0;
1973         }
1974         rxq->nb_rx_hold = nb_hold;
1975         return nb_rx;
1976 }
1977
1978 /**
1979  * Detect an RSC descriptor.
1980  */
1981 static inline uint32_t
1982 ixgbe_rsc_count(union ixgbe_adv_rx_desc *rx)
1983 {
1984         return (rte_le_to_cpu_32(rx->wb.lower.lo_dword.data) &
1985                 IXGBE_RXDADV_RSCCNT_MASK) >> IXGBE_RXDADV_RSCCNT_SHIFT;
1986 }
1987
1988 /**
1989  * ixgbe_fill_cluster_head_buf - fill the first mbuf of the returned packet
1990  *
1991  * Fill the following info in the HEAD buffer of the Rx cluster:
1992  *    - RX port identifier
1993  *    - hardware offload data, if any:
1994  *      - RSS flag & hash
1995  *      - IP checksum flag
1996  *      - VLAN TCI, if any
1997  *      - error flags
1998  * @head HEAD of the packet cluster
1999  * @desc HW descriptor to get data from
2000  * @rxq Pointer to the Rx queue
2001  */
2002 static inline void
2003 ixgbe_fill_cluster_head_buf(
2004         struct rte_mbuf *head,
2005         union ixgbe_adv_rx_desc *desc,
2006         struct ixgbe_rx_queue *rxq,
2007         uint32_t staterr)
2008 {
2009         uint32_t pkt_info;
2010         uint64_t pkt_flags;
2011
2012         head->port = rxq->port_id;
2013
2014         /* The vlan_tci field is only valid when PKT_RX_VLAN is
2015          * set in the pkt_flags field.
2016          */
2017         head->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);
2018         pkt_info = rte_le_to_cpu_32(desc->wb.lower.lo_dword.data);
2019         pkt_flags = rx_desc_status_to_pkt_flags(staterr, rxq->vlan_flags);
2020         pkt_flags |= rx_desc_error_to_pkt_flags(staterr, (uint16_t)pkt_info,
2021                                                 rxq->rx_udp_csum_zero_err);
2022         pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags((uint16_t)pkt_info);
2023         head->ol_flags = pkt_flags;
2024         head->packet_type =
2025                 ixgbe_rxd_pkt_info_to_pkt_type(pkt_info, rxq->pkt_type_mask);
2026
2027         if (likely(pkt_flags & PKT_RX_RSS_HASH))
2028                 head->hash.rss = rte_le_to_cpu_32(desc->wb.lower.hi_dword.rss);
2029         else if (pkt_flags & PKT_RX_FDIR) {
2030                 head->hash.fdir.hash =
2031                         rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.csum)
2032                                                           & IXGBE_ATR_HASH_MASK;
2033                 head->hash.fdir.id =
2034                         rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.ip_id);
2035         }
2036 }
2037
2038 /**
2039  * ixgbe_recv_pkts_lro - receive handler for and LRO case.
2040  *
2041  * @rx_queue Rx queue handle
2042  * @rx_pkts table of received packets
2043  * @nb_pkts size of rx_pkts table
2044  * @bulk_alloc if TRUE bulk allocation is used for a HW ring refilling
2045  *
2046  * Handles the Rx HW ring completions when RSC feature is configured. Uses an
2047  * additional ring of ixgbe_rsc_entry's that will hold the relevant RSC info.
2048  *
2049  * We use the same logic as in Linux and in FreeBSD ixgbe drivers:
2050  * 1) When non-EOP RSC completion arrives:
2051  *    a) Update the HEAD of the current RSC aggregation cluster with the new
2052  *       segment's data length.
2053  *    b) Set the "next" pointer of the current segment to point to the segment
2054  *       at the NEXTP index.
2055  *    c) Pass the HEAD of RSC aggregation cluster on to the next NEXTP entry
2056  *       in the sw_rsc_ring.
2057  * 2) When EOP arrives we just update the cluster's total length and offload
2058  *    flags and deliver the cluster up to the upper layers. In our case - put it
2059  *    in the rx_pkts table.
2060  *
2061  * Returns the number of received packets/clusters (according to the "bulk
2062  * receive" interface).
2063  */
2064 static inline uint16_t
2065 ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
2066                     bool bulk_alloc)
2067 {
2068         struct ixgbe_rx_queue *rxq = rx_queue;
2069         volatile union ixgbe_adv_rx_desc *rx_ring = rxq->rx_ring;
2070         struct ixgbe_rx_entry *sw_ring = rxq->sw_ring;
2071         struct ixgbe_scattered_rx_entry *sw_sc_ring = rxq->sw_sc_ring;
2072         uint16_t rx_id = rxq->rx_tail;
2073         uint16_t nb_rx = 0;
2074         uint16_t nb_hold = rxq->nb_rx_hold;
2075         uint16_t prev_id = rxq->rx_tail;
2076
2077         while (nb_rx < nb_pkts) {
2078                 bool eop;
2079                 struct ixgbe_rx_entry *rxe;
2080                 struct ixgbe_scattered_rx_entry *sc_entry;
2081                 struct ixgbe_scattered_rx_entry *next_sc_entry = NULL;
2082                 struct ixgbe_rx_entry *next_rxe = NULL;
2083                 struct rte_mbuf *first_seg;
2084                 struct rte_mbuf *rxm;
2085                 struct rte_mbuf *nmb = NULL;
2086                 union ixgbe_adv_rx_desc rxd;
2087                 uint16_t data_len;
2088                 uint16_t next_id;
2089                 volatile union ixgbe_adv_rx_desc *rxdp;
2090                 uint32_t staterr;
2091
2092 next_desc:
2093                 /*
2094                  * The code in this whole file uses the volatile pointer to
2095                  * ensure the read ordering of the status and the rest of the
2096                  * descriptor fields (on the compiler level only!!!). This is so
2097                  * UGLY - why not to just use the compiler barrier instead? DPDK
2098                  * even has the rte_compiler_barrier() for that.
2099                  *
2100                  * But most importantly this is just wrong because this doesn't
2101                  * ensure memory ordering in a general case at all. For
2102                  * instance, DPDK is supposed to work on Power CPUs where
2103                  * compiler barrier may just not be enough!
2104                  *
2105                  * I tried to write only this function properly to have a
2106                  * starting point (as a part of an LRO/RSC series) but the
2107                  * compiler cursed at me when I tried to cast away the
2108                  * "volatile" from rx_ring (yes, it's volatile too!!!). So, I'm
2109                  * keeping it the way it is for now.
2110                  *
2111                  * The code in this file is broken in so many other places and
2112                  * will just not work on a big endian CPU anyway therefore the
2113                  * lines below will have to be revisited together with the rest
2114                  * of the ixgbe PMD.
2115                  *
2116                  * TODO:
2117                  *    - Get rid of "volatile" and let the compiler do its job.
2118                  *    - Use the proper memory barrier (rte_rmb()) to ensure the
2119                  *      memory ordering below.
2120                  */
2121                 rxdp = &rx_ring[rx_id];
2122                 staterr = rte_le_to_cpu_32(rxdp->wb.upper.status_error);
2123
2124                 if (!(staterr & IXGBE_RXDADV_STAT_DD))
2125                         break;
2126
2127                 rxd = *rxdp;
2128
2129                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
2130                                   "staterr=0x%x data_len=%u",
2131                            rxq->port_id, rxq->queue_id, rx_id, staterr,
2132                            rte_le_to_cpu_16(rxd.wb.upper.length));
2133
2134                 if (!bulk_alloc) {
2135                         nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
2136                         if (nmb == NULL) {
2137                                 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed "
2138                                                   "port_id=%u queue_id=%u",
2139                                            rxq->port_id, rxq->queue_id);
2140
2141                                 rte_eth_devices[rxq->port_id].data->
2142                                                         rx_mbuf_alloc_failed++;
2143                                 break;
2144                         }
2145                 } else if (nb_hold > rxq->rx_free_thresh) {
2146                         uint16_t next_rdt = rxq->rx_free_trigger;
2147
2148                         if (!ixgbe_rx_alloc_bufs(rxq, false)) {
2149                                 rte_wmb();
2150                                 IXGBE_PCI_REG_WC_WRITE_RELAXED(
2151                                                         rxq->rdt_reg_addr,
2152                                                         next_rdt);
2153                                 nb_hold -= rxq->rx_free_thresh;
2154                         } else {
2155                                 PMD_RX_LOG(DEBUG, "RX bulk alloc failed "
2156                                                   "port_id=%u queue_id=%u",
2157                                            rxq->port_id, rxq->queue_id);
2158
2159                                 rte_eth_devices[rxq->port_id].data->
2160                                                         rx_mbuf_alloc_failed++;
2161                                 break;
2162                         }
2163                 }
2164
2165                 nb_hold++;
2166                 rxe = &sw_ring[rx_id];
2167                 eop = staterr & IXGBE_RXDADV_STAT_EOP;
2168
2169                 next_id = rx_id + 1;
2170                 if (next_id == rxq->nb_rx_desc)
2171                         next_id = 0;
2172
2173                 /* Prefetch next mbuf while processing current one. */
2174                 rte_ixgbe_prefetch(sw_ring[next_id].mbuf);
2175
2176                 /*
2177                  * When next RX descriptor is on a cache-line boundary,
2178                  * prefetch the next 4 RX descriptors and the next 4 pointers
2179                  * to mbufs.
2180                  */
2181                 if ((next_id & 0x3) == 0) {
2182                         rte_ixgbe_prefetch(&rx_ring[next_id]);
2183                         rte_ixgbe_prefetch(&sw_ring[next_id]);
2184                 }
2185
2186                 rxm = rxe->mbuf;
2187
2188                 if (!bulk_alloc) {
2189                         __le64 dma =
2190                           rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2191                         /*
2192                          * Update RX descriptor with the physical address of the
2193                          * new data buffer of the new allocated mbuf.
2194                          */
2195                         rxe->mbuf = nmb;
2196
2197                         rxm->data_off = RTE_PKTMBUF_HEADROOM;
2198                         rxdp->read.hdr_addr = 0;
2199                         rxdp->read.pkt_addr = dma;
2200                 } else
2201                         rxe->mbuf = NULL;
2202
2203                 /*
2204                  * Set data length & data buffer address of mbuf.
2205                  */
2206                 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
2207                 rxm->data_len = data_len;
2208
2209                 if (!eop) {
2210                         uint16_t nextp_id;
2211                         /*
2212                          * Get next descriptor index:
2213                          *  - For RSC it's in the NEXTP field.
2214                          *  - For a scattered packet - it's just a following
2215                          *    descriptor.
2216                          */
2217                         if (ixgbe_rsc_count(&rxd))
2218                                 nextp_id =
2219                                         (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
2220                                                        IXGBE_RXDADV_NEXTP_SHIFT;
2221                         else
2222                                 nextp_id = next_id;
2223
2224                         next_sc_entry = &sw_sc_ring[nextp_id];
2225                         next_rxe = &sw_ring[nextp_id];
2226                         rte_ixgbe_prefetch(next_rxe);
2227                 }
2228
2229                 sc_entry = &sw_sc_ring[rx_id];
2230                 first_seg = sc_entry->fbuf;
2231                 sc_entry->fbuf = NULL;
2232
2233                 /*
2234                  * If this is the first buffer of the received packet,
2235                  * set the pointer to the first mbuf of the packet and
2236                  * initialize its context.
2237                  * Otherwise, update the total length and the number of segments
2238                  * of the current scattered packet, and update the pointer to
2239                  * the last mbuf of the current packet.
2240                  */
2241                 if (first_seg == NULL) {
2242                         first_seg = rxm;
2243                         first_seg->pkt_len = data_len;
2244                         first_seg->nb_segs = 1;
2245                 } else {
2246                         first_seg->pkt_len += data_len;
2247                         first_seg->nb_segs++;
2248                 }
2249
2250                 prev_id = rx_id;
2251                 rx_id = next_id;
2252
2253                 /*
2254                  * If this is not the last buffer of the received packet, update
2255                  * the pointer to the first mbuf at the NEXTP entry in the
2256                  * sw_sc_ring and continue to parse the RX ring.
2257                  */
2258                 if (!eop && next_rxe) {
2259                         rxm->next = next_rxe->mbuf;
2260                         next_sc_entry->fbuf = first_seg;
2261                         goto next_desc;
2262                 }
2263
2264                 /* Initialize the first mbuf of the returned packet */
2265                 ixgbe_fill_cluster_head_buf(first_seg, &rxd, rxq, staterr);
2266
2267                 /*
2268                  * Deal with the case, when HW CRC srip is disabled.
2269                  * That can't happen when LRO is enabled, but still could
2270                  * happen for scattered RX mode.
2271                  */
2272                 first_seg->pkt_len -= rxq->crc_len;
2273                 if (unlikely(rxm->data_len <= rxq->crc_len)) {
2274                         struct rte_mbuf *lp;
2275
2276                         for (lp = first_seg; lp->next != rxm; lp = lp->next)
2277                                 ;
2278
2279                         first_seg->nb_segs--;
2280                         lp->data_len -= rxq->crc_len - rxm->data_len;
2281                         lp->next = NULL;
2282                         rte_pktmbuf_free_seg(rxm);
2283                 } else
2284                         rxm->data_len -= rxq->crc_len;
2285
2286                 /* Prefetch data of first segment, if configured to do so. */
2287                 rte_packet_prefetch((char *)first_seg->buf_addr +
2288                         first_seg->data_off);
2289
2290                 /*
2291                  * Store the mbuf address into the next entry of the array
2292                  * of returned packets.
2293                  */
2294                 rx_pkts[nb_rx++] = first_seg;
2295         }
2296
2297         /*
2298          * Record index of the next RX descriptor to probe.
2299          */
2300         rxq->rx_tail = rx_id;
2301
2302         /*
2303          * If the number of free RX descriptors is greater than the RX free
2304          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
2305          * register.
2306          * Update the RDT with the value of the last processed RX descriptor
2307          * minus 1, to guarantee that the RDT register is never equal to the
2308          * RDH register, which creates a "full" ring situtation from the
2309          * hardware point of view...
2310          */
2311         if (!bulk_alloc && nb_hold > rxq->rx_free_thresh) {
2312                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
2313                            "nb_hold=%u nb_rx=%u",
2314                            rxq->port_id, rxq->queue_id, rx_id, nb_hold, nb_rx);
2315
2316                 rte_wmb();
2317                 IXGBE_PCI_REG_WC_WRITE_RELAXED(rxq->rdt_reg_addr, prev_id);
2318                 nb_hold = 0;
2319         }
2320
2321         rxq->nb_rx_hold = nb_hold;
2322         return nb_rx;
2323 }
2324
2325 uint16_t
2326 ixgbe_recv_pkts_lro_single_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
2327                                  uint16_t nb_pkts)
2328 {
2329         return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, false);
2330 }
2331
2332 uint16_t
2333 ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
2334                                uint16_t nb_pkts)
2335 {
2336         return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, true);
2337 }
2338
2339 /*********************************************************************
2340  *
2341  *  Queue management functions
2342  *
2343  **********************************************************************/
2344
2345 static void __rte_cold
2346 ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)
2347 {
2348         unsigned i;
2349
2350         if (txq->sw_ring != NULL) {
2351                 for (i = 0; i < txq->nb_tx_desc; i++) {
2352                         if (txq->sw_ring[i].mbuf != NULL) {
2353                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2354                                 txq->sw_ring[i].mbuf = NULL;
2355                         }
2356                 }
2357         }
2358 }
2359
2360 static int
2361 ixgbe_tx_done_cleanup_full(struct ixgbe_tx_queue *txq, uint32_t free_cnt)
2362 {
2363         struct ixgbe_tx_entry *swr_ring = txq->sw_ring;
2364         uint16_t i, tx_last, tx_id;
2365         uint16_t nb_tx_free_last;
2366         uint16_t nb_tx_to_clean;
2367         uint32_t pkt_cnt;
2368
2369         /* Start free mbuf from the next of tx_tail */
2370         tx_last = txq->tx_tail;
2371         tx_id  = swr_ring[tx_last].next_id;
2372
2373         if (txq->nb_tx_free == 0 && ixgbe_xmit_cleanup(txq))
2374                 return 0;
2375
2376         nb_tx_to_clean = txq->nb_tx_free;
2377         nb_tx_free_last = txq->nb_tx_free;
2378         if (!free_cnt)
2379                 free_cnt = txq->nb_tx_desc;
2380
2381         /* Loop through swr_ring to count the amount of
2382          * freeable mubfs and packets.
2383          */
2384         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2385                 for (i = 0; i < nb_tx_to_clean &&
2386                         pkt_cnt < free_cnt &&
2387                         tx_id != tx_last; i++) {
2388                         if (swr_ring[tx_id].mbuf != NULL) {
2389                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2390                                 swr_ring[tx_id].mbuf = NULL;
2391
2392                                 /*
2393                                  * last segment in the packet,
2394                                  * increment packet count
2395                                  */
2396                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2397                         }
2398
2399                         tx_id = swr_ring[tx_id].next_id;
2400                 }
2401
2402                 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2403                         txq->nb_tx_free || tx_id == tx_last)
2404                         break;
2405
2406                 if (pkt_cnt < free_cnt) {
2407                         if (ixgbe_xmit_cleanup(txq))
2408                                 break;
2409
2410                         nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2411                         nb_tx_free_last = txq->nb_tx_free;
2412                 }
2413         }
2414
2415         return (int)pkt_cnt;
2416 }
2417
2418 static int
2419 ixgbe_tx_done_cleanup_simple(struct ixgbe_tx_queue *txq,
2420                         uint32_t free_cnt)
2421 {
2422         int i, n, cnt;
2423
2424         if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2425                 free_cnt = txq->nb_tx_desc;
2426
2427         cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2428
2429         for (i = 0; i < cnt; i += n) {
2430                 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2431                         break;
2432
2433                 n = ixgbe_tx_free_bufs(txq);
2434
2435                 if (n == 0)
2436                         break;
2437         }
2438
2439         return i;
2440 }
2441
2442 static int
2443 ixgbe_tx_done_cleanup_vec(struct ixgbe_tx_queue *txq __rte_unused,
2444                         uint32_t free_cnt __rte_unused)
2445 {
2446         return -ENOTSUP;
2447 }
2448
2449 int
2450 ixgbe_dev_tx_done_cleanup(void *tx_queue, uint32_t free_cnt)
2451 {
2452         struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
2453         if (txq->offloads == 0 &&
2454 #ifdef RTE_LIB_SECURITY
2455                         !(txq->using_ipsec) &&
2456 #endif
2457                         txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST) {
2458                 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
2459                                 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128 &&
2460                                 (rte_eal_process_type() != RTE_PROC_PRIMARY ||
2461                                         txq->sw_ring_v != NULL)) {
2462                         return ixgbe_tx_done_cleanup_vec(txq, free_cnt);
2463                 } else {
2464                         return ixgbe_tx_done_cleanup_simple(txq, free_cnt);
2465                 }
2466         }
2467
2468         return ixgbe_tx_done_cleanup_full(txq, free_cnt);
2469 }
2470
2471 static void __rte_cold
2472 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
2473 {
2474         if (txq != NULL &&
2475             txq->sw_ring != NULL)
2476                 rte_free(txq->sw_ring);
2477 }
2478
2479 static void __rte_cold
2480 ixgbe_tx_queue_release(struct ixgbe_tx_queue *txq)
2481 {
2482         if (txq != NULL && txq->ops != NULL) {
2483                 txq->ops->release_mbufs(txq);
2484                 txq->ops->free_swring(txq);
2485                 rte_memzone_free(txq->mz);
2486                 rte_free(txq);
2487         }
2488 }
2489
2490 void __rte_cold
2491 ixgbe_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
2492 {
2493         ixgbe_tx_queue_release(dev->data->tx_queues[qid]);
2494 }
2495
2496 /* (Re)set dynamic ixgbe_tx_queue fields to defaults */
2497 static void __rte_cold
2498 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
2499 {
2500         static const union ixgbe_adv_tx_desc zeroed_desc = {{0}};
2501         struct ixgbe_tx_entry *txe = txq->sw_ring;
2502         uint16_t prev, i;
2503
2504         /* Zero out HW ring memory */
2505         for (i = 0; i < txq->nb_tx_desc; i++) {
2506                 txq->tx_ring[i] = zeroed_desc;
2507         }
2508
2509         /* Initialize SW ring entries */
2510         prev = (uint16_t) (txq->nb_tx_desc - 1);
2511         for (i = 0; i < txq->nb_tx_desc; i++) {
2512                 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
2513
2514                 txd->wb.status = rte_cpu_to_le_32(IXGBE_TXD_STAT_DD);
2515                 txe[i].mbuf = NULL;
2516                 txe[i].last_id = i;
2517                 txe[prev].next_id = i;
2518                 prev = i;
2519         }
2520
2521         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2522         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2523
2524         txq->tx_tail = 0;
2525         txq->nb_tx_used = 0;
2526         /*
2527          * Always allow 1 descriptor to be un-allocated to avoid
2528          * a H/W race condition
2529          */
2530         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2531         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2532         txq->ctx_curr = 0;
2533         memset((void *)&txq->ctx_cache, 0,
2534                 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
2535 }
2536
2537 static const struct ixgbe_txq_ops def_txq_ops = {
2538         .release_mbufs = ixgbe_tx_queue_release_mbufs,
2539         .free_swring = ixgbe_tx_free_swring,
2540         .reset = ixgbe_reset_tx_queue,
2541 };
2542
2543 /* Takes an ethdev and a queue and sets up the tx function to be used based on
2544  * the queue parameters. Used in tx_queue_setup by primary process and then
2545  * in dev_init by secondary process when attaching to an existing ethdev.
2546  */
2547 void __rte_cold
2548 ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)
2549 {
2550         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2551         if ((txq->offloads == 0) &&
2552 #ifdef RTE_LIB_SECURITY
2553                         !(txq->using_ipsec) &&
2554 #endif
2555                         (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
2556                 PMD_INIT_LOG(DEBUG, "Using simple tx code path");
2557                 dev->tx_pkt_prepare = NULL;
2558                 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
2559                                 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128 &&
2560                                 (rte_eal_process_type() != RTE_PROC_PRIMARY ||
2561                                         ixgbe_txq_vec_setup(txq) == 0)) {
2562                         PMD_INIT_LOG(DEBUG, "Vector tx enabled.");
2563                         dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
2564                 } else
2565                 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
2566         } else {
2567                 PMD_INIT_LOG(DEBUG, "Using full-featured tx code path");
2568                 PMD_INIT_LOG(DEBUG,
2569                                 " - offloads = 0x%" PRIx64,
2570                                 txq->offloads);
2571                 PMD_INIT_LOG(DEBUG,
2572                                 " - tx_rs_thresh = %lu " "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
2573                                 (unsigned long)txq->tx_rs_thresh,
2574                                 (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST);
2575                 dev->tx_pkt_burst = ixgbe_xmit_pkts;
2576                 dev->tx_pkt_prepare = ixgbe_prep_pkts;
2577         }
2578 }
2579
2580 uint64_t
2581 ixgbe_get_tx_queue_offloads(struct rte_eth_dev *dev)
2582 {
2583         RTE_SET_USED(dev);
2584
2585         return 0;
2586 }
2587
2588 uint64_t
2589 ixgbe_get_tx_port_offloads(struct rte_eth_dev *dev)
2590 {
2591         uint64_t tx_offload_capa;
2592         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2593
2594         tx_offload_capa =
2595                 DEV_TX_OFFLOAD_VLAN_INSERT |
2596                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2597                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2598                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2599                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2600                 DEV_TX_OFFLOAD_TCP_TSO     |
2601                 DEV_TX_OFFLOAD_MULTI_SEGS;
2602
2603         if (hw->mac.type == ixgbe_mac_82599EB ||
2604             hw->mac.type == ixgbe_mac_X540)
2605                 tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
2606
2607         if (hw->mac.type == ixgbe_mac_X550 ||
2608             hw->mac.type == ixgbe_mac_X550EM_x ||
2609             hw->mac.type == ixgbe_mac_X550EM_a)
2610                 tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2611
2612 #ifdef RTE_LIB_SECURITY
2613         if (dev->security_ctx)
2614                 tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
2615 #endif
2616         return tx_offload_capa;
2617 }
2618
2619 int __rte_cold
2620 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
2621                          uint16_t queue_idx,
2622                          uint16_t nb_desc,
2623                          unsigned int socket_id,
2624                          const struct rte_eth_txconf *tx_conf)
2625 {
2626         const struct rte_memzone *tz;
2627         struct ixgbe_tx_queue *txq;
2628         struct ixgbe_hw     *hw;
2629         uint16_t tx_rs_thresh, tx_free_thresh;
2630         uint64_t offloads;
2631
2632         PMD_INIT_FUNC_TRACE();
2633         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2634
2635         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2636
2637         /*
2638          * Validate number of transmit descriptors.
2639          * It must not exceed hardware maximum, and must be multiple
2640          * of IXGBE_ALIGN.
2641          */
2642         if (nb_desc % IXGBE_TXD_ALIGN != 0 ||
2643                         (nb_desc > IXGBE_MAX_RING_DESC) ||
2644                         (nb_desc < IXGBE_MIN_RING_DESC)) {
2645                 return -EINVAL;
2646         }
2647
2648         /*
2649          * The following two parameters control the setting of the RS bit on
2650          * transmit descriptors.
2651          * TX descriptors will have their RS bit set after txq->tx_rs_thresh
2652          * descriptors have been used.
2653          * The TX descriptor ring will be cleaned after txq->tx_free_thresh
2654          * descriptors are used or if the number of descriptors required
2655          * to transmit a packet is greater than the number of free TX
2656          * descriptors.
2657          * The following constraints must be satisfied:
2658          *  tx_rs_thresh must be greater than 0.
2659          *  tx_rs_thresh must be less than the size of the ring minus 2.
2660          *  tx_rs_thresh must be less than or equal to tx_free_thresh.
2661          *  tx_rs_thresh must be a divisor of the ring size.
2662          *  tx_free_thresh must be greater than 0.
2663          *  tx_free_thresh must be less than the size of the ring minus 3.
2664          *  tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
2665          * One descriptor in the TX ring is used as a sentinel to avoid a
2666          * H/W race condition, hence the maximum threshold constraints.
2667          * When set to zero use default values.
2668          */
2669         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2670                         tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2671         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
2672         tx_rs_thresh = (DEFAULT_TX_RS_THRESH + tx_free_thresh > nb_desc) ?
2673                         nb_desc - tx_free_thresh : DEFAULT_TX_RS_THRESH;
2674         if (tx_conf->tx_rs_thresh > 0)
2675                 tx_rs_thresh = tx_conf->tx_rs_thresh;
2676         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
2677                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
2678                              "exceed nb_desc. (tx_rs_thresh=%u "
2679                              "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
2680                              (unsigned int)tx_rs_thresh,
2681                              (unsigned int)tx_free_thresh,
2682                              (unsigned int)nb_desc,
2683                              (int)dev->data->port_id,
2684                              (int)queue_idx);
2685                 return -(EINVAL);
2686         }
2687         if (tx_rs_thresh >= (nb_desc - 2)) {
2688                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
2689                         "of TX descriptors minus 2. (tx_rs_thresh=%u "
2690                         "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2691                         (int)dev->data->port_id, (int)queue_idx);
2692                 return -(EINVAL);
2693         }
2694         if (tx_rs_thresh > DEFAULT_TX_RS_THRESH) {
2695                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less or equal than %u. "
2696                         "(tx_rs_thresh=%u port=%d queue=%d)",
2697                         DEFAULT_TX_RS_THRESH, (unsigned int)tx_rs_thresh,
2698                         (int)dev->data->port_id, (int)queue_idx);
2699                 return -(EINVAL);
2700         }
2701         if (tx_free_thresh >= (nb_desc - 3)) {
2702                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2703                              "tx_free_thresh must be less than the number of "
2704                              "TX descriptors minus 3. (tx_free_thresh=%u "
2705                              "port=%d queue=%d)",
2706                              (unsigned int)tx_free_thresh,
2707                              (int)dev->data->port_id, (int)queue_idx);
2708                 return -(EINVAL);
2709         }
2710         if (tx_rs_thresh > tx_free_thresh) {
2711                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
2712                              "tx_free_thresh. (tx_free_thresh=%u "
2713                              "tx_rs_thresh=%u port=%d queue=%d)",
2714                              (unsigned int)tx_free_thresh,
2715                              (unsigned int)tx_rs_thresh,
2716                              (int)dev->data->port_id,
2717                              (int)queue_idx);
2718                 return -(EINVAL);
2719         }
2720         if ((nb_desc % tx_rs_thresh) != 0) {
2721                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2722                              "number of TX descriptors. (tx_rs_thresh=%u "
2723                              "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2724                              (int)dev->data->port_id, (int)queue_idx);
2725                 return -(EINVAL);
2726         }
2727
2728         /*
2729          * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
2730          * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
2731          * by the NIC and all descriptors are written back after the NIC
2732          * accumulates WTHRESH descriptors.
2733          */
2734         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2735                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2736                              "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
2737                              "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2738                              (int)dev->data->port_id, (int)queue_idx);
2739                 return -(EINVAL);
2740         }
2741
2742         /* Free memory prior to re-allocation if needed... */
2743         if (dev->data->tx_queues[queue_idx] != NULL) {
2744                 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
2745                 dev->data->tx_queues[queue_idx] = NULL;
2746         }
2747
2748         /* First allocate the tx queue data structure */
2749         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct ixgbe_tx_queue),
2750                                  RTE_CACHE_LINE_SIZE, socket_id);
2751         if (txq == NULL)
2752                 return -ENOMEM;
2753
2754         /*
2755          * Allocate TX ring hardware descriptors. A memzone large enough to
2756          * handle the maximum ring size is allocated in order to allow for
2757          * resizing in later calls to the queue setup function.
2758          */
2759         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2760                         sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
2761                         IXGBE_ALIGN, socket_id);
2762         if (tz == NULL) {
2763                 ixgbe_tx_queue_release(txq);
2764                 return -ENOMEM;
2765         }
2766
2767         txq->mz = tz;
2768         txq->nb_tx_desc = nb_desc;
2769         txq->tx_rs_thresh = tx_rs_thresh;
2770         txq->tx_free_thresh = tx_free_thresh;
2771         txq->pthresh = tx_conf->tx_thresh.pthresh;
2772         txq->hthresh = tx_conf->tx_thresh.hthresh;
2773         txq->wthresh = tx_conf->tx_thresh.wthresh;
2774         txq->queue_id = queue_idx;
2775         txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2776                 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2777         txq->port_id = dev->data->port_id;
2778         txq->offloads = offloads;
2779         txq->ops = &def_txq_ops;
2780         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2781 #ifdef RTE_LIB_SECURITY
2782         txq->using_ipsec = !!(dev->data->dev_conf.txmode.offloads &
2783                         DEV_TX_OFFLOAD_SECURITY);
2784 #endif
2785
2786         /*
2787          * Modification to set VFTDT for virtual function if vf is detected
2788          */
2789         if (hw->mac.type == ixgbe_mac_82599_vf ||
2790             hw->mac.type == ixgbe_mac_X540_vf ||
2791             hw->mac.type == ixgbe_mac_X550_vf ||
2792             hw->mac.type == ixgbe_mac_X550EM_x_vf ||
2793             hw->mac.type == ixgbe_mac_X550EM_a_vf)
2794                 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
2795         else
2796                 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
2797
2798         txq->tx_ring_phys_addr = tz->iova;
2799         txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
2800
2801         /* Allocate software ring */
2802         txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
2803                                 sizeof(struct ixgbe_tx_entry) * nb_desc,
2804                                 RTE_CACHE_LINE_SIZE, socket_id);
2805         if (txq->sw_ring == NULL) {
2806                 ixgbe_tx_queue_release(txq);
2807                 return -ENOMEM;
2808         }
2809         PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2810                      txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
2811
2812         /* set up vector or scalar TX function as appropriate */
2813         ixgbe_set_tx_function(dev, txq);
2814
2815         txq->ops->reset(txq);
2816
2817         dev->data->tx_queues[queue_idx] = txq;
2818
2819
2820         return 0;
2821 }
2822
2823 /**
2824  * ixgbe_free_sc_cluster - free the not-yet-completed scattered cluster
2825  *
2826  * The "next" pointer of the last segment of (not-yet-completed) RSC clusters
2827  * in the sw_rsc_ring is not set to NULL but rather points to the next
2828  * mbuf of this RSC aggregation (that has not been completed yet and still
2829  * resides on the HW ring). So, instead of calling for rte_pktmbuf_free() we
2830  * will just free first "nb_segs" segments of the cluster explicitly by calling
2831  * an rte_pktmbuf_free_seg().
2832  *
2833  * @m scattered cluster head
2834  */
2835 static void __rte_cold
2836 ixgbe_free_sc_cluster(struct rte_mbuf *m)
2837 {
2838         uint16_t i, nb_segs = m->nb_segs;
2839         struct rte_mbuf *next_seg;
2840
2841         for (i = 0; i < nb_segs; i++) {
2842                 next_seg = m->next;
2843                 rte_pktmbuf_free_seg(m);
2844                 m = next_seg;
2845         }
2846 }
2847
2848 static void __rte_cold
2849 ixgbe_rx_queue_release_mbufs(struct ixgbe_rx_queue *rxq)
2850 {
2851         unsigned i;
2852
2853         /* SSE Vector driver has a different way of releasing mbufs. */
2854         if (rxq->rx_using_sse) {
2855                 ixgbe_rx_queue_release_mbufs_vec(rxq);
2856                 return;
2857         }
2858
2859         if (rxq->sw_ring != NULL) {
2860                 for (i = 0; i < rxq->nb_rx_desc; i++) {
2861                         if (rxq->sw_ring[i].mbuf != NULL) {
2862                                 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2863                                 rxq->sw_ring[i].mbuf = NULL;
2864                         }
2865                 }
2866                 if (rxq->rx_nb_avail) {
2867                         for (i = 0; i < rxq->rx_nb_avail; ++i) {
2868                                 struct rte_mbuf *mb;
2869
2870                                 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2871                                 rte_pktmbuf_free_seg(mb);
2872                         }
2873                         rxq->rx_nb_avail = 0;
2874                 }
2875         }
2876
2877         if (rxq->sw_sc_ring)
2878                 for (i = 0; i < rxq->nb_rx_desc; i++)
2879                         if (rxq->sw_sc_ring[i].fbuf) {
2880                                 ixgbe_free_sc_cluster(rxq->sw_sc_ring[i].fbuf);
2881                                 rxq->sw_sc_ring[i].fbuf = NULL;
2882                         }
2883 }
2884
2885 static void __rte_cold
2886 ixgbe_rx_queue_release(struct ixgbe_rx_queue *rxq)
2887 {
2888         if (rxq != NULL) {
2889                 ixgbe_rx_queue_release_mbufs(rxq);
2890                 rte_free(rxq->sw_ring);
2891                 rte_free(rxq->sw_sc_ring);
2892                 rte_memzone_free(rxq->mz);
2893                 rte_free(rxq);
2894         }
2895 }
2896
2897 void __rte_cold
2898 ixgbe_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
2899 {
2900         ixgbe_rx_queue_release(dev->data->rx_queues[qid]);
2901 }
2902
2903 /*
2904  * Check if Rx Burst Bulk Alloc function can be used.
2905  * Return
2906  *        0: the preconditions are satisfied and the bulk allocation function
2907  *           can be used.
2908  *  -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2909  *           function must be used.
2910  */
2911 static inline int __rte_cold
2912 check_rx_burst_bulk_alloc_preconditions(struct ixgbe_rx_queue *rxq)
2913 {
2914         int ret = 0;
2915
2916         /*
2917          * Make sure the following pre-conditions are satisfied:
2918          *   rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2919          *   rxq->rx_free_thresh < rxq->nb_rx_desc
2920          *   (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2921          * Scattered packets are not supported.  This should be checked
2922          * outside of this function.
2923          */
2924         if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
2925                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2926                              "rxq->rx_free_thresh=%d, "
2927                              "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2928                              rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
2929                 ret = -EINVAL;
2930         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
2931                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2932                              "rxq->rx_free_thresh=%d, "
2933                              "rxq->nb_rx_desc=%d",
2934                              rxq->rx_free_thresh, rxq->nb_rx_desc);
2935                 ret = -EINVAL;
2936         } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
2937                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2938                              "rxq->nb_rx_desc=%d, "
2939                              "rxq->rx_free_thresh=%d",
2940                              rxq->nb_rx_desc, rxq->rx_free_thresh);
2941                 ret = -EINVAL;
2942         }
2943
2944         return ret;
2945 }
2946
2947 /* Reset dynamic ixgbe_rx_queue fields back to defaults */
2948 static void __rte_cold
2949 ixgbe_reset_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_rx_queue *rxq)
2950 {
2951         static const union ixgbe_adv_rx_desc zeroed_desc = {{0}};
2952         unsigned i;
2953         uint16_t len = rxq->nb_rx_desc;
2954
2955         /*
2956          * By default, the Rx queue setup function allocates enough memory for
2957          * IXGBE_MAX_RING_DESC.  The Rx Burst bulk allocation function requires
2958          * extra memory at the end of the descriptor ring to be zero'd out.
2959          */
2960         if (adapter->rx_bulk_alloc_allowed)
2961                 /* zero out extra memory */
2962                 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2963
2964         /*
2965          * Zero out HW ring memory. Zero out extra memory at the end of
2966          * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2967          * reads extra memory as zeros.
2968          */
2969         for (i = 0; i < len; i++) {
2970                 rxq->rx_ring[i] = zeroed_desc;
2971         }
2972
2973         /*
2974          * initialize extra software ring entries. Space for these extra
2975          * entries is always allocated
2976          */
2977         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2978         for (i = rxq->nb_rx_desc; i < len; ++i) {
2979                 rxq->sw_ring[i].mbuf = &rxq->fake_mbuf;
2980         }
2981
2982         rxq->rx_nb_avail = 0;
2983         rxq->rx_next_avail = 0;
2984         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2985         rxq->rx_tail = 0;
2986         rxq->nb_rx_hold = 0;
2987
2988         if (rxq->pkt_first_seg != NULL)
2989                 rte_pktmbuf_free(rxq->pkt_first_seg);
2990
2991         rxq->pkt_first_seg = NULL;
2992         rxq->pkt_last_seg = NULL;
2993
2994 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2995         rxq->rxrearm_start = 0;
2996         rxq->rxrearm_nb = 0;
2997 #endif
2998 }
2999
3000 static int
3001 ixgbe_is_vf(struct rte_eth_dev *dev)
3002 {
3003         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3004
3005         switch (hw->mac.type) {
3006         case ixgbe_mac_82599_vf:
3007         case ixgbe_mac_X540_vf:
3008         case ixgbe_mac_X550_vf:
3009         case ixgbe_mac_X550EM_x_vf:
3010         case ixgbe_mac_X550EM_a_vf:
3011                 return 1;
3012         default:
3013                 return 0;
3014         }
3015 }
3016
3017 uint64_t
3018 ixgbe_get_rx_queue_offloads(struct rte_eth_dev *dev)
3019 {
3020         uint64_t offloads = 0;
3021         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3022
3023         if (hw->mac.type != ixgbe_mac_82598EB)
3024                 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
3025
3026         return offloads;
3027 }
3028
3029 uint64_t
3030 ixgbe_get_rx_port_offloads(struct rte_eth_dev *dev)
3031 {
3032         uint64_t offloads;
3033         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3034
3035         offloads = DEV_RX_OFFLOAD_IPV4_CKSUM  |
3036                    DEV_RX_OFFLOAD_UDP_CKSUM   |
3037                    DEV_RX_OFFLOAD_TCP_CKSUM   |
3038                    DEV_RX_OFFLOAD_KEEP_CRC    |
3039                    DEV_RX_OFFLOAD_JUMBO_FRAME |
3040                    DEV_RX_OFFLOAD_VLAN_FILTER |
3041                    DEV_RX_OFFLOAD_SCATTER |
3042                    DEV_RX_OFFLOAD_RSS_HASH;
3043
3044         if (hw->mac.type == ixgbe_mac_82598EB)
3045                 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
3046
3047         if (ixgbe_is_vf(dev) == 0)
3048                 offloads |= DEV_RX_OFFLOAD_VLAN_EXTEND;
3049
3050         /*
3051          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3052          * mode.
3053          */
3054         if ((hw->mac.type == ixgbe_mac_82599EB ||
3055              hw->mac.type == ixgbe_mac_X540 ||
3056              hw->mac.type == ixgbe_mac_X550) &&
3057             !RTE_ETH_DEV_SRIOV(dev).active)
3058                 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
3059
3060         if (hw->mac.type == ixgbe_mac_82599EB ||
3061             hw->mac.type == ixgbe_mac_X540)
3062                 offloads |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3063
3064         if (hw->mac.type == ixgbe_mac_X550 ||
3065             hw->mac.type == ixgbe_mac_X550EM_x ||
3066             hw->mac.type == ixgbe_mac_X550EM_a)
3067                 offloads |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3068
3069 #ifdef RTE_LIB_SECURITY
3070         if (dev->security_ctx)
3071                 offloads |= DEV_RX_OFFLOAD_SECURITY;
3072 #endif
3073
3074         return offloads;
3075 }
3076
3077 int __rte_cold
3078 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
3079                          uint16_t queue_idx,
3080                          uint16_t nb_desc,
3081                          unsigned int socket_id,
3082                          const struct rte_eth_rxconf *rx_conf,
3083                          struct rte_mempool *mp)
3084 {
3085         const struct rte_memzone *rz;
3086         struct ixgbe_rx_queue *rxq;
3087         struct ixgbe_hw     *hw;
3088         uint16_t len;
3089         struct ixgbe_adapter *adapter = dev->data->dev_private;
3090         uint64_t offloads;
3091
3092         PMD_INIT_FUNC_TRACE();
3093         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3094
3095         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
3096
3097         /*
3098          * Validate number of receive descriptors.
3099          * It must not exceed hardware maximum, and must be multiple
3100          * of IXGBE_ALIGN.
3101          */
3102         if (nb_desc % IXGBE_RXD_ALIGN != 0 ||
3103                         (nb_desc > IXGBE_MAX_RING_DESC) ||
3104                         (nb_desc < IXGBE_MIN_RING_DESC)) {
3105                 return -EINVAL;
3106         }
3107
3108         /* Free memory prior to re-allocation if needed... */
3109         if (dev->data->rx_queues[queue_idx] != NULL) {
3110                 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
3111                 dev->data->rx_queues[queue_idx] = NULL;
3112         }
3113
3114         /* First allocate the rx queue data structure */
3115         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct ixgbe_rx_queue),
3116                                  RTE_CACHE_LINE_SIZE, socket_id);
3117         if (rxq == NULL)
3118                 return -ENOMEM;
3119         rxq->mb_pool = mp;
3120         rxq->nb_rx_desc = nb_desc;
3121         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
3122         rxq->queue_id = queue_idx;
3123         rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
3124                 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
3125         rxq->port_id = dev->data->port_id;
3126         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
3127                 rxq->crc_len = RTE_ETHER_CRC_LEN;
3128         else
3129                 rxq->crc_len = 0;
3130         rxq->drop_en = rx_conf->rx_drop_en;
3131         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
3132         rxq->offloads = offloads;
3133
3134         /*
3135          * The packet type in RX descriptor is different for different NICs.
3136          * Some bits are used for x550 but reserved for other NICS.
3137          * So set different masks for different NICs.
3138          */
3139         if (hw->mac.type == ixgbe_mac_X550 ||
3140             hw->mac.type == ixgbe_mac_X550EM_x ||
3141             hw->mac.type == ixgbe_mac_X550EM_a ||
3142             hw->mac.type == ixgbe_mac_X550_vf ||
3143             hw->mac.type == ixgbe_mac_X550EM_x_vf ||
3144             hw->mac.type == ixgbe_mac_X550EM_a_vf)
3145                 rxq->pkt_type_mask = IXGBE_PACKET_TYPE_MASK_X550;
3146         else
3147                 rxq->pkt_type_mask = IXGBE_PACKET_TYPE_MASK_82599;
3148
3149         /*
3150          * 82599 errata, UDP frames with a 0 checksum can be marked as checksum
3151          * errors.
3152          */
3153         if (hw->mac.type == ixgbe_mac_82599EB)
3154                 rxq->rx_udp_csum_zero_err = 1;
3155
3156         /*
3157          * Allocate RX ring hardware descriptors. A memzone large enough to
3158          * handle the maximum ring size is allocated in order to allow for
3159          * resizing in later calls to the queue setup function.
3160          */
3161         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
3162                                       RX_RING_SZ, IXGBE_ALIGN, socket_id);
3163         if (rz == NULL) {
3164                 ixgbe_rx_queue_release(rxq);
3165                 return -ENOMEM;
3166         }
3167
3168         rxq->mz = rz;
3169         /*
3170          * Zero init all the descriptors in the ring.
3171          */
3172         memset(rz->addr, 0, RX_RING_SZ);
3173
3174         /*
3175          * Modified to setup VFRDT for Virtual Function
3176          */
3177         if (hw->mac.type == ixgbe_mac_82599_vf ||
3178             hw->mac.type == ixgbe_mac_X540_vf ||
3179             hw->mac.type == ixgbe_mac_X550_vf ||
3180             hw->mac.type == ixgbe_mac_X550EM_x_vf ||
3181             hw->mac.type == ixgbe_mac_X550EM_a_vf) {
3182                 rxq->rdt_reg_addr =
3183                         IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
3184                 rxq->rdh_reg_addr =
3185                         IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
3186         } else {
3187                 rxq->rdt_reg_addr =
3188                         IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
3189                 rxq->rdh_reg_addr =
3190                         IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
3191         }
3192
3193         rxq->rx_ring_phys_addr = rz->iova;
3194         rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
3195
3196         /*
3197          * Certain constraints must be met in order to use the bulk buffer
3198          * allocation Rx burst function. If any of Rx queues doesn't meet them
3199          * the feature should be disabled for the whole port.
3200          */
3201         if (check_rx_burst_bulk_alloc_preconditions(rxq)) {
3202                 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Rx Bulk Alloc "
3203                                     "preconditions - canceling the feature for "
3204                                     "the whole port[%d]",
3205                              rxq->queue_id, rxq->port_id);
3206                 adapter->rx_bulk_alloc_allowed = false;
3207         }
3208
3209         /*
3210          * Allocate software ring. Allow for space at the end of the
3211          * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
3212          * function does not access an invalid memory region.
3213          */
3214         len = nb_desc;
3215         if (adapter->rx_bulk_alloc_allowed)
3216                 len += RTE_PMD_IXGBE_RX_MAX_BURST;
3217
3218         rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
3219                                           sizeof(struct ixgbe_rx_entry) * len,
3220                                           RTE_CACHE_LINE_SIZE, socket_id);
3221         if (!rxq->sw_ring) {
3222                 ixgbe_rx_queue_release(rxq);
3223                 return -ENOMEM;
3224         }
3225
3226         /*
3227          * Always allocate even if it's not going to be needed in order to
3228          * simplify the code.
3229          *
3230          * This ring is used in LRO and Scattered Rx cases and Scattered Rx may
3231          * be requested in ixgbe_dev_rx_init(), which is called later from
3232          * dev_start() flow.
3233          */
3234         rxq->sw_sc_ring =
3235                 rte_zmalloc_socket("rxq->sw_sc_ring",
3236                                    sizeof(struct ixgbe_scattered_rx_entry) * len,
3237                                    RTE_CACHE_LINE_SIZE, socket_id);
3238         if (!rxq->sw_sc_ring) {
3239                 ixgbe_rx_queue_release(rxq);
3240                 return -ENOMEM;
3241         }
3242
3243         PMD_INIT_LOG(DEBUG, "sw_ring=%p sw_sc_ring=%p hw_ring=%p "
3244                             "dma_addr=0x%"PRIx64,
3245                      rxq->sw_ring, rxq->sw_sc_ring, rxq->rx_ring,
3246                      rxq->rx_ring_phys_addr);
3247
3248         if (!rte_is_power_of_2(nb_desc)) {
3249                 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
3250                                     "preconditions - canceling the feature for "
3251                                     "the whole port[%d]",
3252                              rxq->queue_id, rxq->port_id);
3253                 adapter->rx_vec_allowed = false;
3254         } else
3255                 ixgbe_rxq_vec_setup(rxq);
3256
3257         dev->data->rx_queues[queue_idx] = rxq;
3258
3259         ixgbe_reset_rx_queue(adapter, rxq);
3260
3261         return 0;
3262 }
3263
3264 uint32_t
3265 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3266 {
3267 #define IXGBE_RXQ_SCAN_INTERVAL 4
3268         volatile union ixgbe_adv_rx_desc *rxdp;
3269         struct ixgbe_rx_queue *rxq;
3270         uint32_t desc = 0;
3271
3272         rxq = dev->data->rx_queues[rx_queue_id];
3273         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
3274
3275         while ((desc < rxq->nb_rx_desc) &&
3276                 (rxdp->wb.upper.status_error &
3277                         rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))) {
3278                 desc += IXGBE_RXQ_SCAN_INTERVAL;
3279                 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
3280                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
3281                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
3282                                 desc - rxq->nb_rx_desc]);
3283         }
3284
3285         return desc;
3286 }
3287
3288 int
3289 ixgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
3290 {
3291         struct ixgbe_rx_queue *rxq = rx_queue;
3292         volatile uint32_t *status;
3293         uint32_t nb_hold, desc;
3294
3295         if (unlikely(offset >= rxq->nb_rx_desc))
3296                 return -EINVAL;
3297
3298 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3299         if (rxq->rx_using_sse)
3300                 nb_hold = rxq->rxrearm_nb;
3301         else
3302 #endif
3303                 nb_hold = rxq->nb_rx_hold;
3304         if (offset >= rxq->nb_rx_desc - nb_hold)
3305                 return RTE_ETH_RX_DESC_UNAVAIL;
3306
3307         desc = rxq->rx_tail + offset;
3308         if (desc >= rxq->nb_rx_desc)
3309                 desc -= rxq->nb_rx_desc;
3310
3311         status = &rxq->rx_ring[desc].wb.upper.status_error;
3312         if (*status & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))
3313                 return RTE_ETH_RX_DESC_DONE;
3314
3315         return RTE_ETH_RX_DESC_AVAIL;
3316 }
3317
3318 int
3319 ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
3320 {
3321         struct ixgbe_tx_queue *txq = tx_queue;
3322         volatile uint32_t *status;
3323         uint32_t desc;
3324
3325         if (unlikely(offset >= txq->nb_tx_desc))
3326                 return -EINVAL;
3327
3328         desc = txq->tx_tail + offset;
3329         /* go to next desc that has the RS bit */
3330         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
3331                 txq->tx_rs_thresh;
3332         if (desc >= txq->nb_tx_desc) {
3333                 desc -= txq->nb_tx_desc;
3334                 if (desc >= txq->nb_tx_desc)
3335                         desc -= txq->nb_tx_desc;
3336         }
3337
3338         status = &txq->tx_ring[desc].wb.status;
3339         if (*status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD))
3340                 return RTE_ETH_TX_DESC_DONE;
3341
3342         return RTE_ETH_TX_DESC_FULL;
3343 }
3344
3345 /*
3346  * Set up link loopback for X540/X550 mode Tx->Rx.
3347  */
3348 static inline void __rte_cold
3349 ixgbe_setup_loopback_link_x540_x550(struct ixgbe_hw *hw, bool enable)
3350 {
3351         uint32_t macc;
3352         PMD_INIT_FUNC_TRACE();
3353
3354         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
3355
3356         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
3357                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
3358         macc = IXGBE_READ_REG(hw, IXGBE_MACC);
3359
3360         if (enable) {
3361                 /* datasheet 15.2.1: disable AUTONEG (PHY Bit 7.0.C) */
3362                 autoneg_reg |= IXGBE_MII_AUTONEG_ENABLE;
3363                 /* datasheet 15.2.1: MACC.FLU = 1 (force link up) */
3364                 macc |= IXGBE_MACC_FLU;
3365         } else {
3366                 autoneg_reg &= ~IXGBE_MII_AUTONEG_ENABLE;
3367                 macc &= ~IXGBE_MACC_FLU;
3368         }
3369
3370         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
3371                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
3372
3373         IXGBE_WRITE_REG(hw, IXGBE_MACC, macc);
3374 }
3375
3376 void __rte_cold
3377 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
3378 {
3379         unsigned i;
3380         struct ixgbe_adapter *adapter = dev->data->dev_private;
3381         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3382
3383         PMD_INIT_FUNC_TRACE();
3384
3385         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3386                 struct ixgbe_tx_queue *txq = dev->data->tx_queues[i];
3387
3388                 if (txq != NULL) {
3389                         txq->ops->release_mbufs(txq);
3390                         txq->ops->reset(txq);
3391                 }
3392         }
3393
3394         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3395                 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
3396
3397                 if (rxq != NULL) {
3398                         ixgbe_rx_queue_release_mbufs(rxq);
3399                         ixgbe_reset_rx_queue(adapter, rxq);
3400                 }
3401         }
3402         /* If loopback mode was enabled, reconfigure the link accordingly */
3403         if (dev->data->dev_conf.lpbk_mode != 0) {
3404                 if (hw->mac.type == ixgbe_mac_X540 ||
3405                      hw->mac.type == ixgbe_mac_X550 ||
3406                      hw->mac.type == ixgbe_mac_X550EM_x ||
3407                      hw->mac.type == ixgbe_mac_X550EM_a)
3408                         ixgbe_setup_loopback_link_x540_x550(hw, false);
3409         }
3410 }
3411
3412 void
3413 ixgbe_dev_free_queues(struct rte_eth_dev *dev)
3414 {
3415         unsigned i;
3416
3417         PMD_INIT_FUNC_TRACE();
3418
3419         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3420                 ixgbe_dev_rx_queue_release(dev, i);
3421                 dev->data->rx_queues[i] = NULL;
3422         }
3423         dev->data->nb_rx_queues = 0;
3424
3425         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3426                 ixgbe_dev_tx_queue_release(dev, i);
3427                 dev->data->tx_queues[i] = NULL;
3428         }
3429         dev->data->nb_tx_queues = 0;
3430 }
3431
3432 /*********************************************************************
3433  *
3434  *  Device RX/TX init functions
3435  *
3436  **********************************************************************/
3437
3438 /**
3439  * Receive Side Scaling (RSS)
3440  * See section 7.1.2.8 in the following document:
3441  *     "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
3442  *
3443  * Principles:
3444  * The source and destination IP addresses of the IP header and the source
3445  * and destination ports of TCP/UDP headers, if any, of received packets are
3446  * hashed against a configurable random key to compute a 32-bit RSS hash result.
3447  * The seven (7) LSBs of the 32-bit hash result are used as an index into a
3448  * 128-entry redirection table (RETA).  Each entry of the RETA provides a 3-bit
3449  * RSS output index which is used as the RX queue index where to store the
3450  * received packets.
3451  * The following output is supplied in the RX write-back descriptor:
3452  *     - 32-bit result of the Microsoft RSS hash function,
3453  *     - 4-bit RSS type field.
3454  */
3455
3456 /*
3457  * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
3458  * Used as the default key.
3459  */
3460 static uint8_t rss_intel_key[40] = {
3461         0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
3462         0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
3463         0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
3464         0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
3465         0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
3466 };
3467
3468 static void
3469 ixgbe_rss_disable(struct rte_eth_dev *dev)
3470 {
3471         struct ixgbe_hw *hw;
3472         uint32_t mrqc;
3473         uint32_t mrqc_reg;
3474
3475         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3476         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3477         mrqc = IXGBE_READ_REG(hw, mrqc_reg);
3478         mrqc &= ~IXGBE_MRQC_RSSEN;
3479         IXGBE_WRITE_REG(hw, mrqc_reg, mrqc);
3480 }
3481
3482 static void
3483 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
3484 {
3485         uint8_t  *hash_key;
3486         uint32_t mrqc;
3487         uint32_t rss_key;
3488         uint64_t rss_hf;
3489         uint16_t i;
3490         uint32_t mrqc_reg;
3491         uint32_t rssrk_reg;
3492
3493         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3494         rssrk_reg = ixgbe_rssrk_reg_get(hw->mac.type, 0);
3495
3496         hash_key = rss_conf->rss_key;
3497         if (hash_key != NULL) {
3498                 /* Fill in RSS hash key */
3499                 for (i = 0; i < 10; i++) {
3500                         rss_key  = hash_key[(i * 4)];
3501                         rss_key |= hash_key[(i * 4) + 1] << 8;
3502                         rss_key |= hash_key[(i * 4) + 2] << 16;
3503                         rss_key |= hash_key[(i * 4) + 3] << 24;
3504                         IXGBE_WRITE_REG_ARRAY(hw, rssrk_reg, i, rss_key);
3505                 }
3506         }
3507
3508         /* Set configured hashing protocols in MRQC register */
3509         rss_hf = rss_conf->rss_hf;
3510         mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
3511         if (rss_hf & ETH_RSS_IPV4)
3512                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
3513         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
3514                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
3515         if (rss_hf & ETH_RSS_IPV6)
3516                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
3517         if (rss_hf & ETH_RSS_IPV6_EX)
3518                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
3519         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
3520                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3521         if (rss_hf & ETH_RSS_IPV6_TCP_EX)
3522                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
3523         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
3524                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3525         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
3526                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3527         if (rss_hf & ETH_RSS_IPV6_UDP_EX)
3528                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
3529         IXGBE_WRITE_REG(hw, mrqc_reg, mrqc);
3530 }
3531
3532 int
3533 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
3534                           struct rte_eth_rss_conf *rss_conf)
3535 {
3536         struct ixgbe_hw *hw;
3537         uint32_t mrqc;
3538         uint64_t rss_hf;
3539         uint32_t mrqc_reg;
3540
3541         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3542
3543         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3544                 PMD_DRV_LOG(ERR, "RSS hash update is not supported on this "
3545                         "NIC.");
3546                 return -ENOTSUP;
3547         }
3548         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3549
3550         /*
3551          * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
3552          *     "RSS enabling cannot be done dynamically while it must be
3553          *      preceded by a software reset"
3554          * Before changing anything, first check that the update RSS operation
3555          * does not attempt to disable RSS, if RSS was enabled at
3556          * initialization time, or does not attempt to enable RSS, if RSS was
3557          * disabled at initialization time.
3558          */
3559         rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
3560         mrqc = IXGBE_READ_REG(hw, mrqc_reg);
3561         if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
3562                 if (rss_hf != 0) /* Enable RSS */
3563                         return -(EINVAL);
3564                 return 0; /* Nothing to do */
3565         }
3566         /* RSS enabled */
3567         if (rss_hf == 0) /* Disable RSS */
3568                 return -(EINVAL);
3569         ixgbe_hw_rss_hash_set(hw, rss_conf);
3570         return 0;
3571 }
3572
3573 int
3574 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
3575                             struct rte_eth_rss_conf *rss_conf)
3576 {
3577         struct ixgbe_hw *hw;
3578         uint8_t *hash_key;
3579         uint32_t mrqc;
3580         uint32_t rss_key;
3581         uint64_t rss_hf;
3582         uint16_t i;
3583         uint32_t mrqc_reg;
3584         uint32_t rssrk_reg;
3585
3586         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3587         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3588         rssrk_reg = ixgbe_rssrk_reg_get(hw->mac.type, 0);
3589         hash_key = rss_conf->rss_key;
3590         if (hash_key != NULL) {
3591                 /* Return RSS hash key */
3592                 for (i = 0; i < 10; i++) {
3593                         rss_key = IXGBE_READ_REG_ARRAY(hw, rssrk_reg, i);
3594                         hash_key[(i * 4)] = rss_key & 0x000000FF;
3595                         hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
3596                         hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
3597                         hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
3598                 }
3599         }
3600
3601         /* Get RSS functions configured in MRQC register */
3602         mrqc = IXGBE_READ_REG(hw, mrqc_reg);
3603         if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
3604                 rss_conf->rss_hf = 0;
3605                 return 0;
3606         }
3607         rss_hf = 0;
3608         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
3609                 rss_hf |= ETH_RSS_IPV4;
3610         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
3611                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
3612         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
3613                 rss_hf |= ETH_RSS_IPV6;
3614         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
3615                 rss_hf |= ETH_RSS_IPV6_EX;
3616         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
3617                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
3618         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
3619                 rss_hf |= ETH_RSS_IPV6_TCP_EX;
3620         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
3621                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
3622         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
3623                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
3624         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
3625                 rss_hf |= ETH_RSS_IPV6_UDP_EX;
3626         rss_conf->rss_hf = rss_hf;
3627         return 0;
3628 }
3629
3630 static void
3631 ixgbe_rss_configure(struct rte_eth_dev *dev)
3632 {
3633         struct rte_eth_rss_conf rss_conf;
3634         struct ixgbe_adapter *adapter;
3635         struct ixgbe_hw *hw;
3636         uint32_t reta;
3637         uint16_t i;
3638         uint16_t j;
3639         uint16_t sp_reta_size;
3640         uint32_t reta_reg;
3641
3642         PMD_INIT_FUNC_TRACE();
3643         adapter = dev->data->dev_private;
3644         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3645
3646         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3647
3648         /*
3649          * Fill in redirection table
3650          * The byte-swap is needed because NIC registers are in
3651          * little-endian order.
3652          */
3653         if (adapter->rss_reta_updated == 0) {
3654                 reta = 0;
3655                 for (i = 0, j = 0; i < sp_reta_size; i++, j++) {
3656                         reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3657
3658                         if (j == dev->data->nb_rx_queues)
3659                                 j = 0;
3660                         reta = (reta << 8) | j;
3661                         if ((i & 3) == 3)
3662                                 IXGBE_WRITE_REG(hw, reta_reg,
3663                                                 rte_bswap32(reta));
3664                 }
3665         }
3666
3667         /*
3668          * Configure the RSS key and the RSS protocols used to compute
3669          * the RSS hash of input packets.
3670          */
3671         rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
3672         if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
3673                 ixgbe_rss_disable(dev);
3674                 return;
3675         }
3676         if (rss_conf.rss_key == NULL)
3677                 rss_conf.rss_key = rss_intel_key; /* Default hash key */
3678         ixgbe_hw_rss_hash_set(hw, &rss_conf);
3679 }
3680
3681 #define NUM_VFTA_REGISTERS 128
3682 #define NIC_RX_BUFFER_SIZE 0x200
3683 #define X550_RX_BUFFER_SIZE 0x180
3684
3685 static void
3686 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
3687 {
3688         struct rte_eth_vmdq_dcb_conf *cfg;
3689         struct ixgbe_hw *hw;
3690         enum rte_eth_nb_pools num_pools;
3691         uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
3692         uint16_t pbsize;
3693         uint8_t nb_tcs; /* number of traffic classes */
3694         int i;
3695
3696         PMD_INIT_FUNC_TRACE();
3697         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3698         cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3699         num_pools = cfg->nb_queue_pools;
3700         /* Check we have a valid number of pools */
3701         if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
3702                 ixgbe_rss_disable(dev);
3703                 return;
3704         }
3705         /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
3706         nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
3707
3708         /*
3709          * RXPBSIZE
3710          * split rx buffer up into sections, each for 1 traffic class
3711          */
3712         switch (hw->mac.type) {
3713         case ixgbe_mac_X550:
3714         case ixgbe_mac_X550EM_x:
3715         case ixgbe_mac_X550EM_a:
3716                 pbsize = (uint16_t)(X550_RX_BUFFER_SIZE / nb_tcs);
3717                 break;
3718         default:
3719                 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3720                 break;
3721         }
3722         for (i = 0; i < nb_tcs; i++) {
3723                 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
3724
3725                 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
3726                 /* clear 10 bits. */
3727                 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
3728                 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3729         }
3730         /* zero alloc all unused TCs */
3731         for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3732                 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
3733
3734                 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
3735                 /* clear 10 bits. */
3736                 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3737         }
3738
3739         /* MRQC: enable vmdq and dcb */
3740         mrqc = (num_pools == ETH_16_POOLS) ?
3741                 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN;
3742         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3743
3744         /* PFVTCTL: turn on virtualisation and set the default pool */
3745         vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3746         if (cfg->enable_default_pool) {
3747                 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3748         } else {
3749                 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3750         }
3751
3752         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3753
3754         /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
3755         queue_mapping = 0;
3756         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
3757                 /*
3758                  * mapping is done with 3 bits per priority,
3759                  * so shift by i*3 each time
3760                  */
3761                 queue_mapping |= ((cfg->dcb_tc[i] & 0x07) << (i * 3));
3762
3763         IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
3764
3765         /* RTRPCS: DCB related */
3766         IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
3767
3768         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3769         vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3770         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
3771         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3772
3773         /* VFTA - enable all vlan filters */
3774         for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3775                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3776         }
3777
3778         /* VFRE: pool enabling for receive - 16 or 32 */
3779         IXGBE_WRITE_REG(hw, IXGBE_VFRE(0),
3780                         num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3781
3782         /*
3783          * MPSAR - allow pools to read specific mac addresses
3784          * In this case, all pools should be able to read from mac addr 0
3785          */
3786         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
3787         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
3788
3789         /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3790         for (i = 0; i < cfg->nb_pool_maps; i++) {
3791                 /* set vlan id in VF register and set the valid bit */
3792                 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN |
3793                                 (cfg->pool_map[i].vlan_id & 0xFFF)));
3794                 /*
3795                  * Put the allowed pools in VFB reg. As we only have 16 or 32
3796                  * pools, we only need to use the first half of the register
3797                  * i.e. bits 0-31
3798                  */
3799                 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
3800         }
3801 }
3802
3803 /**
3804  * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
3805  * @dev: pointer to eth_dev structure
3806  * @dcb_config: pointer to ixgbe_dcb_config structure
3807  */
3808 static void
3809 ixgbe_dcb_tx_hw_config(struct rte_eth_dev *dev,
3810                        struct ixgbe_dcb_config *dcb_config)
3811 {
3812         uint32_t reg;
3813         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3814
3815         PMD_INIT_FUNC_TRACE();
3816         if (hw->mac.type != ixgbe_mac_82598EB) {
3817                 /* Disable the Tx desc arbiter so that MTQC can be changed */
3818                 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3819                 reg |= IXGBE_RTTDCS_ARBDIS;
3820                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3821
3822                 /* Enable DCB for Tx with 8 TCs */
3823                 if (dcb_config->num_tcs.pg_tcs == 8) {
3824                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3825                 } else {
3826                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3827                 }
3828                 if (dcb_config->vt_mode)
3829                         reg |= IXGBE_MTQC_VT_ENA;
3830                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3831
3832                 /* Enable the Tx desc arbiter */
3833                 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3834                 reg &= ~IXGBE_RTTDCS_ARBDIS;
3835                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3836
3837                 /* Enable Security TX Buffer IFG for DCB */
3838                 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3839                 reg |= IXGBE_SECTX_DCB;
3840                 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
3841         }
3842 }
3843
3844 /**
3845  * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
3846  * @dev: pointer to rte_eth_dev structure
3847  * @dcb_config: pointer to ixgbe_dcb_config structure
3848  */
3849 static void
3850 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
3851                         struct ixgbe_dcb_config *dcb_config)
3852 {
3853         struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3854                         &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3855         struct ixgbe_hw *hw =
3856                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3857
3858         PMD_INIT_FUNC_TRACE();
3859         if (hw->mac.type != ixgbe_mac_82598EB)
3860                 /*PF VF Transmit Enable*/
3861                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
3862                         vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3863
3864         /*Configure general DCB TX parameters*/
3865         ixgbe_dcb_tx_hw_config(dev, dcb_config);
3866 }
3867
3868 static void
3869 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
3870                         struct ixgbe_dcb_config *dcb_config)
3871 {
3872         struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
3873                         &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3874         struct ixgbe_dcb_tc_config *tc;
3875         uint8_t i, j;
3876
3877         /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3878         if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS) {
3879                 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3880                 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3881         } else {
3882                 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3883                 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3884         }
3885
3886         /* Initialize User Priority to Traffic Class mapping */
3887         for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3888                 tc = &dcb_config->tc_config[j];
3889                 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0;
3890         }
3891
3892         /* User Priority to Traffic Class mapping */
3893         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3894                 j = vmdq_rx_conf->dcb_tc[i];
3895                 tc = &dcb_config->tc_config[j];
3896                 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap |=
3897                                                 (uint8_t)(1 << i);
3898         }
3899 }
3900
3901 static void
3902 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
3903                         struct ixgbe_dcb_config *dcb_config)
3904 {
3905         struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3906                         &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3907         struct ixgbe_dcb_tc_config *tc;
3908         uint8_t i, j;
3909
3910         /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3911         if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS) {
3912                 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3913                 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3914         } else {
3915                 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3916                 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3917         }
3918
3919         /* Initialize User Priority to Traffic Class mapping */
3920         for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3921                 tc = &dcb_config->tc_config[j];
3922                 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0;
3923         }
3924
3925         /* User Priority to Traffic Class mapping */
3926         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3927                 j = vmdq_tx_conf->dcb_tc[i];
3928                 tc = &dcb_config->tc_config[j];
3929                 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap |=
3930                                                 (uint8_t)(1 << i);
3931         }
3932 }
3933
3934 static void
3935 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
3936                 struct ixgbe_dcb_config *dcb_config)
3937 {
3938         struct rte_eth_dcb_rx_conf *rx_conf =
3939                         &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
3940         struct ixgbe_dcb_tc_config *tc;
3941         uint8_t i, j;
3942
3943         dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
3944         dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
3945
3946         /* Initialize User Priority to Traffic Class mapping */
3947         for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3948                 tc = &dcb_config->tc_config[j];
3949                 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0;
3950         }
3951
3952         /* User Priority to Traffic Class mapping */
3953         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3954                 j = rx_conf->dcb_tc[i];
3955                 tc = &dcb_config->tc_config[j];
3956                 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap |=
3957                                                 (uint8_t)(1 << i);
3958         }
3959 }
3960
3961 static void
3962 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
3963                 struct ixgbe_dcb_config *dcb_config)
3964 {
3965         struct rte_eth_dcb_tx_conf *tx_conf =
3966                         &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
3967         struct ixgbe_dcb_tc_config *tc;
3968         uint8_t i, j;
3969
3970         dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
3971         dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
3972
3973         /* Initialize User Priority to Traffic Class mapping */
3974         for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3975                 tc = &dcb_config->tc_config[j];
3976                 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0;
3977         }
3978
3979         /* User Priority to Traffic Class mapping */
3980         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3981                 j = tx_conf->dcb_tc[i];
3982                 tc = &dcb_config->tc_config[j];
3983                 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap |=
3984                                                 (uint8_t)(1 << i);
3985         }
3986 }
3987
3988 /**
3989  * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
3990  * @dev: pointer to eth_dev structure
3991  * @dcb_config: pointer to ixgbe_dcb_config structure
3992  */
3993 static void
3994 ixgbe_dcb_rx_hw_config(struct rte_eth_dev *dev,
3995                        struct ixgbe_dcb_config *dcb_config)
3996 {
3997         uint32_t reg;
3998         uint32_t vlanctrl;
3999         uint8_t i;
4000         uint32_t q;
4001         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4002
4003         PMD_INIT_FUNC_TRACE();
4004         /*
4005          * Disable the arbiter before changing parameters
4006          * (always enable recycle mode; WSP)
4007          */
4008         reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
4009         IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
4010
4011         if (hw->mac.type != ixgbe_mac_82598EB) {
4012                 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
4013                 if (dcb_config->num_tcs.pg_tcs == 4) {
4014                         if (dcb_config->vt_mode)
4015                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
4016                                         IXGBE_MRQC_VMDQRT4TCEN;
4017                         else {
4018                                 /* no matter the mode is DCB or DCB_RSS, just
4019                                  * set the MRQE to RSSXTCEN. RSS is controlled
4020                                  * by RSS_FIELD
4021                                  */
4022                                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
4023                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
4024                                         IXGBE_MRQC_RTRSS4TCEN;
4025                         }
4026                 }
4027                 if (dcb_config->num_tcs.pg_tcs == 8) {
4028                         if (dcb_config->vt_mode)
4029                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
4030                                         IXGBE_MRQC_VMDQRT8TCEN;
4031                         else {
4032                                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
4033                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
4034                                         IXGBE_MRQC_RTRSS8TCEN;
4035                         }
4036                 }
4037
4038                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
4039
4040                 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
4041                         /* Disable drop for all queues in VMDQ mode*/
4042                         for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
4043                                 IXGBE_WRITE_REG(hw, IXGBE_QDE,
4044                                                 (IXGBE_QDE_WRITE |
4045                                                  (q << IXGBE_QDE_IDX_SHIFT)));
4046                 } else {
4047                         /* Enable drop for all queues in SRIOV mode */
4048                         for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
4049                                 IXGBE_WRITE_REG(hw, IXGBE_QDE,
4050                                                 (IXGBE_QDE_WRITE |
4051                                                  (q << IXGBE_QDE_IDX_SHIFT) |
4052                                                  IXGBE_QDE_ENABLE));
4053                 }
4054         }
4055
4056         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
4057         vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4058         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
4059         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
4060
4061         /* VFTA - enable all vlan filters */
4062         for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
4063                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
4064         }
4065
4066         /*
4067          * Configure Rx packet plane (recycle mode; WSP) and
4068          * enable arbiter
4069          */
4070         reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
4071         IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
4072 }
4073
4074 static void
4075 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
4076                         uint16_t *max, uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
4077 {
4078         switch (hw->mac.type) {
4079         case ixgbe_mac_82598EB:
4080                 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
4081                 break;
4082         case ixgbe_mac_82599EB:
4083         case ixgbe_mac_X540:
4084         case ixgbe_mac_X550:
4085         case ixgbe_mac_X550EM_x:
4086         case ixgbe_mac_X550EM_a:
4087                 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
4088                                                   tsa, map);
4089                 break;
4090         default:
4091                 break;
4092         }
4093 }
4094
4095 static void
4096 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
4097                             uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
4098 {
4099         switch (hw->mac.type) {
4100         case ixgbe_mac_82598EB:
4101                 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id, tsa);
4102                 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id, tsa);
4103                 break;
4104         case ixgbe_mac_82599EB:
4105         case ixgbe_mac_X540:
4106         case ixgbe_mac_X550:
4107         case ixgbe_mac_X550EM_x:
4108         case ixgbe_mac_X550EM_a:
4109                 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id, tsa);
4110                 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id, tsa, map);
4111                 break;
4112         default:
4113                 break;
4114         }
4115 }
4116
4117 #define DCB_RX_CONFIG  1
4118 #define DCB_TX_CONFIG  1
4119 #define DCB_TX_PB      1024
4120 /**
4121  * ixgbe_dcb_hw_configure - Enable DCB and configure
4122  * general DCB in VT mode and non-VT mode parameters
4123  * @dev: pointer to rte_eth_dev structure
4124  * @dcb_config: pointer to ixgbe_dcb_config structure
4125  */
4126 static int
4127 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
4128                         struct ixgbe_dcb_config *dcb_config)
4129 {
4130         int     ret = 0;
4131         uint8_t i, pfc_en, nb_tcs;
4132         uint16_t pbsize, rx_buffer_size;
4133         uint8_t config_dcb_rx = 0;
4134         uint8_t config_dcb_tx = 0;
4135         uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
4136         uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
4137         uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
4138         uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
4139         uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
4140         struct ixgbe_dcb_tc_config *tc;
4141         uint32_t max_frame = dev->data->mtu + RTE_ETHER_HDR_LEN +
4142                 RTE_ETHER_CRC_LEN;
4143         struct ixgbe_hw *hw =
4144                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4145         struct ixgbe_bw_conf *bw_conf =
4146                 IXGBE_DEV_PRIVATE_TO_BW_CONF(dev->data->dev_private);
4147
4148         switch (dev->data->dev_conf.rxmode.mq_mode) {
4149         case ETH_MQ_RX_VMDQ_DCB:
4150                 dcb_config->vt_mode = true;
4151                 if (hw->mac.type != ixgbe_mac_82598EB) {
4152                         config_dcb_rx = DCB_RX_CONFIG;
4153                         /*
4154                          *get dcb and VT rx configuration parameters
4155                          *from rte_eth_conf
4156                          */
4157                         ixgbe_vmdq_dcb_rx_config(dev, dcb_config);
4158                         /*Configure general VMDQ and DCB RX parameters*/
4159                         ixgbe_vmdq_dcb_configure(dev);
4160                 }
4161                 break;
4162         case ETH_MQ_RX_DCB:
4163         case ETH_MQ_RX_DCB_RSS:
4164                 dcb_config->vt_mode = false;
4165                 config_dcb_rx = DCB_RX_CONFIG;
4166                 /* Get dcb TX configuration parameters from rte_eth_conf */
4167                 ixgbe_dcb_rx_config(dev, dcb_config);
4168                 /*Configure general DCB RX parameters*/
4169                 ixgbe_dcb_rx_hw_config(dev, dcb_config);
4170                 break;
4171         default:
4172                 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
4173                 break;
4174         }
4175         switch (dev->data->dev_conf.txmode.mq_mode) {
4176         case ETH_MQ_TX_VMDQ_DCB:
4177                 dcb_config->vt_mode = true;
4178                 config_dcb_tx = DCB_TX_CONFIG;
4179                 /* get DCB and VT TX configuration parameters
4180                  * from rte_eth_conf
4181                  */
4182                 ixgbe_dcb_vt_tx_config(dev, dcb_config);
4183                 /*Configure general VMDQ and DCB TX parameters*/
4184                 ixgbe_vmdq_dcb_hw_tx_config(dev, dcb_config);
4185                 break;
4186
4187         case ETH_MQ_TX_DCB:
4188                 dcb_config->vt_mode = false;
4189                 config_dcb_tx = DCB_TX_CONFIG;
4190                 /*get DCB TX configuration parameters from rte_eth_conf*/
4191                 ixgbe_dcb_tx_config(dev, dcb_config);
4192                 /*Configure general DCB TX parameters*/
4193                 ixgbe_dcb_tx_hw_config(dev, dcb_config);
4194                 break;
4195         default:
4196                 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
4197                 break;
4198         }
4199
4200         nb_tcs = dcb_config->num_tcs.pfc_tcs;
4201         /* Unpack map */
4202         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4203         if (nb_tcs == ETH_4_TCS) {
4204                 /* Avoid un-configured priority mapping to TC0 */
4205                 uint8_t j = 4;
4206                 uint8_t mask = 0xFF;
4207
4208                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
4209                         mask = (uint8_t)(mask & (~(1 << map[i])));
4210                 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
4211                         if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
4212                                 map[j++] = i;
4213                         mask >>= 1;
4214                 }
4215                 /* Re-configure 4 TCs BW */
4216                 for (i = 0; i < nb_tcs; i++) {
4217                         tc = &dcb_config->tc_config[i];
4218                         if (bw_conf->tc_num != nb_tcs)
4219                                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
4220                                         (uint8_t)(100 / nb_tcs);
4221                         tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
4222                                                 (uint8_t)(100 / nb_tcs);
4223                 }
4224                 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4225                         tc = &dcb_config->tc_config[i];
4226                         tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
4227                         tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
4228                 }
4229         } else {
4230                 /* Re-configure 8 TCs BW */
4231                 for (i = 0; i < nb_tcs; i++) {
4232                         tc = &dcb_config->tc_config[i];
4233                         if (bw_conf->tc_num != nb_tcs)
4234                                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
4235                                         (uint8_t)(100 / nb_tcs + (i & 1));
4236                         tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
4237                                 (uint8_t)(100 / nb_tcs + (i & 1));
4238                 }
4239         }
4240
4241         switch (hw->mac.type) {
4242         case ixgbe_mac_X550:
4243         case ixgbe_mac_X550EM_x:
4244         case ixgbe_mac_X550EM_a:
4245                 rx_buffer_size = X550_RX_BUFFER_SIZE;
4246                 break;
4247         default:
4248                 rx_buffer_size = NIC_RX_BUFFER_SIZE;
4249                 break;
4250         }
4251
4252         if (config_dcb_rx) {
4253                 /* Set RX buffer size */
4254                 pbsize = (uint16_t)(rx_buffer_size / nb_tcs);
4255                 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
4256
4257                 for (i = 0; i < nb_tcs; i++) {
4258                         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
4259                 }
4260                 /* zero alloc all unused TCs */
4261                 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
4262                         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4263                 }
4264         }
4265         if (config_dcb_tx) {
4266                 /* Only support an equally distributed
4267                  *  Tx packet buffer strategy.
4268                  */
4269                 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
4270                 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
4271
4272                 for (i = 0; i < nb_tcs; i++) {
4273                         IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4274                         IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4275                 }
4276                 /* Clear unused TCs, if any, to zero buffer size*/
4277                 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
4278                         IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4279                         IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4280                 }
4281         }
4282
4283         /*Calculates traffic class credits*/
4284         ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config, max_frame,
4285                                 IXGBE_DCB_TX_CONFIG);
4286         ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config, max_frame,
4287                                 IXGBE_DCB_RX_CONFIG);
4288
4289         if (config_dcb_rx) {
4290                 /* Unpack CEE standard containers */
4291                 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
4292                 ixgbe_dcb_unpack_max_cee(dcb_config, max);
4293                 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
4294                 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
4295                 /* Configure PG(ETS) RX */
4296                 ixgbe_dcb_hw_arbite_rx_config(hw, refill, max, bwgid, tsa, map);
4297         }
4298
4299         if (config_dcb_tx) {
4300                 /* Unpack CEE standard containers */
4301                 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
4302                 ixgbe_dcb_unpack_max_cee(dcb_config, max);
4303                 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
4304                 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
4305                 /* Configure PG(ETS) TX */
4306                 ixgbe_dcb_hw_arbite_tx_config(hw, refill, max, bwgid, tsa, map);
4307         }
4308
4309         /*Configure queue statistics registers*/
4310         ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
4311
4312         /* Check if the PFC is supported */
4313         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
4314                 pbsize = (uint16_t)(rx_buffer_size / nb_tcs);
4315                 for (i = 0; i < nb_tcs; i++) {
4316                         /*
4317                         * If the TC count is 8,and the default high_water is 48,
4318                         * the low_water is 16 as default.
4319                         */
4320                         hw->fc.high_water[i] = (pbsize * 3) / 4;
4321                         hw->fc.low_water[i] = pbsize / 4;
4322                         /* Enable pfc for this TC */
4323                         tc = &dcb_config->tc_config[i];
4324                         tc->pfc = ixgbe_dcb_pfc_enabled;
4325                 }
4326                 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
4327                 if (dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
4328                         pfc_en &= 0x0F;
4329                 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
4330         }
4331
4332         return ret;
4333 }
4334
4335 /**
4336  * ixgbe_configure_dcb - Configure DCB  Hardware
4337  * @dev: pointer to rte_eth_dev
4338  */
4339 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
4340 {
4341         struct ixgbe_dcb_config *dcb_cfg =
4342                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4343         struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
4344
4345         PMD_INIT_FUNC_TRACE();
4346
4347         /* check support mq_mode for DCB */
4348         if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
4349             (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB) &&
4350             (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB_RSS))
4351                 return;
4352
4353         if (dev->data->nb_rx_queues > ETH_DCB_NUM_QUEUES)
4354                 return;
4355
4356         /** Configure DCB hardware **/
4357         ixgbe_dcb_hw_configure(dev, dcb_cfg);
4358 }
4359
4360 /*
4361  * VMDq only support for 10 GbE NIC.
4362  */
4363 static void
4364 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
4365 {
4366         struct rte_eth_vmdq_rx_conf *cfg;
4367         struct ixgbe_hw *hw;
4368         enum rte_eth_nb_pools num_pools;
4369         uint32_t mrqc, vt_ctl, vlanctrl;
4370         uint32_t vmolr = 0;
4371         int i;
4372
4373         PMD_INIT_FUNC_TRACE();
4374         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4375         cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
4376         num_pools = cfg->nb_queue_pools;
4377
4378         ixgbe_rss_disable(dev);
4379
4380         /* MRQC: enable vmdq */
4381         mrqc = IXGBE_MRQC_VMDQEN;
4382         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
4383
4384         /* PFVTCTL: turn on virtualisation and set the default pool */
4385         vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
4386         if (cfg->enable_default_pool)
4387                 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
4388         else
4389                 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
4390
4391         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
4392
4393         for (i = 0; i < (int)num_pools; i++) {
4394                 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
4395                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
4396         }
4397
4398         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
4399         vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4400         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
4401         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
4402
4403         /* VFTA - enable all vlan filters */
4404         for (i = 0; i < NUM_VFTA_REGISTERS; i++)
4405                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
4406
4407         /* VFRE: pool enabling for receive - 64 */
4408         IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
4409         if (num_pools == ETH_64_POOLS)
4410                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
4411
4412         /*
4413          * MPSAR - allow pools to read specific mac addresses
4414          * In this case, all pools should be able to read from mac addr 0
4415          */
4416         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
4417         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
4418
4419         /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
4420         for (i = 0; i < cfg->nb_pool_maps; i++) {
4421                 /* set vlan id in VF register and set the valid bit */
4422                 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN |
4423                                 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
4424                 /*
4425                  * Put the allowed pools in VFB reg. As we only have 16 or 64
4426                  * pools, we only need to use the first half of the register
4427                  * i.e. bits 0-31
4428                  */
4429                 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
4430                         IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i * 2),
4431                                         (cfg->pool_map[i].pools & UINT32_MAX));
4432                 else
4433                         IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i * 2 + 1)),
4434                                         ((cfg->pool_map[i].pools >> 32) & UINT32_MAX));
4435
4436         }
4437
4438         /* PFDMA Tx General Switch Control Enables VMDQ loopback */
4439         if (cfg->enable_loop_back) {
4440                 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
4441                 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
4442                         IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
4443         }
4444
4445         IXGBE_WRITE_FLUSH(hw);
4446 }
4447
4448 /*
4449  * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
4450  * @hw: pointer to hardware structure
4451  */
4452 static void
4453 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
4454 {
4455         uint32_t reg;
4456         uint32_t q;
4457
4458         PMD_INIT_FUNC_TRACE();
4459         /*PF VF Transmit Enable*/
4460         IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
4461         IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
4462
4463         /* Disable the Tx desc arbiter so that MTQC can be changed */
4464         reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
4465         reg |= IXGBE_RTTDCS_ARBDIS;
4466         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
4467
4468         reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
4469         IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
4470
4471         /* Disable drop for all queues */
4472         for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
4473                 IXGBE_WRITE_REG(hw, IXGBE_QDE,
4474                   (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
4475
4476         /* Enable the Tx desc arbiter */
4477         reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
4478         reg &= ~IXGBE_RTTDCS_ARBDIS;
4479         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
4480
4481         IXGBE_WRITE_FLUSH(hw);
4482 }
4483
4484 static int __rte_cold
4485 ixgbe_alloc_rx_queue_mbufs(struct ixgbe_rx_queue *rxq)
4486 {
4487         struct ixgbe_rx_entry *rxe = rxq->sw_ring;
4488         uint64_t dma_addr;
4489         unsigned int i;
4490
4491         /* Initialize software ring entries */
4492         for (i = 0; i < rxq->nb_rx_desc; i++) {
4493                 volatile union ixgbe_adv_rx_desc *rxd;
4494                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
4495
4496                 if (mbuf == NULL) {
4497                         PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
4498                                      (unsigned) rxq->queue_id);
4499                         return -ENOMEM;
4500                 }
4501
4502                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
4503                 mbuf->port = rxq->port_id;
4504
4505                 dma_addr =
4506                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
4507                 rxd = &rxq->rx_ring[i];
4508                 rxd->read.hdr_addr = 0;
4509                 rxd->read.pkt_addr = dma_addr;
4510                 rxe[i].mbuf = mbuf;
4511         }
4512
4513         return 0;
4514 }
4515
4516 static int
4517 ixgbe_config_vf_rss(struct rte_eth_dev *dev)
4518 {
4519         struct ixgbe_hw *hw;
4520         uint32_t mrqc;
4521
4522         ixgbe_rss_configure(dev);
4523
4524         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4525
4526         /* MRQC: enable VF RSS */
4527         mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
4528         mrqc &= ~IXGBE_MRQC_MRQE_MASK;
4529         switch (RTE_ETH_DEV_SRIOV(dev).active) {
4530         case ETH_64_POOLS:
4531                 mrqc |= IXGBE_MRQC_VMDQRSS64EN;
4532                 break;
4533
4534         case ETH_32_POOLS:
4535                 mrqc |= IXGBE_MRQC_VMDQRSS32EN;
4536                 break;
4537
4538         default:
4539                 PMD_INIT_LOG(ERR, "Invalid pool number in IOV mode with VMDQ RSS");
4540                 return -EINVAL;
4541         }
4542
4543         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
4544
4545         return 0;
4546 }
4547
4548 static int
4549 ixgbe_config_vf_default(struct rte_eth_dev *dev)
4550 {
4551         struct ixgbe_hw *hw =
4552                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4553
4554         switch (RTE_ETH_DEV_SRIOV(dev).active) {
4555         case ETH_64_POOLS:
4556                 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
4557                         IXGBE_MRQC_VMDQEN);
4558                 break;
4559
4560         case ETH_32_POOLS:
4561                 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
4562                         IXGBE_MRQC_VMDQRT4TCEN);
4563                 break;
4564
4565         case ETH_16_POOLS:
4566                 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
4567                         IXGBE_MRQC_VMDQRT8TCEN);
4568                 break;
4569         default:
4570                 PMD_INIT_LOG(ERR,
4571                         "invalid pool number in IOV mode");
4572                 break;
4573         }
4574         return 0;
4575 }
4576
4577 static int
4578 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
4579 {
4580         struct ixgbe_hw *hw =
4581                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4582
4583         if (hw->mac.type == ixgbe_mac_82598EB)
4584                 return 0;
4585
4586         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
4587                 /*
4588                  * SRIOV inactive scheme
4589                  * any DCB/RSS w/o VMDq multi-queue setting
4590                  */
4591                 switch (dev->data->dev_conf.rxmode.mq_mode) {
4592                 case ETH_MQ_RX_RSS:
4593                 case ETH_MQ_RX_DCB_RSS:
4594                 case ETH_MQ_RX_VMDQ_RSS:
4595                         ixgbe_rss_configure(dev);
4596                         break;
4597
4598                 case ETH_MQ_RX_VMDQ_DCB:
4599                         ixgbe_vmdq_dcb_configure(dev);
4600                         break;
4601
4602                 case ETH_MQ_RX_VMDQ_ONLY:
4603                         ixgbe_vmdq_rx_hw_configure(dev);
4604                         break;
4605
4606                 case ETH_MQ_RX_NONE:
4607                 default:
4608                         /* if mq_mode is none, disable rss mode.*/
4609                         ixgbe_rss_disable(dev);
4610                         break;
4611                 }
4612         } else {
4613                 /* SRIOV active scheme
4614                  * Support RSS together with SRIOV.
4615                  */
4616                 switch (dev->data->dev_conf.rxmode.mq_mode) {
4617                 case ETH_MQ_RX_RSS:
4618                 case ETH_MQ_RX_VMDQ_RSS:
4619                         ixgbe_config_vf_rss(dev);
4620                         break;
4621                 case ETH_MQ_RX_VMDQ_DCB:
4622                 case ETH_MQ_RX_DCB:
4623                 /* In SRIOV, the configuration is the same as VMDq case */
4624                         ixgbe_vmdq_dcb_configure(dev);
4625                         break;
4626                 /* DCB/RSS together with SRIOV is not supported */
4627                 case ETH_MQ_RX_VMDQ_DCB_RSS:
4628                 case ETH_MQ_RX_DCB_RSS:
4629                         PMD_INIT_LOG(ERR,
4630                                 "Could not support DCB/RSS with VMDq & SRIOV");
4631                         return -1;
4632                 default:
4633                         ixgbe_config_vf_default(dev);
4634                         break;
4635                 }
4636         }
4637
4638         return 0;
4639 }
4640
4641 static int
4642 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
4643 {
4644         struct ixgbe_hw *hw =
4645                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4646         uint32_t mtqc;
4647         uint32_t rttdcs;
4648
4649         if (hw->mac.type == ixgbe_mac_82598EB)
4650                 return 0;
4651
4652         /* disable arbiter before setting MTQC */
4653         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
4654         rttdcs |= IXGBE_RTTDCS_ARBDIS;
4655         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
4656
4657         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
4658                 /*
4659                  * SRIOV inactive scheme
4660                  * any DCB w/o VMDq multi-queue setting
4661                  */
4662                 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
4663                         ixgbe_vmdq_tx_hw_configure(hw);
4664                 else {
4665                         mtqc = IXGBE_MTQC_64Q_1PB;
4666                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
4667                 }
4668         } else {
4669                 switch (RTE_ETH_DEV_SRIOV(dev).active) {
4670
4671                 /*
4672                  * SRIOV active scheme
4673                  * FIXME if support DCB together with VMDq & SRIOV
4674                  */
4675                 case ETH_64_POOLS:
4676                         mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
4677                         break;
4678                 case ETH_32_POOLS:
4679                         mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
4680                         break;
4681                 case ETH_16_POOLS:
4682                         mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
4683                                 IXGBE_MTQC_8TC_8TQ;
4684                         break;
4685                 default:
4686                         mtqc = IXGBE_MTQC_64Q_1PB;
4687                         PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
4688                 }
4689                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
4690         }
4691
4692         /* re-enable arbiter */
4693         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
4694         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
4695
4696         return 0;
4697 }
4698
4699 /**
4700  * ixgbe_get_rscctl_maxdesc - Calculate the RSCCTL[n].MAXDESC for PF
4701  *
4702  * Return the RSCCTL[n].MAXDESC for 82599 and x540 PF devices according to the
4703  * spec rev. 3.0 chapter 8.2.3.8.13.
4704  *
4705  * @pool Memory pool of the Rx queue
4706  */
4707 static inline uint32_t
4708 ixgbe_get_rscctl_maxdesc(struct rte_mempool *pool)
4709 {
4710         struct rte_pktmbuf_pool_private *mp_priv = rte_mempool_get_priv(pool);
4711
4712         /* MAXDESC * SRRCTL.BSIZEPKT must not exceed 64 KB minus one */
4713         uint16_t maxdesc =
4714                 RTE_IPV4_MAX_PKT_LEN /
4715                         (mp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM);
4716
4717         if (maxdesc >= 16)
4718                 return IXGBE_RSCCTL_MAXDESC_16;
4719         else if (maxdesc >= 8)
4720                 return IXGBE_RSCCTL_MAXDESC_8;
4721         else if (maxdesc >= 4)
4722                 return IXGBE_RSCCTL_MAXDESC_4;
4723         else
4724                 return IXGBE_RSCCTL_MAXDESC_1;
4725 }
4726
4727 /**
4728  * ixgbe_set_ivar - Setup the correct IVAR register for a particular MSIX
4729  * interrupt
4730  *
4731  * (Taken from FreeBSD tree)
4732  * (yes this is all very magic and confusing :)
4733  *
4734  * @dev port handle
4735  * @entry the register array entry
4736  * @vector the MSIX vector for this queue
4737  * @type RX/TX/MISC
4738  */
4739 static void
4740 ixgbe_set_ivar(struct rte_eth_dev *dev, u8 entry, u8 vector, s8 type)
4741 {
4742         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4743         u32 ivar, index;
4744
4745         vector |= IXGBE_IVAR_ALLOC_VAL;
4746
4747         switch (hw->mac.type) {
4748
4749         case ixgbe_mac_82598EB:
4750                 if (type == -1)
4751                         entry = IXGBE_IVAR_OTHER_CAUSES_INDEX;
4752                 else
4753                         entry += (type * 64);
4754                 index = (entry >> 2) & 0x1F;
4755                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
4756                 ivar &= ~(0xFF << (8 * (entry & 0x3)));
4757                 ivar |= (vector << (8 * (entry & 0x3)));
4758                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
4759                 break;
4760
4761         case ixgbe_mac_82599EB:
4762         case ixgbe_mac_X540:
4763                 if (type == -1) { /* MISC IVAR */
4764                         index = (entry & 1) * 8;
4765                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4766                         ivar &= ~(0xFF << index);
4767                         ivar |= (vector << index);
4768                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
4769                 } else {        /* RX/TX IVARS */
4770                         index = (16 * (entry & 1)) + (8 * type);
4771                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1));
4772                         ivar &= ~(0xFF << index);
4773                         ivar |= (vector << index);
4774                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar);
4775                 }
4776
4777                 break;
4778
4779         default:
4780                 break;
4781         }
4782 }
4783
4784 void __rte_cold
4785 ixgbe_set_rx_function(struct rte_eth_dev *dev)
4786 {
4787         uint16_t i, rx_using_sse;
4788         struct ixgbe_adapter *adapter = dev->data->dev_private;
4789
4790         /*
4791          * In order to allow Vector Rx there are a few configuration
4792          * conditions to be met and Rx Bulk Allocation should be allowed.
4793          */
4794         if (ixgbe_rx_vec_dev_conf_condition_check(dev) ||
4795             !adapter->rx_bulk_alloc_allowed ||
4796                         rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128) {
4797                 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx "
4798                                     "preconditions",
4799                              dev->data->port_id);
4800
4801                 adapter->rx_vec_allowed = false;
4802         }
4803
4804         /*
4805          * Initialize the appropriate LRO callback.
4806          *
4807          * If all queues satisfy the bulk allocation preconditions
4808          * (hw->rx_bulk_alloc_allowed is TRUE) then we may use bulk allocation.
4809          * Otherwise use a single allocation version.
4810          */
4811         if (dev->data->lro) {
4812                 if (adapter->rx_bulk_alloc_allowed) {
4813                         PMD_INIT_LOG(DEBUG, "LRO is requested. Using a bulk "
4814                                            "allocation version");
4815                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
4816                 } else {
4817                         PMD_INIT_LOG(DEBUG, "LRO is requested. Using a single "
4818                                            "allocation version");
4819                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
4820                 }
4821         } else if (dev->data->scattered_rx) {
4822                 /*
4823                  * Set the non-LRO scattered callback: there are Vector and
4824                  * single allocation versions.
4825                  */
4826                 if (adapter->rx_vec_allowed) {
4827                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
4828                                             "callback (port=%d).",
4829                                      dev->data->port_id);
4830
4831                         dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
4832                 } else if (adapter->rx_bulk_alloc_allowed) {
4833                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
4834                                            "allocation callback (port=%d).",
4835                                      dev->data->port_id);
4836                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
4837                 } else {
4838                         PMD_INIT_LOG(DEBUG, "Using Regualr (non-vector, "
4839                                             "single allocation) "
4840                                             "Scattered Rx callback "
4841                                             "(port=%d).",
4842                                      dev->data->port_id);
4843
4844                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
4845                 }
4846         /*
4847          * Below we set "simple" callbacks according to port/queues parameters.
4848          * If parameters allow we are going to choose between the following
4849          * callbacks:
4850          *    - Vector
4851          *    - Bulk Allocation
4852          *    - Single buffer allocation (the simplest one)
4853          */
4854         } else if (adapter->rx_vec_allowed) {
4855                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
4856                                     "burst size no less than %d (port=%d).",
4857                              RTE_IXGBE_DESCS_PER_LOOP,
4858                              dev->data->port_id);
4859
4860                 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
4861         } else if (adapter->rx_bulk_alloc_allowed) {
4862                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
4863                                     "satisfied. Rx Burst Bulk Alloc function "
4864                                     "will be used on port=%d.",
4865                              dev->data->port_id);
4866
4867                 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
4868         } else {
4869                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
4870                                     "satisfied, or Scattered Rx is requested "
4871                                     "(port=%d).",
4872                              dev->data->port_id);
4873
4874                 dev->rx_pkt_burst = ixgbe_recv_pkts;
4875         }
4876
4877         /* Propagate information about RX function choice through all queues. */
4878
4879         rx_using_sse =
4880                 (dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec ||
4881                 dev->rx_pkt_burst == ixgbe_recv_pkts_vec);
4882
4883         for (i = 0; i < dev->data->nb_rx_queues; i++) {
4884                 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4885
4886                 rxq->rx_using_sse = rx_using_sse;
4887 #ifdef RTE_LIB_SECURITY
4888                 rxq->using_ipsec = !!(dev->data->dev_conf.rxmode.offloads &
4889                                 DEV_RX_OFFLOAD_SECURITY);
4890 #endif
4891         }
4892 }
4893
4894 /**
4895  * ixgbe_set_rsc - configure RSC related port HW registers
4896  *
4897  * Configures the port's RSC related registers according to the 4.6.7.2 chapter
4898  * of 82599 Spec (x540 configuration is virtually the same).
4899  *
4900  * @dev port handle
4901  *
4902  * Returns 0 in case of success or a non-zero error code
4903  */
4904 static int
4905 ixgbe_set_rsc(struct rte_eth_dev *dev)
4906 {
4907         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4908         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4909         struct rte_eth_dev_info dev_info = { 0 };
4910         bool rsc_capable = false;
4911         uint16_t i;
4912         uint32_t rdrxctl;
4913         uint32_t rfctl;
4914
4915         /* Sanity check */
4916         dev->dev_ops->dev_infos_get(dev, &dev_info);
4917         if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_TCP_LRO)
4918                 rsc_capable = true;
4919
4920         if (!rsc_capable && (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO)) {
4921                 PMD_INIT_LOG(CRIT, "LRO is requested on HW that doesn't "
4922                                    "support it");
4923                 return -EINVAL;
4924         }
4925
4926         /* RSC global configuration (chapter 4.6.7.2.1 of 82599 Spec) */
4927
4928         if ((rx_conf->offloads & DEV_RX_OFFLOAD_KEEP_CRC) &&
4929              (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO)) {
4930                 /*
4931                  * According to chapter of 4.6.7.2.1 of the Spec Rev.
4932                  * 3.0 RSC configuration requires HW CRC stripping being
4933                  * enabled. If user requested both HW CRC stripping off
4934                  * and RSC on - return an error.
4935                  */
4936                 PMD_INIT_LOG(CRIT, "LRO can't be enabled when HW CRC "
4937                                     "is disabled");
4938                 return -EINVAL;
4939         }
4940
4941         /* RFCTL configuration  */
4942         rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4943         if ((rsc_capable) && (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO))
4944                 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
4945         else
4946                 rfctl |= IXGBE_RFCTL_RSC_DIS;
4947         /* disable NFS filtering */
4948         rfctl |= IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS;
4949         IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4950
4951         /* If LRO hasn't been requested - we are done here. */
4952         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO))
4953                 return 0;
4954
4955         /* Set RDRXCTL.RSCACKC bit */
4956         rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4957         rdrxctl |= IXGBE_RDRXCTL_RSCACKC;
4958         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4959
4960         /* Per-queue RSC configuration (chapter 4.6.7.2.2 of 82599 Spec) */
4961         for (i = 0; i < dev->data->nb_rx_queues; i++) {
4962                 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4963                 uint32_t srrctl =
4964                         IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxq->reg_idx));
4965                 uint32_t rscctl =
4966                         IXGBE_READ_REG(hw, IXGBE_RSCCTL(rxq->reg_idx));
4967                 uint32_t psrtype =
4968                         IXGBE_READ_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx));
4969                 uint32_t eitr =
4970                         IXGBE_READ_REG(hw, IXGBE_EITR(rxq->reg_idx));
4971
4972                 /*
4973                  * ixgbe PMD doesn't support header-split at the moment.
4974                  *
4975                  * Following the 4.6.7.2.1 chapter of the 82599/x540
4976                  * Spec if RSC is enabled the SRRCTL[n].BSIZEHEADER
4977                  * should be configured even if header split is not
4978                  * enabled. We will configure it 128 bytes following the
4979                  * recommendation in the spec.
4980                  */
4981                 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
4982                 srrctl |= (128 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4983                                             IXGBE_SRRCTL_BSIZEHDR_MASK;
4984
4985                 /*
4986                  * TODO: Consider setting the Receive Descriptor Minimum
4987                  * Threshold Size for an RSC case. This is not an obviously
4988                  * beneficiary option but the one worth considering...
4989                  */
4990
4991                 rscctl |= IXGBE_RSCCTL_RSCEN;
4992                 rscctl |= ixgbe_get_rscctl_maxdesc(rxq->mb_pool);
4993                 psrtype |= IXGBE_PSRTYPE_TCPHDR;
4994
4995                 /*
4996                  * RSC: Set ITR interval corresponding to 2K ints/s.
4997                  *
4998                  * Full-sized RSC aggregations for a 10Gb/s link will
4999                  * arrive at about 20K aggregation/s rate.
5000                  *
5001                  * 2K inst/s rate will make only 10% of the
5002                  * aggregations to be closed due to the interrupt timer
5003                  * expiration for a streaming at wire-speed case.
5004                  *
5005                  * For a sparse streaming case this setting will yield
5006                  * at most 500us latency for a single RSC aggregation.
5007                  */
5008                 eitr &= ~IXGBE_EITR_ITR_INT_MASK;
5009                 eitr |= IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT);
5010                 eitr |= IXGBE_EITR_CNT_WDIS;
5011
5012                 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
5013                 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(rxq->reg_idx), rscctl);
5014                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
5015                 IXGBE_WRITE_REG(hw, IXGBE_EITR(rxq->reg_idx), eitr);
5016
5017                 /*
5018                  * RSC requires the mapping of the queue to the
5019                  * interrupt vector.
5020                  */
5021                 ixgbe_set_ivar(dev, rxq->reg_idx, i, 0);
5022         }
5023
5024         dev->data->lro = 1;
5025
5026         PMD_INIT_LOG(DEBUG, "enabling LRO mode");
5027
5028         return 0;
5029 }
5030
5031 /*
5032  * Initializes Receive Unit.
5033  */
5034 int __rte_cold
5035 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
5036 {
5037         struct ixgbe_hw     *hw;
5038         struct ixgbe_rx_queue *rxq;
5039         uint64_t bus_addr;
5040         uint32_t rxctrl;
5041         uint32_t fctrl;
5042         uint32_t hlreg0;
5043         uint32_t maxfrs;
5044         uint32_t srrctl;
5045         uint32_t rdrxctl;
5046         uint32_t rxcsum;
5047         uint16_t buf_size;
5048         uint16_t i;
5049         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
5050         int rc;
5051
5052         PMD_INIT_FUNC_TRACE();
5053         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5054
5055         /*
5056          * Make sure receives are disabled while setting
5057          * up the RX context (registers, descriptor rings, etc.).
5058          */
5059         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5060         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
5061
5062         /* Enable receipt of broadcasted frames */
5063         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5064         fctrl |= IXGBE_FCTRL_BAM;
5065         fctrl |= IXGBE_FCTRL_DPF;
5066         fctrl |= IXGBE_FCTRL_PMCF;
5067         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5068
5069         /*
5070          * Configure CRC stripping, if any.
5071          */
5072         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5073         if (rx_conf->offloads & DEV_RX_OFFLOAD_KEEP_CRC)
5074                 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
5075         else
5076                 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
5077
5078         /*
5079          * Configure jumbo frame support, if any.
5080          */
5081         if (rx_conf->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
5082                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5083                 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5084                 maxfrs &= 0x0000FFFF;
5085                 maxfrs |= (rx_conf->max_rx_pkt_len << 16);
5086                 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5087         } else
5088                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5089
5090         /*
5091          * If loopback mode is configured, set LPBK bit.
5092          */
5093         if (dev->data->dev_conf.lpbk_mode != 0) {
5094                 rc = ixgbe_check_supported_loopback_mode(dev);
5095                 if (rc < 0) {
5096                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
5097                         return rc;
5098                 }
5099                 hlreg0 |= IXGBE_HLREG0_LPBK;
5100         } else {
5101                 hlreg0 &= ~IXGBE_HLREG0_LPBK;
5102         }
5103
5104         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5105
5106         /*
5107          * Assume no header split and no VLAN strip support
5108          * on any Rx queue first .
5109          */
5110         rx_conf->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
5111         /* Setup RX queues */
5112         for (i = 0; i < dev->data->nb_rx_queues; i++) {
5113                 rxq = dev->data->rx_queues[i];
5114
5115                 /*
5116                  * Reset crc_len in case it was changed after queue setup by a
5117                  * call to configure.
5118                  */
5119                 if (rx_conf->offloads & DEV_RX_OFFLOAD_KEEP_CRC)
5120                         rxq->crc_len = RTE_ETHER_CRC_LEN;
5121                 else
5122                         rxq->crc_len = 0;
5123
5124                 /* Setup the Base and Length of the Rx Descriptor Rings */
5125                 bus_addr = rxq->rx_ring_phys_addr;
5126                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
5127                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
5128                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
5129                                 (uint32_t)(bus_addr >> 32));
5130                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
5131                                 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
5132                 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
5133                 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
5134
5135                 /* Configure the SRRCTL register */
5136                 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
5137
5138                 /* Set if packets are dropped when no descriptors available */
5139                 if (rxq->drop_en)
5140                         srrctl |= IXGBE_SRRCTL_DROP_EN;
5141
5142                 /*
5143                  * Configure the RX buffer size in the BSIZEPACKET field of
5144                  * the SRRCTL register of the queue.
5145                  * The value is in 1 KB resolution. Valid values can be from
5146                  * 1 KB to 16 KB.
5147                  */
5148                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
5149                         RTE_PKTMBUF_HEADROOM);
5150                 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
5151                            IXGBE_SRRCTL_BSIZEPKT_MASK);
5152
5153                 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
5154
5155                 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
5156                                        IXGBE_SRRCTL_BSIZEPKT_SHIFT);
5157
5158                 /* It adds dual VLAN length for supporting dual VLAN */
5159                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
5160                                             2 * IXGBE_VLAN_TAG_SIZE > buf_size)
5161                         dev->data->scattered_rx = 1;
5162                 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
5163                         rx_conf->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
5164         }
5165
5166         if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)
5167                 dev->data->scattered_rx = 1;
5168
5169         /*
5170          * Device configured with multiple RX queues.
5171          */
5172         ixgbe_dev_mq_rx_configure(dev);
5173
5174         /*
5175          * Setup the Checksum Register.
5176          * Disable Full-Packet Checksum which is mutually exclusive with RSS.
5177          * Enable IP/L4 checkum computation by hardware if requested to do so.
5178          */
5179         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
5180         rxcsum |= IXGBE_RXCSUM_PCSD;
5181         if (rx_conf->offloads & DEV_RX_OFFLOAD_CHECKSUM)
5182                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
5183         else
5184                 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
5185
5186         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
5187
5188         if (hw->mac.type == ixgbe_mac_82599EB ||
5189             hw->mac.type == ixgbe_mac_X540) {
5190                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
5191                 if (rx_conf->offloads & DEV_RX_OFFLOAD_KEEP_CRC)
5192                         rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
5193                 else
5194                         rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
5195                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
5196                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
5197         }
5198
5199         rc = ixgbe_set_rsc(dev);
5200         if (rc)
5201                 return rc;
5202
5203         ixgbe_set_rx_function(dev);
5204
5205         return 0;
5206 }
5207
5208 /*
5209  * Initializes Transmit Unit.
5210  */
5211 void __rte_cold
5212 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
5213 {
5214         struct ixgbe_hw     *hw;
5215         struct ixgbe_tx_queue *txq;
5216         uint64_t bus_addr;
5217         uint32_t hlreg0;
5218         uint32_t txctrl;
5219         uint16_t i;
5220
5221         PMD_INIT_FUNC_TRACE();
5222         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5223
5224         /* Enable TX CRC (checksum offload requirement) and hw padding
5225          * (TSO requirement)
5226          */
5227         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5228         hlreg0 |= (IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);
5229         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5230
5231         /* Setup the Base and Length of the Tx Descriptor Rings */
5232         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5233                 txq = dev->data->tx_queues[i];
5234
5235                 bus_addr = txq->tx_ring_phys_addr;
5236                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
5237                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
5238                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
5239                                 (uint32_t)(bus_addr >> 32));
5240                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
5241                                 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
5242                 /* Setup the HW Tx Head and TX Tail descriptor pointers */
5243                 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
5244                 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
5245
5246                 /*
5247                  * Disable Tx Head Writeback RO bit, since this hoses
5248                  * bookkeeping if things aren't delivered in order.
5249                  */
5250                 switch (hw->mac.type) {
5251                 case ixgbe_mac_82598EB:
5252                         txctrl = IXGBE_READ_REG(hw,
5253                                                 IXGBE_DCA_TXCTRL(txq->reg_idx));
5254                         txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
5255                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
5256                                         txctrl);
5257                         break;
5258
5259                 case ixgbe_mac_82599EB:
5260                 case ixgbe_mac_X540:
5261                 case ixgbe_mac_X550:
5262                 case ixgbe_mac_X550EM_x:
5263                 case ixgbe_mac_X550EM_a:
5264                 default:
5265                         txctrl = IXGBE_READ_REG(hw,
5266                                                 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
5267                         txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
5268                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
5269                                         txctrl);
5270                         break;
5271                 }
5272         }
5273
5274         /* Device configured with multiple TX queues. */
5275         ixgbe_dev_mq_tx_configure(dev);
5276 }
5277
5278 /*
5279  * Check if requested loopback mode is supported
5280  */
5281 int
5282 ixgbe_check_supported_loopback_mode(struct rte_eth_dev *dev)
5283 {
5284         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5285
5286         if (dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_TX_RX)
5287                 if (hw->mac.type == ixgbe_mac_82599EB ||
5288                      hw->mac.type == ixgbe_mac_X540 ||
5289                      hw->mac.type == ixgbe_mac_X550 ||
5290                      hw->mac.type == ixgbe_mac_X550EM_x ||
5291                      hw->mac.type == ixgbe_mac_X550EM_a)
5292                         return 0;
5293
5294         return -ENOTSUP;
5295 }
5296
5297 /*
5298  * Set up link for 82599 loopback mode Tx->Rx.
5299  */
5300 static inline void __rte_cold
5301 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
5302 {
5303         PMD_INIT_FUNC_TRACE();
5304
5305         if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
5306                 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
5307                                 IXGBE_SUCCESS) {
5308                         PMD_INIT_LOG(ERR, "Could not enable loopback mode");
5309                         /* ignore error */
5310                         return;
5311                 }
5312         }
5313
5314         /* Restart link */
5315         IXGBE_WRITE_REG(hw,
5316                         IXGBE_AUTOC,
5317                         IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
5318         ixgbe_reset_pipeline_82599(hw);
5319
5320         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
5321         msec_delay(50);
5322 }
5323
5324
5325 /*
5326  * Start Transmit and Receive Units.
5327  */
5328 int __rte_cold
5329 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
5330 {
5331         struct ixgbe_hw     *hw;
5332         struct ixgbe_tx_queue *txq;
5333         struct ixgbe_rx_queue *rxq;
5334         uint32_t txdctl;
5335         uint32_t dmatxctl;
5336         uint32_t rxctrl;
5337         uint16_t i;
5338         int ret = 0;
5339
5340         PMD_INIT_FUNC_TRACE();
5341         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5342
5343         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5344                 txq = dev->data->tx_queues[i];
5345                 /* Setup Transmit Threshold Registers */
5346                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
5347                 txdctl |= txq->pthresh & 0x7F;
5348                 txdctl |= ((txq->hthresh & 0x7F) << 8);
5349                 txdctl |= ((txq->wthresh & 0x7F) << 16);
5350                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
5351         }
5352
5353         if (hw->mac.type != ixgbe_mac_82598EB) {
5354                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
5355                 dmatxctl |= IXGBE_DMATXCTL_TE;
5356                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
5357         }
5358
5359         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5360                 txq = dev->data->tx_queues[i];
5361                 if (!txq->tx_deferred_start) {
5362                         ret = ixgbe_dev_tx_queue_start(dev, i);
5363                         if (ret < 0)
5364                                 return ret;
5365                 }
5366         }
5367
5368         for (i = 0; i < dev->data->nb_rx_queues; i++) {
5369                 rxq = dev->data->rx_queues[i];
5370                 if (!rxq->rx_deferred_start) {
5371                         ret = ixgbe_dev_rx_queue_start(dev, i);
5372                         if (ret < 0)
5373                                 return ret;
5374                 }
5375         }
5376
5377         /* Enable Receive engine */
5378         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5379         if (hw->mac.type == ixgbe_mac_82598EB)
5380                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
5381         rxctrl |= IXGBE_RXCTRL_RXEN;
5382         hw->mac.ops.enable_rx_dma(hw, rxctrl);
5383
5384         /* If loopback mode is enabled, set up the link accordingly */
5385         if (dev->data->dev_conf.lpbk_mode != 0) {
5386                 if (hw->mac.type == ixgbe_mac_82599EB)
5387                         ixgbe_setup_loopback_link_82599(hw);
5388                 else if (hw->mac.type == ixgbe_mac_X540 ||
5389                      hw->mac.type == ixgbe_mac_X550 ||
5390                      hw->mac.type == ixgbe_mac_X550EM_x ||
5391                      hw->mac.type == ixgbe_mac_X550EM_a)
5392                         ixgbe_setup_loopback_link_x540_x550(hw, true);
5393         }
5394
5395 #ifdef RTE_LIB_SECURITY
5396         if ((dev->data->dev_conf.rxmode.offloads &
5397                         DEV_RX_OFFLOAD_SECURITY) ||
5398                 (dev->data->dev_conf.txmode.offloads &
5399                         DEV_TX_OFFLOAD_SECURITY)) {
5400                 ret = ixgbe_crypto_enable_ipsec(dev);
5401                 if (ret != 0) {
5402                         PMD_DRV_LOG(ERR,
5403                                     "ixgbe_crypto_enable_ipsec fails with %d.",
5404                                     ret);
5405                         return ret;
5406                 }
5407         }
5408 #endif
5409
5410         return 0;
5411 }
5412
5413 /*
5414  * Start Receive Units for specified queue.
5415  */
5416 int __rte_cold
5417 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
5418 {
5419         struct ixgbe_hw     *hw;
5420         struct ixgbe_rx_queue *rxq;
5421         uint32_t rxdctl;
5422         int poll_ms;
5423
5424         PMD_INIT_FUNC_TRACE();
5425         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5426
5427         rxq = dev->data->rx_queues[rx_queue_id];
5428
5429         /* Allocate buffers for descriptor rings */
5430         if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
5431                 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
5432                              rx_queue_id);
5433                 return -1;
5434         }
5435         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5436         rxdctl |= IXGBE_RXDCTL_ENABLE;
5437         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
5438
5439         /* Wait until RX Enable ready */
5440         poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5441         do {
5442                 rte_delay_ms(1);
5443                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5444         } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
5445         if (!poll_ms)
5446                 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", rx_queue_id);
5447         rte_wmb();
5448         IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
5449         IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
5450         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
5451
5452         return 0;
5453 }
5454
5455 /*
5456  * Stop Receive Units for specified queue.
5457  */
5458 int __rte_cold
5459 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
5460 {
5461         struct ixgbe_hw     *hw;
5462         struct ixgbe_adapter *adapter = dev->data->dev_private;
5463         struct ixgbe_rx_queue *rxq;
5464         uint32_t rxdctl;
5465         int poll_ms;
5466
5467         PMD_INIT_FUNC_TRACE();
5468         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5469
5470         rxq = dev->data->rx_queues[rx_queue_id];
5471
5472         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5473         rxdctl &= ~IXGBE_RXDCTL_ENABLE;
5474         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
5475
5476         /* Wait until RX Enable bit clear */
5477         poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5478         do {
5479                 rte_delay_ms(1);
5480                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5481         } while (--poll_ms && (rxdctl & IXGBE_RXDCTL_ENABLE));
5482         if (!poll_ms)
5483                 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d", rx_queue_id);
5484
5485         rte_delay_us(RTE_IXGBE_WAIT_100_US);
5486
5487         ixgbe_rx_queue_release_mbufs(rxq);
5488         ixgbe_reset_rx_queue(adapter, rxq);
5489         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
5490
5491         return 0;
5492 }
5493
5494
5495 /*
5496  * Start Transmit Units for specified queue.
5497  */
5498 int __rte_cold
5499 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
5500 {
5501         struct ixgbe_hw     *hw;
5502         struct ixgbe_tx_queue *txq;
5503         uint32_t txdctl;
5504         int poll_ms;
5505
5506         PMD_INIT_FUNC_TRACE();
5507         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5508
5509         txq = dev->data->tx_queues[tx_queue_id];
5510         IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
5511         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
5512         txdctl |= IXGBE_TXDCTL_ENABLE;
5513         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
5514
5515         /* Wait until TX Enable ready */
5516         if (hw->mac.type == ixgbe_mac_82599EB) {
5517                 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5518                 do {
5519                         rte_delay_ms(1);
5520                         txdctl = IXGBE_READ_REG(hw,
5521                                 IXGBE_TXDCTL(txq->reg_idx));
5522                 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
5523                 if (!poll_ms)
5524                         PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d",
5525                                 tx_queue_id);
5526         }
5527         rte_wmb();
5528         IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
5529         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
5530
5531         return 0;
5532 }
5533
5534 /*
5535  * Stop Transmit Units for specified queue.
5536  */
5537 int __rte_cold
5538 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
5539 {
5540         struct ixgbe_hw     *hw;
5541         struct ixgbe_tx_queue *txq;
5542         uint32_t txdctl;
5543         uint32_t txtdh, txtdt;
5544         int poll_ms;
5545
5546         PMD_INIT_FUNC_TRACE();
5547         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5548
5549         txq = dev->data->tx_queues[tx_queue_id];
5550
5551         /* Wait until TX queue is empty */
5552         if (hw->mac.type == ixgbe_mac_82599EB) {
5553                 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5554                 do {
5555                         rte_delay_us(RTE_IXGBE_WAIT_100_US);
5556                         txtdh = IXGBE_READ_REG(hw,
5557                                                IXGBE_TDH(txq->reg_idx));
5558                         txtdt = IXGBE_READ_REG(hw,
5559                                                IXGBE_TDT(txq->reg_idx));
5560                 } while (--poll_ms && (txtdh != txtdt));
5561                 if (!poll_ms)
5562                         PMD_INIT_LOG(ERR,
5563                                 "Tx Queue %d is not empty when stopping.",
5564                                 tx_queue_id);
5565         }
5566
5567         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
5568         txdctl &= ~IXGBE_TXDCTL_ENABLE;
5569         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
5570
5571         /* Wait until TX Enable bit clear */
5572         if (hw->mac.type == ixgbe_mac_82599EB) {
5573                 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5574                 do {
5575                         rte_delay_ms(1);
5576                         txdctl = IXGBE_READ_REG(hw,
5577                                                 IXGBE_TXDCTL(txq->reg_idx));
5578                 } while (--poll_ms && (txdctl & IXGBE_TXDCTL_ENABLE));
5579                 if (!poll_ms)
5580                         PMD_INIT_LOG(ERR, "Could not disable Tx Queue %d",
5581                                 tx_queue_id);
5582         }
5583
5584         if (txq->ops != NULL) {
5585                 txq->ops->release_mbufs(txq);
5586                 txq->ops->reset(txq);
5587         }
5588         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
5589
5590         return 0;
5591 }
5592
5593 void
5594 ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
5595         struct rte_eth_rxq_info *qinfo)
5596 {
5597         struct ixgbe_rx_queue *rxq;
5598
5599         rxq = dev->data->rx_queues[queue_id];
5600
5601         qinfo->mp = rxq->mb_pool;
5602         qinfo->scattered_rx = dev->data->scattered_rx;
5603         qinfo->nb_desc = rxq->nb_rx_desc;
5604
5605         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
5606         qinfo->conf.rx_drop_en = rxq->drop_en;
5607         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
5608         qinfo->conf.offloads = rxq->offloads;
5609 }
5610
5611 void
5612 ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
5613         struct rte_eth_txq_info *qinfo)
5614 {
5615         struct ixgbe_tx_queue *txq;
5616
5617         txq = dev->data->tx_queues[queue_id];
5618
5619         qinfo->nb_desc = txq->nb_tx_desc;
5620
5621         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
5622         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
5623         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
5624
5625         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
5626         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
5627         qinfo->conf.offloads = txq->offloads;
5628         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
5629 }
5630
5631 /*
5632  * [VF] Initializes Receive Unit.
5633  */
5634 int __rte_cold
5635 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
5636 {
5637         struct ixgbe_hw     *hw;
5638         struct ixgbe_rx_queue *rxq;
5639         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
5640         uint64_t bus_addr;
5641         uint32_t srrctl, psrtype = 0;
5642         uint16_t buf_size;
5643         uint16_t i;
5644         int ret;
5645
5646         PMD_INIT_FUNC_TRACE();
5647         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5648
5649         if (rte_is_power_of_2(dev->data->nb_rx_queues) == 0) {
5650                 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
5651                         "it should be power of 2");
5652                 return -1;
5653         }
5654
5655         if (dev->data->nb_rx_queues > hw->mac.max_rx_queues) {
5656                 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
5657                         "it should be equal to or less than %d",
5658                         hw->mac.max_rx_queues);
5659                 return -1;
5660         }
5661
5662         /*
5663          * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
5664          * disables the VF receipt of packets if the PF MTU is > 1500.
5665          * This is done to deal with 82599 limitations that imposes
5666          * the PF and all VFs to share the same MTU.
5667          * Then, the PF driver enables again the VF receipt of packet when
5668          * the VF driver issues a IXGBE_VF_SET_LPE request.
5669          * In the meantime, the VF device cannot be used, even if the VF driver
5670          * and the Guest VM network stack are ready to accept packets with a
5671          * size up to the PF MTU.
5672          * As a work-around to this PF behaviour, force the call to
5673          * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
5674          * VF packets received can work in all cases.
5675          */
5676         if (ixgbevf_rlpml_set_vf(hw,
5677             (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len)) {
5678                 PMD_INIT_LOG(ERR, "Set max packet length to %d failed.",
5679                              dev->data->dev_conf.rxmode.max_rx_pkt_len);
5680                 return -EINVAL;
5681         }
5682
5683         /*
5684          * Assume no header split and no VLAN strip support
5685          * on any Rx queue first .
5686          */
5687         rxmode->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
5688         /* Setup RX queues */
5689         for (i = 0; i < dev->data->nb_rx_queues; i++) {
5690                 rxq = dev->data->rx_queues[i];
5691
5692                 /* Allocate buffers for descriptor rings */
5693                 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
5694                 if (ret)
5695                         return ret;
5696
5697                 /* Setup the Base and Length of the Rx Descriptor Rings */
5698                 bus_addr = rxq->rx_ring_phys_addr;
5699
5700                 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
5701                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
5702                 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
5703                                 (uint32_t)(bus_addr >> 32));
5704                 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
5705                                 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
5706                 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
5707                 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
5708
5709
5710                 /* Configure the SRRCTL register */
5711                 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
5712
5713                 /* Set if packets are dropped when no descriptors available */
5714                 if (rxq->drop_en)
5715                         srrctl |= IXGBE_SRRCTL_DROP_EN;
5716
5717                 /*
5718                  * Configure the RX buffer size in the BSIZEPACKET field of
5719                  * the SRRCTL register of the queue.
5720                  * The value is in 1 KB resolution. Valid values can be from
5721                  * 1 KB to 16 KB.
5722                  */
5723                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
5724                         RTE_PKTMBUF_HEADROOM);
5725                 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
5726                            IXGBE_SRRCTL_BSIZEPKT_MASK);
5727
5728                 /*
5729                  * VF modification to write virtual function SRRCTL register
5730                  */
5731                 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
5732
5733                 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
5734                                        IXGBE_SRRCTL_BSIZEPKT_SHIFT);
5735
5736                 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER ||
5737                     /* It adds dual VLAN length for supporting dual VLAN */
5738                     (rxmode->max_rx_pkt_len +
5739                                 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
5740                         if (!dev->data->scattered_rx)
5741                                 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
5742                         dev->data->scattered_rx = 1;
5743                 }
5744
5745                 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
5746                         rxmode->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
5747         }
5748
5749         /* Set RQPL for VF RSS according to max Rx queue */
5750         psrtype |= (dev->data->nb_rx_queues >> 1) <<
5751                 IXGBE_PSRTYPE_RQPL_SHIFT;
5752         IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
5753
5754         ixgbe_set_rx_function(dev);
5755
5756         return 0;
5757 }
5758
5759 /*
5760  * [VF] Initializes Transmit Unit.
5761  */
5762 void __rte_cold
5763 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
5764 {
5765         struct ixgbe_hw     *hw;
5766         struct ixgbe_tx_queue *txq;
5767         uint64_t bus_addr;
5768         uint32_t txctrl;
5769         uint16_t i;
5770
5771         PMD_INIT_FUNC_TRACE();
5772         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5773
5774         /* Setup the Base and Length of the Tx Descriptor Rings */
5775         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5776                 txq = dev->data->tx_queues[i];
5777                 bus_addr = txq->tx_ring_phys_addr;
5778                 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
5779                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
5780                 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
5781                                 (uint32_t)(bus_addr >> 32));
5782                 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
5783                                 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
5784                 /* Setup the HW Tx Head and TX Tail descriptor pointers */
5785                 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
5786                 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
5787
5788                 /*
5789                  * Disable Tx Head Writeback RO bit, since this hoses
5790                  * bookkeeping if things aren't delivered in order.
5791                  */
5792                 txctrl = IXGBE_READ_REG(hw,
5793                                 IXGBE_VFDCA_TXCTRL(i));
5794                 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
5795                 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
5796                                 txctrl);
5797         }
5798 }
5799
5800 /*
5801  * [VF] Start Transmit and Receive Units.
5802  */
5803 void __rte_cold
5804 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
5805 {
5806         struct ixgbe_hw     *hw;
5807         struct ixgbe_tx_queue *txq;
5808         struct ixgbe_rx_queue *rxq;
5809         uint32_t txdctl;
5810         uint32_t rxdctl;
5811         uint16_t i;
5812         int poll_ms;
5813
5814         PMD_INIT_FUNC_TRACE();
5815         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5816
5817         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5818                 txq = dev->data->tx_queues[i];
5819                 /* Setup Transmit Threshold Registers */
5820                 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5821                 txdctl |= txq->pthresh & 0x7F;
5822                 txdctl |= ((txq->hthresh & 0x7F) << 8);
5823                 txdctl |= ((txq->wthresh & 0x7F) << 16);
5824                 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
5825         }
5826
5827         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5828
5829                 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5830                 txdctl |= IXGBE_TXDCTL_ENABLE;
5831                 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
5832
5833                 poll_ms = 10;
5834                 /* Wait until TX Enable ready */
5835                 do {
5836                         rte_delay_ms(1);
5837                         txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5838                 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
5839                 if (!poll_ms)
5840                         PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
5841         }
5842         for (i = 0; i < dev->data->nb_rx_queues; i++) {
5843
5844                 rxq = dev->data->rx_queues[i];
5845
5846                 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
5847                 rxdctl |= IXGBE_RXDCTL_ENABLE;
5848                 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
5849
5850                 /* Wait until RX Enable ready */
5851                 poll_ms = 10;
5852                 do {
5853                         rte_delay_ms(1);
5854                         rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
5855                 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
5856                 if (!poll_ms)
5857                         PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
5858                 rte_wmb();
5859                 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);
5860
5861         }
5862 }
5863
5864 int
5865 ixgbe_rss_conf_init(struct ixgbe_rte_flow_rss_conf *out,
5866                     const struct rte_flow_action_rss *in)
5867 {
5868         if (in->key_len > RTE_DIM(out->key) ||
5869             in->queue_num > RTE_DIM(out->queue))
5870                 return -EINVAL;
5871         out->conf = (struct rte_flow_action_rss){
5872                 .func = in->func,
5873                 .level = in->level,
5874                 .types = in->types,
5875                 .key_len = in->key_len,
5876                 .queue_num = in->queue_num,
5877                 .key = memcpy(out->key, in->key, in->key_len),
5878                 .queue = memcpy(out->queue, in->queue,
5879                                 sizeof(*in->queue) * in->queue_num),
5880         };
5881         return 0;
5882 }
5883
5884 int
5885 ixgbe_action_rss_same(const struct rte_flow_action_rss *comp,
5886                       const struct rte_flow_action_rss *with)
5887 {
5888         return (comp->func == with->func &&
5889                 comp->level == with->level &&
5890                 comp->types == with->types &&
5891                 comp->key_len == with->key_len &&
5892                 comp->queue_num == with->queue_num &&
5893                 !memcmp(comp->key, with->key, with->key_len) &&
5894                 !memcmp(comp->queue, with->queue,
5895                         sizeof(*with->queue) * with->queue_num));
5896 }
5897
5898 int
5899 ixgbe_config_rss_filter(struct rte_eth_dev *dev,
5900                 struct ixgbe_rte_flow_rss_conf *conf, bool add)
5901 {
5902         struct ixgbe_hw *hw;
5903         uint32_t reta;
5904         uint16_t i;
5905         uint16_t j;
5906         uint16_t sp_reta_size;
5907         uint32_t reta_reg;
5908         struct rte_eth_rss_conf rss_conf = {
5909                 .rss_key = conf->conf.key_len ?
5910                         (void *)(uintptr_t)conf->conf.key : NULL,
5911                 .rss_key_len = conf->conf.key_len,
5912                 .rss_hf = conf->conf.types,
5913         };
5914         struct ixgbe_filter_info *filter_info =
5915                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5916
5917         PMD_INIT_FUNC_TRACE();
5918         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5919
5920         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5921
5922         if (!add) {
5923                 if (ixgbe_action_rss_same(&filter_info->rss_info.conf,
5924                                           &conf->conf)) {
5925                         ixgbe_rss_disable(dev);
5926                         memset(&filter_info->rss_info, 0,
5927                                 sizeof(struct ixgbe_rte_flow_rss_conf));
5928                         return 0;
5929                 }
5930                 return -EINVAL;
5931         }
5932
5933         if (filter_info->rss_info.conf.queue_num)
5934                 return -EINVAL;
5935         /* Fill in redirection table
5936          * The byte-swap is needed because NIC registers are in
5937          * little-endian order.
5938          */
5939         reta = 0;
5940         for (i = 0, j = 0; i < sp_reta_size; i++, j++) {
5941                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5942
5943                 if (j == conf->conf.queue_num)
5944                         j = 0;
5945                 reta = (reta << 8) | conf->conf.queue[j];
5946                 if ((i & 3) == 3)
5947                         IXGBE_WRITE_REG(hw, reta_reg,
5948                                         rte_bswap32(reta));
5949         }
5950
5951         /* Configure the RSS key and the RSS protocols used to compute
5952          * the RSS hash of input packets.
5953          */
5954         if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
5955                 ixgbe_rss_disable(dev);
5956                 return 0;
5957         }
5958         if (rss_conf.rss_key == NULL)
5959                 rss_conf.rss_key = rss_intel_key; /* Default hash key */
5960         ixgbe_hw_rss_hash_set(hw, &rss_conf);
5961
5962         if (ixgbe_rss_conf_init(&filter_info->rss_info, &conf->conf))
5963                 return -EINVAL;
5964
5965         return 0;
5966 }
5967
5968 /* Stubs needed for linkage when RTE_ARCH_PPC_64 is set */
5969 #if defined(RTE_ARCH_PPC_64)
5970 int
5971 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
5972 {
5973         return -1;
5974 }
5975
5976 uint16_t
5977 ixgbe_recv_pkts_vec(
5978         void __rte_unused *rx_queue,
5979         struct rte_mbuf __rte_unused **rx_pkts,
5980         uint16_t __rte_unused nb_pkts)
5981 {
5982         return 0;
5983 }
5984
5985 uint16_t
5986 ixgbe_recv_scattered_pkts_vec(
5987         void __rte_unused *rx_queue,
5988         struct rte_mbuf __rte_unused **rx_pkts,
5989         uint16_t __rte_unused nb_pkts)
5990 {
5991         return 0;
5992 }
5993
5994 int
5995 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue __rte_unused *rxq)
5996 {
5997         return -1;
5998 }
5999
6000 uint16_t
6001 ixgbe_xmit_fixed_burst_vec(void __rte_unused *tx_queue,
6002                 struct rte_mbuf __rte_unused **tx_pkts,
6003                 uint16_t __rte_unused nb_pkts)
6004 {
6005         return 0;
6006 }
6007
6008 int
6009 ixgbe_txq_vec_setup(struct ixgbe_tx_queue __rte_unused *txq)
6010 {
6011         return -1;
6012 }
6013
6014 void
6015 ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue __rte_unused *rxq)
6016 {
6017         return;
6018 }
6019 #endif