4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _IXGBE_RXTX_H_
35 #define _IXGBE_RXTX_H_
38 #define RTE_PMD_IXGBE_TX_MAX_BURST 32
39 #define RTE_PMD_IXGBE_RX_MAX_BURST 32
41 #define RTE_IXGBE_DESCS_PER_LOOP 4
43 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
44 (uint64_t) ((mb)->buf_physaddr + (mb)->data_off)
46 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
47 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
49 #ifdef RTE_IXGBE_INC_VECTOR
50 #define RTE_IXGBE_VPMD_RX_BURST 32
51 #define RTE_IXGBE_VPMD_TX_BURST 32
52 #define RTE_IXGBE_RXQ_REARM_THRESH RTE_IXGBE_VPMD_RX_BURST
53 #define RTE_IXGBE_TX_MAX_FREE_BUF_SZ 64
56 #define RX_RING_SZ ((IXGBE_MAX_RING_DESC + RTE_IXGBE_DESCS_PER_LOOP - 1) * \
57 sizeof(union ixgbe_adv_rx_desc))
59 #ifdef RTE_PMD_PACKET_PREFETCH
60 #define rte_packet_prefetch(p) rte_prefetch1(p)
62 #define rte_packet_prefetch(p) do {} while(0)
65 #define RTE_IXGBE_REGISTER_POLL_WAIT_10_MS 10
66 #define RTE_IXGBE_WAIT_100_US 100
67 #define RTE_IXGBE_VMTXSW_REGISTER_COUNT 2
70 * Structure associated with each descriptor of the RX ring of a RX queue.
72 struct ixgbe_rx_entry {
73 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
76 struct ixgbe_scattered_rx_entry {
77 struct rte_mbuf *fbuf; /**< First segment of the fragmented packet. */
81 * Structure associated with each descriptor of the TX ring of a TX queue.
83 struct ixgbe_tx_entry {
84 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
85 uint16_t next_id; /**< Index of next descriptor in ring. */
86 uint16_t last_id; /**< Index of last scattered descriptor. */
90 * Structure associated with each descriptor of the TX ring of a TX queue.
92 struct ixgbe_tx_entry_v {
93 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
97 * Structure associated with each RX queue.
99 struct ixgbe_rx_queue {
100 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
101 volatile union ixgbe_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
102 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
103 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
104 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
105 struct ixgbe_rx_entry *sw_ring; /**< address of RX software ring. */
106 struct ixgbe_scattered_rx_entry *sw_sc_ring; /**< address of scattered Rx software ring. */
107 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
108 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
109 uint64_t mbuf_initializer; /**< value to init mbufs */
110 uint16_t nb_rx_desc; /**< number of RX descriptors. */
111 uint16_t rx_tail; /**< current value of RDT register. */
112 uint16_t nb_rx_hold; /**< number of held free RX desc. */
113 uint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */
114 uint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */
115 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
116 uint16_t rx_using_sse;
117 /**< indicates that vector RX is in use */
118 #ifdef RTE_IXGBE_INC_VECTOR
119 uint16_t rxrearm_nb; /**< number of remaining to be re-armed */
120 uint16_t rxrearm_start; /**< the idx we start the re-arming from */
122 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
123 uint16_t queue_id; /**< RX queue index. */
124 uint16_t reg_idx; /**< RX queue register index. */
125 uint8_t port_id; /**< Device port identifier. */
126 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
127 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
128 uint8_t rx_deferred_start; /**< not in global dev start. */
129 /** need to alloc dummy mbuf, for wraparound when scanning hw ring */
130 struct rte_mbuf fake_mbuf;
131 /** hold packets to return to application */
132 struct rte_mbuf *rx_stage[RTE_PMD_IXGBE_RX_MAX_BURST*2];
136 * IXGBE CTX Constants
138 enum ixgbe_advctx_num {
139 IXGBE_CTX_0 = 0, /**< CTX0 */
140 IXGBE_CTX_1 = 1, /**< CTX1 */
141 IXGBE_CTX_NUM = 2, /**< CTX NUMBER */
144 /** Offload features */
145 union ixgbe_tx_offload {
148 uint64_t l2_len:7; /**< L2 (MAC) Header Length. */
149 uint64_t l3_len:9; /**< L3 (IP) Header Length. */
150 uint64_t l4_len:8; /**< L4 (TCP/UDP) Header Length. */
151 uint64_t tso_segsz:16; /**< TCP TSO segment size */
152 uint64_t vlan_tci:16;
153 /**< VLAN Tag Control Identifier (CPU order). */
158 * Compare mask for vlan_macip_len.data,
159 * should be in sync with ixgbe_vlan_macip.f layout.
161 #define TX_VLAN_CMP_MASK 0xFFFF0000 /**< VLAN length - 16-bits. */
162 #define TX_MAC_LEN_CMP_MASK 0x0000FE00 /**< MAC length - 7-bits. */
163 #define TX_IP_LEN_CMP_MASK 0x000001FF /**< IP length - 9-bits. */
164 /** MAC+IP length. */
165 #define TX_MACIP_LEN_CMP_MASK (TX_MAC_LEN_CMP_MASK | TX_IP_LEN_CMP_MASK)
168 * Structure to check if new context need be built
171 struct ixgbe_advctx_info {
172 uint64_t flags; /**< ol_flags for context build. */
173 /**< tx offload: vlan, tso, l2-l3-l4 lengths. */
174 union ixgbe_tx_offload tx_offload;
175 /** compare mask for tx offload. */
176 union ixgbe_tx_offload tx_offload_mask;
180 * Structure associated with each TX queue.
182 struct ixgbe_tx_queue {
183 /** TX ring virtual address. */
184 volatile union ixgbe_adv_tx_desc *tx_ring;
185 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
187 struct ixgbe_tx_entry *sw_ring; /**< address of SW ring for scalar PMD. */
188 struct ixgbe_tx_entry_v *sw_ring_v; /**< address of SW ring for vector PMD */
190 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
191 uint16_t nb_tx_desc; /**< number of TX descriptors. */
192 uint16_t tx_tail; /**< current value of TDT reg. */
193 /**< Start freeing TX buffers if there are less free descriptors than
195 uint16_t tx_free_thresh;
196 /** Number of TX descriptors to use before RS bit is set. */
197 uint16_t tx_rs_thresh;
198 /** Number of TX descriptors used since RS bit was set. */
200 /** Index to last TX descriptor to have been cleaned. */
201 uint16_t last_desc_cleaned;
202 /** Total number of TX descriptors ready to be allocated. */
204 uint16_t tx_next_dd; /**< next desc to scan for DD bit */
205 uint16_t tx_next_rs; /**< next desc to set RS bit */
206 uint16_t queue_id; /**< TX queue index. */
207 uint16_t reg_idx; /**< TX queue register index. */
208 uint8_t port_id; /**< Device port identifier. */
209 uint8_t pthresh; /**< Prefetch threshold register. */
210 uint8_t hthresh; /**< Host threshold register. */
211 uint8_t wthresh; /**< Write-back threshold reg. */
212 uint32_t txq_flags; /**< Holds flags for this TXq */
213 uint32_t ctx_curr; /**< Hardware context states. */
214 /** Hardware context0 history. */
215 struct ixgbe_advctx_info ctx_cache[IXGBE_CTX_NUM];
216 const struct ixgbe_txq_ops *ops; /**< txq ops */
217 uint8_t tx_deferred_start; /**< not in global dev start. */
220 struct ixgbe_txq_ops {
221 void (*release_mbufs)(struct ixgbe_tx_queue *txq);
222 void (*free_swring)(struct ixgbe_tx_queue *txq);
223 void (*reset)(struct ixgbe_tx_queue *txq);
227 * The "simple" TX queue functions require that the following
228 * flags are set when the TX queue is configured:
229 * - ETH_TXQ_FLAGS_NOMULTSEGS
230 * - ETH_TXQ_FLAGS_NOVLANOFFL
231 * - ETH_TXQ_FLAGS_NOXSUMSCTP
232 * - ETH_TXQ_FLAGS_NOXSUMUDP
233 * - ETH_TXQ_FLAGS_NOXSUMTCP
234 * and that the RS bit threshold (tx_rs_thresh) is at least equal to
235 * RTE_PMD_IXGBE_TX_MAX_BURST.
237 #define IXGBE_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
238 ETH_TXQ_FLAGS_NOOFFLOADS)
241 * Populate descriptors with the following info:
242 * 1.) buffer_addr = phys_addr + headroom
243 * 2.) cmd_type_len = DCMD_DTYP_FLAGS | pkt_len
244 * 3.) olinfo_status = pkt_len << PAYLEN_SHIFT
247 /* Defines for Tx descriptor */
248 #define DCMD_DTYP_FLAGS (IXGBE_ADVTXD_DTYP_DATA |\
249 IXGBE_ADVTXD_DCMD_IFCS |\
250 IXGBE_ADVTXD_DCMD_DEXT |\
251 IXGBE_ADVTXD_DCMD_EOP)
254 /* Takes an ethdev and a queue and sets up the tx function to be used based on
255 * the queue parameters. Used in tx_queue_setup by primary process and then
256 * in dev_init by secondary process when attaching to an existing ethdev.
258 void ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq);
261 * Sets the rx_pkt_burst callback in the ixgbe rte_eth_dev instance.
263 * Sets the callback based on the device parameters:
264 * - ixgbe_hw.rx_bulk_alloc_allowed
265 * - rte_eth_dev_data.scattered_rx
266 * - rte_eth_dev_data.lro
267 * - conditions checked in ixgbe_rx_vec_condition_check()
269 * This means that the parameters above have to be configured prior to calling
272 * @dev rte_eth_dev handle
274 void ixgbe_set_rx_function(struct rte_eth_dev *dev);
276 uint16_t ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
278 uint16_t ixgbe_recv_scattered_pkts_vec(void *rx_queue,
279 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
280 int ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev);
281 int ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq);
282 void ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq);
284 #ifdef RTE_IXGBE_INC_VECTOR
286 uint16_t ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
288 int ixgbe_txq_vec_setup(struct ixgbe_tx_queue *txq);
290 #endif /* RTE_IXGBE_INC_VECTOR */
291 #endif /* _IXGBE_RXTX_H_ */