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34 #ifndef _IXGBE_RXTX_H_
35 #define _IXGBE_RXTX_H_
38 #define RTE_PMD_IXGBE_TX_MAX_BURST 32
39 #define RTE_PMD_IXGBE_RX_MAX_BURST 32
41 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
42 #define RTE_IXGBE_DESCS_PER_LOOP 4
43 #elif defined(RTE_IXGBE_INC_VECTOR)
44 #define RTE_IXGBE_DESCS_PER_LOOP 4
46 #define RTE_IXGBE_DESCS_PER_LOOP 1
49 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
50 (uint64_t) ((mb)->buf_physaddr + (mb)->data_off)
52 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
53 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
55 #ifdef RTE_IXGBE_INC_VECTOR
56 #define RTE_IXGBE_VPMD_RX_BURST 32
57 #define RTE_IXGBE_VPMD_TX_BURST 32
58 #define RTE_IXGBE_RXQ_REARM_THRESH RTE_IXGBE_VPMD_RX_BURST
59 #define RTE_IXGBE_TX_MAX_FREE_BUF_SZ 64
62 #define RX_RING_SZ ((IXGBE_MAX_RING_DESC + RTE_IXGBE_DESCS_PER_LOOP - 1) * \
63 sizeof(union ixgbe_adv_rx_desc))
65 #ifdef RTE_PMD_PACKET_PREFETCH
66 #define rte_packet_prefetch(p) rte_prefetch1(p)
68 #define rte_packet_prefetch(p) do {} while(0)
71 #define RTE_IXGBE_REGISTER_POLL_WAIT_10_MS 10
72 #define RTE_IXGBE_WAIT_100_US 100
73 #define RTE_IXGBE_VMTXSW_REGISTER_COUNT 2
76 * Structure associated with each descriptor of the RX ring of a RX queue.
78 struct ixgbe_rx_entry {
79 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
82 struct ixgbe_scattered_rx_entry {
83 struct rte_mbuf *fbuf; /**< First segment of the fragmented packet. */
87 * Structure associated with each descriptor of the TX ring of a TX queue.
89 struct ixgbe_tx_entry {
90 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
91 uint16_t next_id; /**< Index of next descriptor in ring. */
92 uint16_t last_id; /**< Index of last scattered descriptor. */
96 * Structure associated with each descriptor of the TX ring of a TX queue.
98 struct ixgbe_tx_entry_v {
99 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
103 * Structure associated with each RX queue.
105 struct ixgbe_rx_queue {
106 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
107 volatile union ixgbe_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
108 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
109 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
110 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
111 struct ixgbe_rx_entry *sw_ring; /**< address of RX software ring. */
112 struct ixgbe_scattered_rx_entry *sw_sc_ring; /**< address of scattered Rx software ring. */
113 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
114 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
115 uint64_t mbuf_initializer; /**< value to init mbufs */
116 uint16_t nb_rx_desc; /**< number of RX descriptors. */
117 uint16_t rx_tail; /**< current value of RDT register. */
118 uint16_t nb_rx_hold; /**< number of held free RX desc. */
119 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
120 uint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */
121 uint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */
122 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
124 uint16_t rx_using_sse;
125 /**< indicates that vector RX is in use */
126 #ifdef RTE_IXGBE_INC_VECTOR
127 uint16_t rxrearm_nb; /**< number of remaining to be re-armed */
128 uint16_t rxrearm_start; /**< the idx we start the re-arming from */
130 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
131 uint16_t queue_id; /**< RX queue index. */
132 uint16_t reg_idx; /**< RX queue register index. */
133 uint8_t port_id; /**< Device port identifier. */
134 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
135 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
136 uint8_t rx_deferred_start; /**< not in global dev start. */
137 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
138 /** need to alloc dummy mbuf, for wraparound when scanning hw ring */
139 struct rte_mbuf fake_mbuf;
140 /** hold packets to return to application */
141 struct rte_mbuf *rx_stage[RTE_PMD_IXGBE_RX_MAX_BURST*2];
146 * IXGBE CTX Constants
148 enum ixgbe_advctx_num {
149 IXGBE_CTX_0 = 0, /**< CTX0 */
150 IXGBE_CTX_1 = 1, /**< CTX1 */
151 IXGBE_CTX_NUM = 2, /**< CTX NUMBER */
154 /** Offload features */
155 union ixgbe_tx_offload {
158 uint64_t l2_len:7; /**< L2 (MAC) Header Length. */
159 uint64_t l3_len:9; /**< L3 (IP) Header Length. */
160 uint64_t l4_len:8; /**< L4 (TCP/UDP) Header Length. */
161 uint64_t tso_segsz:16; /**< TCP TSO segment size */
162 uint64_t vlan_tci:16;
163 /**< VLAN Tag Control Identifier (CPU order). */
168 * Compare mask for vlan_macip_len.data,
169 * should be in sync with ixgbe_vlan_macip.f layout.
171 #define TX_VLAN_CMP_MASK 0xFFFF0000 /**< VLAN length - 16-bits. */
172 #define TX_MAC_LEN_CMP_MASK 0x0000FE00 /**< MAC length - 7-bits. */
173 #define TX_IP_LEN_CMP_MASK 0x000001FF /**< IP length - 9-bits. */
174 /** MAC+IP length. */
175 #define TX_MACIP_LEN_CMP_MASK (TX_MAC_LEN_CMP_MASK | TX_IP_LEN_CMP_MASK)
178 * Structure to check if new context need be built
181 struct ixgbe_advctx_info {
182 uint64_t flags; /**< ol_flags for context build. */
183 /**< tx offload: vlan, tso, l2-l3-l4 lengths. */
184 union ixgbe_tx_offload tx_offload;
185 /** compare mask for tx offload. */
186 union ixgbe_tx_offload tx_offload_mask;
190 * Structure associated with each TX queue.
192 struct ixgbe_tx_queue {
193 /** TX ring virtual address. */
194 volatile union ixgbe_adv_tx_desc *tx_ring;
195 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
196 struct ixgbe_tx_entry *sw_ring; /**< virtual address of SW ring. */
197 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
198 uint16_t nb_tx_desc; /**< number of TX descriptors. */
199 uint16_t tx_tail; /**< current value of TDT reg. */
200 /**< Start freeing TX buffers if there are less free descriptors than
202 uint16_t tx_free_thresh;
203 /** Number of TX descriptors to use before RS bit is set. */
204 uint16_t tx_rs_thresh;
205 /** Number of TX descriptors used since RS bit was set. */
207 /** Index to last TX descriptor to have been cleaned. */
208 uint16_t last_desc_cleaned;
209 /** Total number of TX descriptors ready to be allocated. */
211 uint16_t tx_next_dd; /**< next desc to scan for DD bit */
212 uint16_t tx_next_rs; /**< next desc to set RS bit */
213 uint16_t queue_id; /**< TX queue index. */
214 uint16_t reg_idx; /**< TX queue register index. */
215 uint8_t port_id; /**< Device port identifier. */
216 uint8_t pthresh; /**< Prefetch threshold register. */
217 uint8_t hthresh; /**< Host threshold register. */
218 uint8_t wthresh; /**< Write-back threshold reg. */
219 uint32_t txq_flags; /**< Holds flags for this TXq */
220 uint32_t ctx_curr; /**< Hardware context states. */
221 /** Hardware context0 history. */
222 struct ixgbe_advctx_info ctx_cache[IXGBE_CTX_NUM];
223 const struct ixgbe_txq_ops *ops; /**< txq ops */
224 uint8_t tx_deferred_start; /**< not in global dev start. */
227 struct ixgbe_txq_ops {
228 void (*release_mbufs)(struct ixgbe_tx_queue *txq);
229 void (*free_swring)(struct ixgbe_tx_queue *txq);
230 void (*reset)(struct ixgbe_tx_queue *txq);
234 * The "simple" TX queue functions require that the following
235 * flags are set when the TX queue is configured:
236 * - ETH_TXQ_FLAGS_NOMULTSEGS
237 * - ETH_TXQ_FLAGS_NOVLANOFFL
238 * - ETH_TXQ_FLAGS_NOXSUMSCTP
239 * - ETH_TXQ_FLAGS_NOXSUMUDP
240 * - ETH_TXQ_FLAGS_NOXSUMTCP
241 * and that the RS bit threshold (tx_rs_thresh) is at least equal to
242 * RTE_PMD_IXGBE_TX_MAX_BURST.
244 #define IXGBE_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
245 ETH_TXQ_FLAGS_NOOFFLOADS)
248 * Populate descriptors with the following info:
249 * 1.) buffer_addr = phys_addr + headroom
250 * 2.) cmd_type_len = DCMD_DTYP_FLAGS | pkt_len
251 * 3.) olinfo_status = pkt_len << PAYLEN_SHIFT
254 /* Defines for Tx descriptor */
255 #define DCMD_DTYP_FLAGS (IXGBE_ADVTXD_DTYP_DATA |\
256 IXGBE_ADVTXD_DCMD_IFCS |\
257 IXGBE_ADVTXD_DCMD_DEXT |\
258 IXGBE_ADVTXD_DCMD_EOP)
261 /* Takes an ethdev and a queue and sets up the tx function to be used based on
262 * the queue parameters. Used in tx_queue_setup by primary process and then
263 * in dev_init by secondary process when attaching to an existing ethdev.
265 void ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq);
268 * Sets the rx_pkt_burst callback in the ixgbe rte_eth_dev instance.
270 * Sets the callback based on the device parameters:
271 * - ixgbe_hw.rx_bulk_alloc_allowed
272 * - rte_eth_dev_data.scattered_rx
273 * - rte_eth_dev_data.lro
274 * - conditions checked in ixgbe_rx_vec_condition_check()
276 * This means that the parameters above have to be configured prior to calling
279 * @dev rte_eth_dev handle
281 void ixgbe_set_rx_function(struct rte_eth_dev *dev);
283 uint16_t ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
285 uint16_t ixgbe_recv_scattered_pkts_vec(void *rx_queue,
286 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
287 int ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev);
288 int ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq);
289 void ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq);
291 #ifdef RTE_IXGBE_INC_VECTOR
293 uint16_t ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
295 int ixgbe_txq_vec_setup(struct ixgbe_tx_queue *txq);
297 #endif /* RTE_IXGBE_INC_VECTOR */
298 #endif /* _IXGBE_RXTX_H_ */