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35 #include <rte_ethdev.h>
36 #include <rte_malloc.h>
38 #include "ixgbe_ethdev.h"
39 #include "ixgbe_rxtx.h"
41 #include <tmmintrin.h>
43 #ifndef __INTEL_COMPILER
44 #pragma GCC diagnostic ignored "-Wcast-qual"
48 ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq)
52 volatile union ixgbe_adv_rx_desc *rxdp;
53 struct ixgbe_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
54 struct rte_mbuf *mb0, *mb1;
55 __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
56 RTE_PKTMBUF_HEADROOM);
57 __m128i dma_addr0, dma_addr1;
59 rxdp = rxq->rx_ring + rxq->rxrearm_start;
61 /* Pull 'n' more MBUFs into the software ring */
62 if (rte_mempool_get_bulk(rxq->mb_pool,
64 RTE_IXGBE_RXQ_REARM_THRESH) < 0) {
65 if (rxq->rxrearm_nb + RTE_IXGBE_RXQ_REARM_THRESH >=
67 dma_addr0 = _mm_setzero_si128();
68 for (i = 0; i < RTE_IXGBE_DESCS_PER_LOOP; i++) {
69 rxep[i].mbuf = &rxq->fake_mbuf;
70 _mm_store_si128((__m128i *)&rxdp[i].read,
74 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
75 RTE_IXGBE_RXQ_REARM_THRESH;
79 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
80 for (i = 0; i < RTE_IXGBE_RXQ_REARM_THRESH; i += 2, rxep += 2) {
81 __m128i vaddr0, vaddr1;
88 * Flush mbuf with pkt template.
89 * Data to be rearmed is 6 bytes long.
90 * Though, RX will overwrite ol_flags that are coming next
91 * anyway. So overwrite whole 8 bytes with one load:
92 * 6 bytes of rearm_data plus first 2 bytes of ol_flags.
94 p0 = (uintptr_t)&mb0->rearm_data;
95 *(uint64_t *)p0 = rxq->mbuf_initializer;
96 p1 = (uintptr_t)&mb1->rearm_data;
97 *(uint64_t *)p1 = rxq->mbuf_initializer;
99 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
100 vaddr0 = _mm_loadu_si128((__m128i *)&(mb0->buf_addr));
101 vaddr1 = _mm_loadu_si128((__m128i *)&(mb1->buf_addr));
103 /* convert pa to dma_addr hdr/data */
104 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
105 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
107 /* add headroom to pa values */
108 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
109 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
111 /* flush desc with pa dma_addr */
112 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
113 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
116 rxq->rxrearm_start += RTE_IXGBE_RXQ_REARM_THRESH;
117 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
118 rxq->rxrearm_start = 0;
120 rxq->rxrearm_nb -= RTE_IXGBE_RXQ_REARM_THRESH;
122 rx_id = (uint16_t) ((rxq->rxrearm_start == 0) ?
123 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
125 /* Update the tail pointer on the NIC */
126 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
129 /* Handling the offload flags (olflags) field takes computation
130 * time when receiving packets. Therefore we provide a flag to disable
131 * the processing of the olflags field when they are not needed. This
132 * gives improved performance, at the cost of losing the offload info
133 * in the received packet
135 #ifdef RTE_IXGBE_RX_OLFLAGS_ENABLE
138 #define OLFLAGS_MASK_V (((uint64_t)PKT_RX_VLAN_PKT << 48) | \
139 ((uint64_t)PKT_RX_VLAN_PKT << 32) | \
140 ((uint64_t)PKT_RX_VLAN_PKT << 16) | \
141 ((uint64_t)PKT_RX_VLAN_PKT))
143 #define OLFLAGS_MASK ((uint16_t)(PKT_RX_VLAN_PKT | PKT_RX_IPV4_HDR |\
144 PKT_RX_IPV4_HDR_EXT | PKT_RX_IPV6_HDR |\
145 PKT_RX_IPV6_HDR_EXT))
146 #define OLFLAGS_MASK_V (((uint64_t)OLFLAGS_MASK << 48) | \
147 ((uint64_t)OLFLAGS_MASK << 32) | \
148 ((uint64_t)OLFLAGS_MASK << 16) | \
149 ((uint64_t)OLFLAGS_MASK))
150 #define PTYPE_SHIFT (1)
151 #endif /* RTE_NEXT_ABI */
153 #define VTAG_SHIFT (3)
156 desc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
159 __m128i vtag0, vtag1;
165 vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
166 vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
167 vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
168 vtag1 = _mm_srli_epi16(vtag1, VTAG_SHIFT);
169 vol.dword = _mm_cvtsi128_si64(vtag1) & OLFLAGS_MASK_V;
171 __m128i ptype0, ptype1, vtag0, vtag1;
177 ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
178 ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
179 vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
180 vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
182 ptype1 = _mm_unpacklo_epi32(ptype0, ptype1);
183 vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
185 ptype1 = _mm_slli_epi16(ptype1, PTYPE_SHIFT);
186 vtag1 = _mm_srli_epi16(vtag1, VTAG_SHIFT);
188 ptype1 = _mm_or_si128(ptype1, vtag1);
189 vol.dword = _mm_cvtsi128_si64(ptype1) & OLFLAGS_MASK_V;
190 #endif /* RTE_NEXT_ABI */
192 rx_pkts[0]->ol_flags = vol.e[0];
193 rx_pkts[1]->ol_flags = vol.e[1];
194 rx_pkts[2]->ol_flags = vol.e[2];
195 rx_pkts[3]->ol_flags = vol.e[3];
198 #define desc_to_olflags_v(desc, rx_pkts) do {} while (0)
202 * vPMD receive routine, now only accept (nb_pkts == RTE_IXGBE_VPMD_RX_BURST)
206 * - nb_pkts < RTE_IXGBE_VPMD_RX_BURST, just return no packet
207 * - nb_pkts > RTE_IXGBE_VPMD_RX_BURST, only scan RTE_IXGBE_VPMD_RX_BURST
209 * - don't support ol_flags for rss and csum err
211 static inline uint16_t
212 _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
213 uint16_t nb_pkts, uint8_t *split_packet)
215 volatile union ixgbe_adv_rx_desc *rxdp;
216 struct ixgbe_rx_entry *sw_ring;
217 uint16_t nb_pkts_recd;
222 __m128i crc_adjust = _mm_set_epi16(
223 0, 0, 0, /* ignore non-length fields */
224 -rxq->crc_len, /* sub crc on data_len */
225 0, /* ignore high-16bits of pkt_len */
226 -rxq->crc_len, /* sub crc on pkt_len */
227 0, 0 /* ignore pkt_type field */
229 __m128i dd_check, eop_check;
230 __m128i desc_mask = _mm_set_epi32(0xFFFFFFFF, 0xFFFFFFFF,
231 0xFFFFFFFF, 0xFFFF07F0);
233 __m128i crc_adjust = _mm_set_epi16(
234 0, 0, 0, 0, /* ignore non-length fields */
235 0, /* ignore high-16bits of pkt_len */
236 -rxq->crc_len, /* sub crc on pkt_len */
237 -rxq->crc_len, /* sub crc on data_len */
238 0 /* ignore pkt_type field */
240 __m128i dd_check, eop_check;
241 #endif /* RTE_NEXT_ABI */
243 if (unlikely(nb_pkts < RTE_IXGBE_VPMD_RX_BURST))
246 /* Just the act of getting into the function from the application is
247 * going to cost about 7 cycles */
248 rxdp = rxq->rx_ring + rxq->rx_tail;
250 _mm_prefetch((const void *)rxdp, _MM_HINT_T0);
252 /* See if we need to rearm the RX queue - gives the prefetch a bit
254 if (rxq->rxrearm_nb > RTE_IXGBE_RXQ_REARM_THRESH)
255 ixgbe_rxq_rearm(rxq);
257 /* Before we start moving massive data around, check to see if
258 * there is actually a packet available */
259 if (!(rxdp->wb.upper.status_error &
260 rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
263 /* 4 packets DD mask */
264 dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
266 /* 4 packets EOP mask */
267 eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
269 /* mask to shuffle from desc. to mbuf */
271 shuf_msk = _mm_set_epi8(
272 7, 6, 5, 4, /* octet 4~7, 32bits rss */
273 15, 14, /* octet 14~15, low 16 bits vlan_macip */
274 13, 12, /* octet 12~13, 16 bits data_len */
275 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
276 13, 12, /* octet 12~13, low 16 bits pkt_len */
277 0xFF, 0xFF, /* skip high 16 bits pkt_type */
278 1, /* octet 1, 8 bits pkt_type field */
279 0 /* octet 0, 4 bits offset 4 pkt_type field */
282 shuf_msk = _mm_set_epi8(
283 7, 6, 5, 4, /* octet 4~7, 32bits rss */
284 0xFF, 0xFF, /* skip high 16 bits vlan_macip, zero out */
285 15, 14, /* octet 14~15, low 16 bits vlan_macip */
286 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
287 13, 12, /* octet 12~13, low 16 bits pkt_len */
288 13, 12, /* octet 12~13, 16 bits data_len */
289 0xFF, 0xFF /* skip pkt_type field */
291 #endif /* RTE_NEXT_ABI */
293 /* Cache is empty -> need to scan the buffer rings, but first move
294 * the next 'n' mbufs into the cache */
295 sw_ring = &rxq->sw_ring[rxq->rx_tail];
298 /* A. load 4 packet in one loop
299 * [A*. mask out 4 unused dirty field in desc]
300 * B. copy 4 mbuf point from swring to rx_pkts
301 * C. calc the number of DD bits among the 4 packets
302 * [C*. extract the end-of-packet bit, if requested]
303 * D. fill info. from desc to mbuf
306 /* A. load 4 packet in one loop
307 * B. copy 4 mbuf point from swring to rx_pkts
308 * C. calc the number of DD bits among the 4 packets
309 * [C*. extract the end-of-packet bit, if requested]
310 * D. fill info. from desc to mbuf
312 #endif /* RTE_NEXT_ABI */
313 for (pos = 0, nb_pkts_recd = 0; pos < RTE_IXGBE_VPMD_RX_BURST;
314 pos += RTE_IXGBE_DESCS_PER_LOOP,
315 rxdp += RTE_IXGBE_DESCS_PER_LOOP) {
316 __m128i descs[RTE_IXGBE_DESCS_PER_LOOP];
317 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
318 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
319 __m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */
322 rte_prefetch0(&rx_pkts[pos]->cacheline1);
323 rte_prefetch0(&rx_pkts[pos + 1]->cacheline1);
324 rte_prefetch0(&rx_pkts[pos + 2]->cacheline1);
325 rte_prefetch0(&rx_pkts[pos + 3]->cacheline1);
328 /* B.1 load 1 mbuf point */
329 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
331 /* Read desc statuses backwards to avoid race condition */
332 /* A.1 load 4 pkts desc */
333 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
335 /* B.2 copy 2 mbuf point into rx_pkts */
336 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
338 /* B.1 load 1 mbuf point */
339 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
341 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
342 /* B.1 load 2 mbuf point */
343 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
344 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
346 /* B.2 copy 2 mbuf point into rx_pkts */
347 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
350 /* A* mask out 0~3 bits RSS type */
351 descs[3] = _mm_and_si128(descs[3], desc_mask);
352 descs[2] = _mm_and_si128(descs[2], desc_mask);
354 /* A* mask out 0~3 bits RSS type */
355 descs[1] = _mm_and_si128(descs[1], desc_mask);
356 descs[0] = _mm_and_si128(descs[0], desc_mask);
357 #endif /* RTE_NEXT_ABI */
359 /* avoid compiler reorder optimization */
360 rte_compiler_barrier();
362 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
363 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
364 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
366 /* C.1 4=>2 filter staterr info only */
367 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
368 /* C.1 4=>2 filter staterr info only */
369 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
372 /* set ol_flags with vlan packet type */
374 /* set ol_flags with packet type and vlan tag */
375 #endif /* RTE_NEXT_ABI */
376 desc_to_olflags_v(descs, &rx_pkts[pos]);
378 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
379 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
380 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
382 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
383 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
384 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
386 /* C.2 get 4 pkts staterr value */
387 zero = _mm_xor_si128(dd_check, dd_check);
388 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
390 /* D.3 copy final 3,4 data to rx_pkts */
391 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
393 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
396 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
397 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
398 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
400 /* C* extract and record EOP bit */
402 __m128i eop_shuf_mask = _mm_set_epi8(
403 0xFF, 0xFF, 0xFF, 0xFF,
404 0xFF, 0xFF, 0xFF, 0xFF,
405 0xFF, 0xFF, 0xFF, 0xFF,
406 0x04, 0x0C, 0x00, 0x08
409 /* and with mask to extract bits, flipping 1-0 */
410 __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
411 /* the staterr values are not in order, as the count
412 * count of dd bits doesn't care. However, for end of
413 * packet tracking, we do care, so shuffle. This also
414 * compresses the 32-bit values to 8-bit */
415 eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
416 /* store the resulting 32-bit value */
417 *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
418 split_packet += RTE_IXGBE_DESCS_PER_LOOP;
420 /* zero-out next pointers */
421 rx_pkts[pos]->next = NULL;
422 rx_pkts[pos + 1]->next = NULL;
423 rx_pkts[pos + 2]->next = NULL;
424 rx_pkts[pos + 3]->next = NULL;
427 /* C.3 calc available number of desc */
428 staterr = _mm_and_si128(staterr, dd_check);
429 staterr = _mm_packs_epi32(staterr, zero);
431 /* D.3 copy final 1,2 data to rx_pkts */
432 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
434 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
437 /* C.4 calc avaialbe number of desc */
438 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
440 if (likely(var != RTE_IXGBE_DESCS_PER_LOOP))
444 /* Update our internal tail pointer */
445 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
446 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
447 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
453 * vPMD receive routine, now only accept (nb_pkts == RTE_IXGBE_VPMD_RX_BURST)
457 * - nb_pkts < RTE_IXGBE_VPMD_RX_BURST, just return no packet
458 * - nb_pkts > RTE_IXGBE_VPMD_RX_BURST, only scan RTE_IXGBE_VPMD_RX_BURST
460 * - don't support ol_flags for rss and csum err
463 ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
466 return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
469 static inline uint16_t
470 reassemble_packets(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_bufs,
471 uint16_t nb_bufs, uint8_t *split_flags)
473 struct rte_mbuf *pkts[RTE_IXGBE_VPMD_RX_BURST]; /*finished pkts*/
474 struct rte_mbuf *start = rxq->pkt_first_seg;
475 struct rte_mbuf *end = rxq->pkt_last_seg;
476 unsigned pkt_idx, buf_idx;
479 for (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {
481 /* processing a split packet */
482 end->next = rx_bufs[buf_idx];
483 rx_bufs[buf_idx]->data_len += rxq->crc_len;
486 start->pkt_len += rx_bufs[buf_idx]->data_len;
489 if (!split_flags[buf_idx]) {
490 /* it's the last packet of the set */
491 start->hash = end->hash;
492 start->ol_flags = end->ol_flags;
493 /* we need to strip crc for the whole packet */
494 start->pkt_len -= rxq->crc_len;
495 if (end->data_len > rxq->crc_len)
496 end->data_len -= rxq->crc_len;
498 /* free up last mbuf */
499 struct rte_mbuf *secondlast = start;
502 while (secondlast->next != end)
503 secondlast = secondlast->next;
504 secondlast->data_len -= (rxq->crc_len -
506 secondlast->next = NULL;
507 rte_pktmbuf_free_seg(end);
510 pkts[pkt_idx++] = start;
514 /* not processing a split packet */
515 if (!split_flags[buf_idx]) {
516 /* not a split packet, save and skip */
517 pkts[pkt_idx++] = rx_bufs[buf_idx];
520 end = start = rx_bufs[buf_idx];
521 rx_bufs[buf_idx]->data_len += rxq->crc_len;
522 rx_bufs[buf_idx]->pkt_len += rxq->crc_len;
526 /* save the partial packet for next time */
527 rxq->pkt_first_seg = start;
528 rxq->pkt_last_seg = end;
529 memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
534 * vPMD receive routine that reassembles scattered packets
537 * - don't support ol_flags for rss and csum err
538 * - now only accept (nb_pkts == RTE_IXGBE_VPMD_RX_BURST)
541 ixgbe_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
544 struct ixgbe_rx_queue *rxq = rx_queue;
545 uint8_t split_flags[RTE_IXGBE_VPMD_RX_BURST] = {0};
547 /* get some new buffers */
548 uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
553 /* happy day case, full burst + no packets to be joined */
554 const uint64_t *split_fl64 = (uint64_t *)split_flags;
555 if (rxq->pkt_first_seg == NULL &&
556 split_fl64[0] == 0 && split_fl64[1] == 0 &&
557 split_fl64[2] == 0 && split_fl64[3] == 0)
560 /* reassemble any packets that need reassembly*/
562 if (rxq->pkt_first_seg == NULL) {
563 /* find the first split flag, and only reassemble then*/
564 while (i < nb_bufs && !split_flags[i])
569 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
574 vtx1(volatile union ixgbe_adv_tx_desc *txdp,
575 struct rte_mbuf *pkt, uint64_t flags)
577 __m128i descriptor = _mm_set_epi64x((uint64_t)pkt->pkt_len << 46 |
578 flags | pkt->data_len,
579 pkt->buf_physaddr + pkt->data_off);
580 _mm_store_si128((__m128i *)&txdp->read, descriptor);
584 vtx(volatile union ixgbe_adv_tx_desc *txdp,
585 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
588 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
589 vtx1(txdp, *pkt, flags);
592 static inline int __attribute__((always_inline))
593 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
595 struct ixgbe_tx_entry_v *txep;
600 struct rte_mbuf *m, *free[RTE_IXGBE_TX_MAX_FREE_BUF_SZ];
602 /* check DD bit on threshold descriptor */
603 status = txq->tx_ring[txq->tx_next_dd].wb.status;
604 if (!(status & IXGBE_ADVTXD_STAT_DD))
607 n = txq->tx_rs_thresh;
610 * first buffer to free from S/W ring is at index
611 * tx_next_dd - (tx_rs_thresh-1)
613 txep = &txq->sw_ring_v[txq->tx_next_dd - (n - 1)];
614 m = __rte_pktmbuf_prefree_seg(txep[0].mbuf);
615 if (likely(m != NULL)) {
618 for (i = 1; i < n; i++) {
619 m = __rte_pktmbuf_prefree_seg(txep[i].mbuf);
620 if (likely(m != NULL)) {
621 if (likely(m->pool == free[0]->pool))
624 rte_mempool_put_bulk(free[0]->pool,
625 (void *)free, nb_free);
631 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
633 for (i = 1; i < n; i++) {
634 m = __rte_pktmbuf_prefree_seg(txep[i].mbuf);
636 rte_mempool_put(m->pool, m);
640 /* buffers were freed, update counters */
641 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
642 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
643 if (txq->tx_next_dd >= txq->nb_tx_desc)
644 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
646 return txq->tx_rs_thresh;
649 static inline void __attribute__((always_inline))
650 tx_backlog_entry(struct ixgbe_tx_entry_v *txep,
651 struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
654 for (i = 0; i < (int)nb_pkts; ++i)
655 txep[i].mbuf = tx_pkts[i];
659 ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
662 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
663 volatile union ixgbe_adv_tx_desc *txdp;
664 struct ixgbe_tx_entry_v *txep;
665 uint16_t n, nb_commit, tx_id;
666 uint64_t flags = DCMD_DTYP_FLAGS;
667 uint64_t rs = IXGBE_ADVTXD_DCMD_RS|DCMD_DTYP_FLAGS;
670 if (unlikely(nb_pkts > RTE_IXGBE_VPMD_TX_BURST))
671 nb_pkts = RTE_IXGBE_VPMD_TX_BURST;
673 if (txq->nb_tx_free < txq->tx_free_thresh)
674 ixgbe_tx_free_bufs(txq);
676 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
677 if (unlikely(nb_pkts == 0))
680 tx_id = txq->tx_tail;
681 txdp = &txq->tx_ring[tx_id];
682 txep = &txq->sw_ring_v[tx_id];
684 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
686 n = (uint16_t)(txq->nb_tx_desc - tx_id);
687 if (nb_commit >= n) {
689 tx_backlog_entry(txep, tx_pkts, n);
691 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
692 vtx1(txdp, *tx_pkts, flags);
694 vtx1(txdp, *tx_pkts++, rs);
696 nb_commit = (uint16_t)(nb_commit - n);
699 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
701 /* avoid reach the end of ring */
702 txdp = &(txq->tx_ring[tx_id]);
703 txep = &txq->sw_ring_v[tx_id];
706 tx_backlog_entry(txep, tx_pkts, nb_commit);
708 vtx(txdp, tx_pkts, nb_commit, flags);
710 tx_id = (uint16_t)(tx_id + nb_commit);
711 if (tx_id > txq->tx_next_rs) {
712 txq->tx_ring[txq->tx_next_rs].read.cmd_type_len |=
713 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
714 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
718 txq->tx_tail = tx_id;
720 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
725 static void __attribute__((cold))
726 ixgbe_tx_queue_release_mbufs_vec(struct ixgbe_tx_queue *txq)
729 struct ixgbe_tx_entry_v *txe;
730 const uint16_t max_desc = (uint16_t)(txq->nb_tx_desc - 1);
732 if (txq->sw_ring == NULL || txq->nb_tx_free == max_desc)
735 /* release the used mbufs in sw_ring */
736 for (i = txq->tx_next_dd - (txq->tx_rs_thresh - 1);
738 i = (i + 1) & max_desc) {
739 txe = &txq->sw_ring_v[i];
740 rte_pktmbuf_free_seg(txe->mbuf);
742 txq->nb_tx_free = max_desc;
745 for (i = 0; i < txq->nb_tx_desc; i++) {
746 txe = &txq->sw_ring_v[i];
751 void __attribute__((cold))
752 ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq)
754 const unsigned mask = rxq->nb_rx_desc - 1;
757 if (rxq->sw_ring == NULL || rxq->rxrearm_nb >= rxq->nb_rx_desc)
760 /* free all mbufs that are valid in the ring */
761 for (i = rxq->rx_tail; i != rxq->rxrearm_start; i = (i + 1) & mask)
762 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
763 rxq->rxrearm_nb = rxq->nb_rx_desc;
765 /* set all entries to NULL */
766 memset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_rx_desc);
769 static void __attribute__((cold))
770 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
775 if (txq->sw_ring != NULL) {
776 rte_free(txq->sw_ring_v - 1);
777 txq->sw_ring_v = NULL;
781 static void __attribute__((cold))
782 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
784 static const union ixgbe_adv_tx_desc zeroed_desc = {{0}};
785 struct ixgbe_tx_entry_v *txe = txq->sw_ring_v;
788 /* Zero out HW ring memory */
789 for (i = 0; i < txq->nb_tx_desc; i++)
790 txq->tx_ring[i] = zeroed_desc;
792 /* Initialize SW ring entries */
793 for (i = 0; i < txq->nb_tx_desc; i++) {
794 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
795 txd->wb.status = IXGBE_TXD_STAT_DD;
799 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
800 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
805 * Always allow 1 descriptor to be un-allocated to avoid
806 * a H/W race condition
808 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
809 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
811 memset((void *)&txq->ctx_cache, 0,
812 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
815 static const struct ixgbe_txq_ops vec_txq_ops = {
816 .release_mbufs = ixgbe_tx_queue_release_mbufs_vec,
817 .free_swring = ixgbe_tx_free_swring,
818 .reset = ixgbe_reset_tx_queue,
821 int __attribute__((cold))
822 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq)
825 struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
828 mb_def.data_off = RTE_PKTMBUF_HEADROOM;
829 mb_def.port = rxq->port_id;
830 rte_mbuf_refcnt_set(&mb_def, 1);
832 /* prevent compiler reordering: rearm_data covers previous fields */
833 rte_compiler_barrier();
834 p = (uintptr_t)&mb_def.rearm_data;
835 rxq->mbuf_initializer = *(uint64_t *)p;
839 int __attribute__((cold))
840 ixgbe_txq_vec_setup(struct ixgbe_tx_queue *txq)
842 if (txq->sw_ring_v == NULL)
845 /* leave the first one for overflow */
846 txq->sw_ring_v = txq->sw_ring_v + 1;
847 txq->ops = &vec_txq_ops;
852 int __attribute__((cold))
853 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
855 #ifndef RTE_LIBRTE_IEEE1588
856 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
857 struct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;
859 #ifndef RTE_IXGBE_RX_OLFLAGS_ENABLE
860 /* whithout rx ol_flags, no VP flag report */
861 if (rxmode->hw_vlan_strip != 0 ||
862 rxmode->hw_vlan_extend != 0)
866 /* no fdir support */
867 if (fconf->mode != RTE_FDIR_MODE_NONE)
871 * - no csum error report support
872 * - no header split support
874 if (rxmode->hw_ip_checksum == 1 ||
875 rxmode->header_split == 1)