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35 #include <rte_ethdev.h>
36 #include <rte_malloc.h>
38 #include "ixgbe_ethdev.h"
39 #include "ixgbe_rxtx.h"
40 #include "ixgbe_rxtx_vec_common.h"
44 #pragma GCC diagnostic ignored "-Wcast-qual"
47 ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq)
51 volatile union ixgbe_adv_rx_desc *rxdp;
52 struct ixgbe_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
53 struct rte_mbuf *mb0, *mb1;
54 uint64x2_t dma_addr0, dma_addr1;
55 uint64x2_t zero = vdupq_n_u64(0);
59 rxdp = rxq->rx_ring + rxq->rxrearm_start;
61 /* Pull 'n' more MBUFs into the software ring */
62 if (unlikely(rte_mempool_get_bulk(rxq->mb_pool,
64 RTE_IXGBE_RXQ_REARM_THRESH) < 0)) {
65 if (rxq->rxrearm_nb + RTE_IXGBE_RXQ_REARM_THRESH >=
67 for (i = 0; i < RTE_IXGBE_DESCS_PER_LOOP; i++) {
68 rxep[i].mbuf = &rxq->fake_mbuf;
69 vst1q_u64((uint64_t *)&rxdp[i].read,
73 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
74 RTE_IXGBE_RXQ_REARM_THRESH;
78 p = vld1_u8((uint8_t *)&rxq->mbuf_initializer);
80 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
81 for (i = 0; i < RTE_IXGBE_RXQ_REARM_THRESH; i += 2, rxep += 2) {
86 * Flush mbuf with pkt template.
87 * Data to be rearmed is 6 bytes long.
89 vst1_u8((uint8_t *)&mb0->rearm_data, p);
90 paddr = mb0->buf_physaddr + RTE_PKTMBUF_HEADROOM;
91 dma_addr0 = vsetq_lane_u64(paddr, zero, 0);
92 /* flush desc with pa dma_addr */
93 vst1q_u64((uint64_t *)&rxdp++->read, dma_addr0);
95 vst1_u8((uint8_t *)&mb1->rearm_data, p);
96 paddr = mb1->buf_physaddr + RTE_PKTMBUF_HEADROOM;
97 dma_addr1 = vsetq_lane_u64(paddr, zero, 0);
98 vst1q_u64((uint64_t *)&rxdp++->read, dma_addr1);
101 rxq->rxrearm_start += RTE_IXGBE_RXQ_REARM_THRESH;
102 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
103 rxq->rxrearm_start = 0;
105 rxq->rxrearm_nb -= RTE_IXGBE_RXQ_REARM_THRESH;
107 rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
108 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
110 /* Update the tail pointer on the NIC */
111 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
114 #define VTAG_SHIFT (3)
117 desc_to_olflags_v(uint8x16x2_t sterr_tmp1, uint8x16x2_t sterr_tmp2,
118 uint8x16_t staterr, struct rte_mbuf **rx_pkts)
128 const uint8x16_t pkttype_msk = {
129 PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT,
130 PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT,
131 0x00, 0x00, 0x00, 0x00,
132 0x00, 0x00, 0x00, 0x00,
133 0x00, 0x00, 0x00, 0x00};
135 const uint8x16_t rsstype_msk = {
136 0x0F, 0x0F, 0x0F, 0x0F,
137 0x00, 0x00, 0x00, 0x00,
138 0x00, 0x00, 0x00, 0x00,
139 0x00, 0x00, 0x00, 0x00};
141 const uint8x16_t rss_flags = {
142 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
143 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
144 PKT_RX_RSS_HASH, 0, 0, 0,
145 0, 0, 0, PKT_RX_FDIR};
147 ptype = vzipq_u8(sterr_tmp1.val[0], sterr_tmp2.val[0]).val[0];
148 ptype = vandq_u8(ptype, rsstype_msk);
149 ptype = vqtbl1q_u8(rss_flags, ptype);
151 vtag = vshrq_n_u8(staterr, VTAG_SHIFT);
152 vtag = vandq_u8(vtag, pkttype_msk);
153 vtag = vorrq_u8(ptype, vtag);
155 vol.word = vgetq_lane_u32(vreinterpretq_u32_u8(vtag), 0);
157 rx_pkts[0]->ol_flags = vol.e[0];
158 rx_pkts[1]->ol_flags = vol.e[1];
159 rx_pkts[2]->ol_flags = vol.e[2];
160 rx_pkts[3]->ol_flags = vol.e[3];
164 * vPMD raw receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP)
167 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
168 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
170 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
171 * - don't support ol_flags for rss and csum err
174 #define IXGBE_VPMD_DESC_DD_MASK 0x01010101
175 #define IXGBE_VPMD_DESC_EOP_MASK 0x02020202
177 static inline uint16_t
178 _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
179 uint16_t nb_pkts, uint8_t *split_packet)
181 volatile union ixgbe_adv_rx_desc *rxdp;
182 struct ixgbe_rx_entry *sw_ring;
183 uint16_t nb_pkts_recd;
185 uint8x16_t shuf_msk = {
187 0xFF, 0xFF, /* skip 32 bits pkt_type */
188 12, 13, /* octet 12~13, low 16 bits pkt_len */
189 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
190 12, 13, /* octet 12~13, 16 bits data_len */
191 14, 15, /* octet 14~15, low 16 bits vlan_macip */
192 4, 5, 6, 7 /* octet 4~7, 32bits rss */
194 uint16x8_t crc_adjust = {0, 0, rxq->crc_len, 0,
195 rxq->crc_len, 0, 0, 0};
197 /* nb_pkts shall be less equal than RTE_IXGBE_MAX_RX_BURST */
198 nb_pkts = RTE_MIN(nb_pkts, RTE_IXGBE_MAX_RX_BURST);
200 /* nb_pkts has to be floor-aligned to RTE_IXGBE_DESCS_PER_LOOP */
201 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_IXGBE_DESCS_PER_LOOP);
203 /* Just the act of getting into the function from the application is
204 * going to cost about 7 cycles
206 rxdp = rxq->rx_ring + rxq->rx_tail;
208 rte_prefetch_non_temporal(rxdp);
210 /* See if we need to rearm the RX queue - gives the prefetch a bit
213 if (rxq->rxrearm_nb > RTE_IXGBE_RXQ_REARM_THRESH)
214 ixgbe_rxq_rearm(rxq);
216 /* Before we start moving massive data around, check to see if
217 * there is actually a packet available
219 if (!(rxdp->wb.upper.status_error &
220 rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
223 /* Cache is empty -> need to scan the buffer rings, but first move
224 * the next 'n' mbufs into the cache
226 sw_ring = &rxq->sw_ring[rxq->rx_tail];
228 /* A. load 4 packet in one loop
229 * B. copy 4 mbuf point from swring to rx_pkts
230 * C. calc the number of DD bits among the 4 packets
231 * [C*. extract the end-of-packet bit, if requested]
232 * D. fill info. from desc to mbuf
234 for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
235 pos += RTE_IXGBE_DESCS_PER_LOOP,
236 rxdp += RTE_IXGBE_DESCS_PER_LOOP) {
237 uint64x2_t descs[RTE_IXGBE_DESCS_PER_LOOP];
238 uint8x16_t pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
239 uint8x16x2_t sterr_tmp1, sterr_tmp2;
240 uint64x2_t mbp1, mbp2;
246 /* B.1 load 1 mbuf point */
247 mbp1 = vld1q_u64((uint64_t *)&sw_ring[pos]);
249 /* B.2 copy 2 mbuf point into rx_pkts */
250 vst1q_u64((uint64_t *)&rx_pkts[pos], mbp1);
252 /* B.1 load 1 mbuf point */
253 mbp2 = vld1q_u64((uint64_t *)&sw_ring[pos + 2]);
255 /* A. load 4 pkts descs */
256 descs[0] = vld1q_u64((uint64_t *)(rxdp));
257 descs[1] = vld1q_u64((uint64_t *)(rxdp + 1));
258 descs[2] = vld1q_u64((uint64_t *)(rxdp + 2));
259 descs[3] = vld1q_u64((uint64_t *)(rxdp + 3));
262 /* B.2 copy 2 mbuf point into rx_pkts */
263 vst1q_u64((uint64_t *)&rx_pkts[pos + 2], mbp2);
266 rte_mbuf_prefetch_part2(rx_pkts[pos]);
267 rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
268 rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
269 rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
272 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
273 pkt_mb4 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[3]), shuf_msk);
274 pkt_mb3 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[2]), shuf_msk);
276 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
277 pkt_mb2 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[1]), shuf_msk);
278 pkt_mb1 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[0]), shuf_msk);
280 /* C.1 4=>2 filter staterr info only */
281 sterr_tmp2 = vzipq_u8(vreinterpretq_u8_u64(descs[1]),
282 vreinterpretq_u8_u64(descs[3]));
283 /* C.1 4=>2 filter staterr info only */
284 sterr_tmp1 = vzipq_u8(vreinterpretq_u8_u64(descs[0]),
285 vreinterpretq_u8_u64(descs[2]));
287 /* C.2 get 4 pkts staterr value */
288 staterr = vzipq_u8(sterr_tmp1.val[1], sterr_tmp2.val[1]).val[0];
289 stat = vgetq_lane_u32(vreinterpretq_u32_u8(staterr), 0);
291 /* set ol_flags with vlan packet type */
292 desc_to_olflags_v(sterr_tmp1, sterr_tmp2, staterr,
295 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
296 tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb4), crc_adjust);
297 pkt_mb4 = vreinterpretq_u8_u16(tmp);
298 tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb3), crc_adjust);
299 pkt_mb3 = vreinterpretq_u8_u16(tmp);
301 /* D.3 copy final 3,4 data to rx_pkts */
302 vst1q_u8((void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,
304 vst1q_u8((void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,
307 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
308 tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb2), crc_adjust);
309 pkt_mb2 = vreinterpretq_u8_u16(tmp);
310 tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb1), crc_adjust);
311 pkt_mb1 = vreinterpretq_u8_u16(tmp);
313 /* C* extract and record EOP bit */
315 /* and with mask to extract bits, flipping 1-0 */
316 *(int *)split_packet = ~stat & IXGBE_VPMD_DESC_EOP_MASK;
318 split_packet += RTE_IXGBE_DESCS_PER_LOOP;
321 rte_prefetch_non_temporal(rxdp + RTE_IXGBE_DESCS_PER_LOOP);
323 /* D.3 copy final 1,2 data to rx_pkts */
324 vst1q_u8((uint8_t *)&rx_pkts[pos + 1]->rx_descriptor_fields1,
326 vst1q_u8((uint8_t *)&rx_pkts[pos]->rx_descriptor_fields1,
329 stat &= IXGBE_VPMD_DESC_DD_MASK;
331 /* C.4 calc avaialbe number of desc */
332 if (likely(stat != IXGBE_VPMD_DESC_DD_MASK)) {
333 while (stat & 0x01) {
340 nb_pkts_recd += RTE_IXGBE_DESCS_PER_LOOP;
344 /* Update our internal tail pointer */
345 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
346 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
347 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
353 * vPMD receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP)
356 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
357 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
359 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
360 * - don't support ol_flags for rss and csum err
363 ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
366 return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
370 * vPMD receive routine that reassembles scattered packets
373 * - don't support ol_flags for rss and csum err
374 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
375 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
377 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
380 ixgbe_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
383 struct ixgbe_rx_queue *rxq = rx_queue;
384 uint8_t split_flags[RTE_IXGBE_MAX_RX_BURST] = {0};
386 /* get some new buffers */
387 uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
392 /* happy day case, full burst + no packets to be joined */
393 const uint64_t *split_fl64 = (uint64_t *)split_flags;
394 if (rxq->pkt_first_seg == NULL &&
395 split_fl64[0] == 0 && split_fl64[1] == 0 &&
396 split_fl64[2] == 0 && split_fl64[3] == 0)
399 /* reassemble any packets that need reassembly*/
401 if (rxq->pkt_first_seg == NULL) {
402 /* find the first split flag, and only reassemble then*/
403 while (i < nb_bufs && !split_flags[i])
408 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
413 vtx1(volatile union ixgbe_adv_tx_desc *txdp,
414 struct rte_mbuf *pkt, uint64_t flags)
416 uint64x2_t descriptor = {
417 pkt->buf_physaddr + pkt->data_off,
418 (uint64_t)pkt->pkt_len << 46 | flags | pkt->data_len};
420 vst1q_u64((uint64_t *)&txdp->read, descriptor);
424 vtx(volatile union ixgbe_adv_tx_desc *txdp,
425 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
429 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
430 vtx1(txdp, *pkt, flags);
434 ixgbe_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
437 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
438 volatile union ixgbe_adv_tx_desc *txdp;
439 struct ixgbe_tx_entry_v *txep;
440 uint16_t n, nb_commit, tx_id;
441 uint64_t flags = DCMD_DTYP_FLAGS;
442 uint64_t rs = IXGBE_ADVTXD_DCMD_RS | DCMD_DTYP_FLAGS;
445 /* cross rx_thresh boundary is not allowed */
446 nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
448 if (txq->nb_tx_free < txq->tx_free_thresh)
449 ixgbe_tx_free_bufs(txq);
451 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
452 if (unlikely(nb_pkts == 0))
455 tx_id = txq->tx_tail;
456 txdp = &txq->tx_ring[tx_id];
457 txep = &txq->sw_ring_v[tx_id];
459 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
461 n = (uint16_t)(txq->nb_tx_desc - tx_id);
462 if (nb_commit >= n) {
463 tx_backlog_entry(txep, tx_pkts, n);
465 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
466 vtx1(txdp, *tx_pkts, flags);
468 vtx1(txdp, *tx_pkts++, rs);
470 nb_commit = (uint16_t)(nb_commit - n);
473 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
475 /* avoid reach the end of ring */
476 txdp = &txq->tx_ring[tx_id];
477 txep = &txq->sw_ring_v[tx_id];
480 tx_backlog_entry(txep, tx_pkts, nb_commit);
482 vtx(txdp, tx_pkts, nb_commit, flags);
484 tx_id = (uint16_t)(tx_id + nb_commit);
485 if (tx_id > txq->tx_next_rs) {
486 txq->tx_ring[txq->tx_next_rs].read.cmd_type_len |=
487 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
488 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
492 txq->tx_tail = tx_id;
494 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
499 static void __attribute__((cold))
500 ixgbe_tx_queue_release_mbufs_vec(struct ixgbe_tx_queue *txq)
502 _ixgbe_tx_queue_release_mbufs_vec(txq);
505 void __attribute__((cold))
506 ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq)
508 _ixgbe_rx_queue_release_mbufs_vec(rxq);
511 static void __attribute__((cold))
512 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
514 _ixgbe_tx_free_swring_vec(txq);
517 static void __attribute__((cold))
518 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
520 _ixgbe_reset_tx_queue_vec(txq);
523 static const struct ixgbe_txq_ops vec_txq_ops = {
524 .release_mbufs = ixgbe_tx_queue_release_mbufs_vec,
525 .free_swring = ixgbe_tx_free_swring,
526 .reset = ixgbe_reset_tx_queue,
529 int __attribute__((cold))
530 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq)
532 return ixgbe_rxq_vec_setup_default(rxq);
535 int __attribute__((cold))
536 ixgbe_txq_vec_setup(struct ixgbe_tx_queue *txq)
538 return ixgbe_txq_vec_setup_default(txq, &vec_txq_ops);
541 int __attribute__((cold))
542 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
544 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
546 /* no csum error report support */
547 if (rxmode->hw_ip_checksum == 1)
550 return ixgbe_rx_vec_dev_conf_condition_check_default(dev);