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35 #include <rte_ethdev.h>
36 #include <rte_malloc.h>
38 #include "ixgbe_ethdev.h"
39 #include "ixgbe_rxtx.h"
40 #include "ixgbe_rxtx_vec_common.h"
42 #include <tmmintrin.h>
44 #ifndef __INTEL_COMPILER
45 #pragma GCC diagnostic ignored "-Wcast-qual"
49 ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq)
53 volatile union ixgbe_adv_rx_desc *rxdp;
54 struct ixgbe_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
55 struct rte_mbuf *mb0, *mb1;
56 __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
57 RTE_PKTMBUF_HEADROOM);
58 __m128i dma_addr0, dma_addr1;
60 const __m128i hba_msk = _mm_set_epi64x(0, UINT64_MAX);
62 rxdp = rxq->rx_ring + rxq->rxrearm_start;
64 /* Pull 'n' more MBUFs into the software ring */
65 if (rte_mempool_get_bulk(rxq->mb_pool,
67 RTE_IXGBE_RXQ_REARM_THRESH) < 0) {
68 if (rxq->rxrearm_nb + RTE_IXGBE_RXQ_REARM_THRESH >=
70 dma_addr0 = _mm_setzero_si128();
71 for (i = 0; i < RTE_IXGBE_DESCS_PER_LOOP; i++) {
72 rxep[i].mbuf = &rxq->fake_mbuf;
73 _mm_store_si128((__m128i *)&rxdp[i].read,
77 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
78 RTE_IXGBE_RXQ_REARM_THRESH;
82 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
83 for (i = 0; i < RTE_IXGBE_RXQ_REARM_THRESH; i += 2, rxep += 2) {
84 __m128i vaddr0, vaddr1;
91 * Flush mbuf with pkt template.
92 * Data to be rearmed is 6 bytes long.
93 * Though, RX will overwrite ol_flags that are coming next
94 * anyway. So overwrite whole 8 bytes with one load:
95 * 6 bytes of rearm_data plus first 2 bytes of ol_flags.
97 p0 = (uintptr_t)&mb0->rearm_data;
98 *(uint64_t *)p0 = rxq->mbuf_initializer;
99 p1 = (uintptr_t)&mb1->rearm_data;
100 *(uint64_t *)p1 = rxq->mbuf_initializer;
102 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
103 vaddr0 = _mm_loadu_si128((__m128i *)&(mb0->buf_addr));
104 vaddr1 = _mm_loadu_si128((__m128i *)&(mb1->buf_addr));
106 /* convert pa to dma_addr hdr/data */
107 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
108 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
110 /* add headroom to pa values */
111 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
112 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
114 /* set Header Buffer Address to zero */
115 dma_addr0 = _mm_and_si128(dma_addr0, hba_msk);
116 dma_addr1 = _mm_and_si128(dma_addr1, hba_msk);
118 /* flush desc with pa dma_addr */
119 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
120 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
123 rxq->rxrearm_start += RTE_IXGBE_RXQ_REARM_THRESH;
124 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
125 rxq->rxrearm_start = 0;
127 rxq->rxrearm_nb -= RTE_IXGBE_RXQ_REARM_THRESH;
129 rx_id = (uint16_t) ((rxq->rxrearm_start == 0) ?
130 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
132 /* Update the tail pointer on the NIC */
133 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
136 /* Handling the offload flags (olflags) field takes computation
137 * time when receiving packets. Therefore we provide a flag to disable
138 * the processing of the olflags field when they are not needed. This
139 * gives improved performance, at the cost of losing the offload info
140 * in the received packet
142 #ifdef RTE_IXGBE_RX_OLFLAGS_ENABLE
145 desc_to_olflags_v(__m128i descs[4], uint8_t vlan_flags,
146 struct rte_mbuf **rx_pkts)
148 __m128i ptype0, ptype1, vtag0, vtag1;
154 /* mask everything except rss type */
155 const __m128i rsstype_msk = _mm_set_epi16(
156 0x0000, 0x0000, 0x0000, 0x0000,
157 0x000F, 0x000F, 0x000F, 0x000F);
159 /* map rss type to rss hash flag */
160 const __m128i rss_flags = _mm_set_epi8(PKT_RX_FDIR, 0, 0, 0,
161 0, 0, 0, PKT_RX_RSS_HASH,
162 PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0,
163 PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, 0);
165 /* mask everything except vlan present bit */
166 const __m128i vlan_msk = _mm_set_epi16(
169 IXGBE_RXD_STAT_VP, IXGBE_RXD_STAT_VP,
170 IXGBE_RXD_STAT_VP, IXGBE_RXD_STAT_VP);
171 /* map vlan present (0x8) to ol_flags */
172 const __m128i vlan_map = _mm_set_epi8(
178 ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
179 ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
180 vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
181 vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
183 ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
184 ptype0 = _mm_and_si128(ptype0, rsstype_msk);
185 ptype0 = _mm_shuffle_epi8(rss_flags, ptype0);
187 vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
188 vtag1 = _mm_and_si128(vtag1, vlan_msk);
189 vtag1 = _mm_shuffle_epi8(vlan_map, vtag1);
191 vtag1 = _mm_or_si128(ptype0, vtag1);
192 vol.dword = _mm_cvtsi128_si64(vtag1);
194 rx_pkts[0]->ol_flags = vol.e[0];
195 rx_pkts[1]->ol_flags = vol.e[1];
196 rx_pkts[2]->ol_flags = vol.e[2];
197 rx_pkts[3]->ol_flags = vol.e[3];
200 #define desc_to_olflags_v(desc, vlan_flags, rx_pkts) do { \
201 RTE_SET_USED(vlan_flags); \
206 * vPMD raw receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP)
209 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
210 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
212 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
213 * - don't support ol_flags for rss and csum err
215 static inline uint16_t
216 _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
217 uint16_t nb_pkts, uint8_t *split_packet)
219 volatile union ixgbe_adv_rx_desc *rxdp;
220 struct ixgbe_rx_entry *sw_ring;
221 uint16_t nb_pkts_recd;
225 __m128i crc_adjust = _mm_set_epi16(
226 0, 0, 0, /* ignore non-length fields */
227 -rxq->crc_len, /* sub crc on data_len */
228 0, /* ignore high-16bits of pkt_len */
229 -rxq->crc_len, /* sub crc on pkt_len */
230 0, 0 /* ignore pkt_type field */
232 __m128i dd_check, eop_check;
235 /* nb_pkts shall be less equal than RTE_IXGBE_MAX_RX_BURST */
236 nb_pkts = RTE_MIN(nb_pkts, RTE_IXGBE_MAX_RX_BURST);
238 /* nb_pkts has to be floor-aligned to RTE_IXGBE_DESCS_PER_LOOP */
239 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_IXGBE_DESCS_PER_LOOP);
241 /* Just the act of getting into the function from the application is
242 * going to cost about 7 cycles
244 rxdp = rxq->rx_ring + rxq->rx_tail;
248 /* See if we need to rearm the RX queue - gives the prefetch a bit
251 if (rxq->rxrearm_nb > RTE_IXGBE_RXQ_REARM_THRESH)
252 ixgbe_rxq_rearm(rxq);
254 /* Before we start moving massive data around, check to see if
255 * there is actually a packet available
257 if (!(rxdp->wb.upper.status_error &
258 rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
261 /* 4 packets DD mask */
262 dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
264 /* 4 packets EOP mask */
265 eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
267 /* mask to shuffle from desc. to mbuf */
268 shuf_msk = _mm_set_epi8(
269 7, 6, 5, 4, /* octet 4~7, 32bits rss */
270 15, 14, /* octet 14~15, low 16 bits vlan_macip */
271 13, 12, /* octet 12~13, 16 bits data_len */
272 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
273 13, 12, /* octet 12~13, low 16 bits pkt_len */
274 0xFF, 0xFF, /* skip 32 bit pkt_type */
278 /* Cache is empty -> need to scan the buffer rings, but first move
279 * the next 'n' mbufs into the cache
281 sw_ring = &rxq->sw_ring[rxq->rx_tail];
283 /* ensure these 2 flags are in the lower 8 bits */
284 RTE_BUILD_BUG_ON((PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED) > UINT8_MAX);
285 vlan_flags = rxq->vlan_flags & UINT8_MAX;
287 /* A. load 4 packet in one loop
288 * [A*. mask out 4 unused dirty field in desc]
289 * B. copy 4 mbuf point from swring to rx_pkts
290 * C. calc the number of DD bits among the 4 packets
291 * [C*. extract the end-of-packet bit, if requested]
292 * D. fill info. from desc to mbuf
294 for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
295 pos += RTE_IXGBE_DESCS_PER_LOOP,
296 rxdp += RTE_IXGBE_DESCS_PER_LOOP) {
297 __m128i descs[RTE_IXGBE_DESCS_PER_LOOP];
298 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
299 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
300 __m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */
302 /* B.1 load 1 mbuf point */
303 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
305 /* Read desc statuses backwards to avoid race condition */
306 /* A.1 load 4 pkts desc */
307 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
309 /* B.2 copy 2 mbuf point into rx_pkts */
310 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
312 /* B.1 load 1 mbuf point */
313 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
315 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
316 /* B.1 load 2 mbuf point */
317 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
318 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
320 /* B.2 copy 2 mbuf point into rx_pkts */
321 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
324 rte_mbuf_prefetch_part2(rx_pkts[pos]);
325 rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
326 rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
327 rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
330 /* avoid compiler reorder optimization */
331 rte_compiler_barrier();
333 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
334 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
335 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
337 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
338 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
339 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
341 /* C.1 4=>2 filter staterr info only */
342 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
343 /* C.1 4=>2 filter staterr info only */
344 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
346 /* set ol_flags with vlan packet type */
347 desc_to_olflags_v(descs, vlan_flags, &rx_pkts[pos]);
349 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
350 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
351 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
353 /* C.2 get 4 pkts staterr value */
354 zero = _mm_xor_si128(dd_check, dd_check);
355 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
357 /* D.3 copy final 3,4 data to rx_pkts */
358 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
360 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
363 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
364 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
365 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
367 /* C* extract and record EOP bit */
369 __m128i eop_shuf_mask = _mm_set_epi8(
370 0xFF, 0xFF, 0xFF, 0xFF,
371 0xFF, 0xFF, 0xFF, 0xFF,
372 0xFF, 0xFF, 0xFF, 0xFF,
373 0x04, 0x0C, 0x00, 0x08
376 /* and with mask to extract bits, flipping 1-0 */
377 __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
378 /* the staterr values are not in order, as the count
379 * count of dd bits doesn't care. However, for end of
380 * packet tracking, we do care, so shuffle. This also
381 * compresses the 32-bit values to 8-bit
383 eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
384 /* store the resulting 32-bit value */
385 *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
386 split_packet += RTE_IXGBE_DESCS_PER_LOOP;
388 /* zero-out next pointers */
389 rx_pkts[pos]->next = NULL;
390 rx_pkts[pos + 1]->next = NULL;
391 rx_pkts[pos + 2]->next = NULL;
392 rx_pkts[pos + 3]->next = NULL;
395 /* C.3 calc available number of desc */
396 staterr = _mm_and_si128(staterr, dd_check);
397 staterr = _mm_packs_epi32(staterr, zero);
399 /* D.3 copy final 1,2 data to rx_pkts */
400 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
402 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
405 /* C.4 calc avaialbe number of desc */
406 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
408 if (likely(var != RTE_IXGBE_DESCS_PER_LOOP))
412 /* Update our internal tail pointer */
413 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
414 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
415 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
421 * vPMD receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP)
424 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
425 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
427 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
428 * - don't support ol_flags for rss and csum err
431 ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
434 return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
438 * vPMD receive routine that reassembles scattered packets
441 * - don't support ol_flags for rss and csum err
442 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
443 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
445 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
448 ixgbe_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
451 struct ixgbe_rx_queue *rxq = rx_queue;
452 uint8_t split_flags[RTE_IXGBE_MAX_RX_BURST] = {0};
454 /* get some new buffers */
455 uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
460 /* happy day case, full burst + no packets to be joined */
461 const uint64_t *split_fl64 = (uint64_t *)split_flags;
462 if (rxq->pkt_first_seg == NULL &&
463 split_fl64[0] == 0 && split_fl64[1] == 0 &&
464 split_fl64[2] == 0 && split_fl64[3] == 0)
467 /* reassemble any packets that need reassembly*/
469 if (rxq->pkt_first_seg == NULL) {
470 /* find the first split flag, and only reassemble then*/
471 while (i < nb_bufs && !split_flags[i])
476 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
481 vtx1(volatile union ixgbe_adv_tx_desc *txdp,
482 struct rte_mbuf *pkt, uint64_t flags)
484 __m128i descriptor = _mm_set_epi64x((uint64_t)pkt->pkt_len << 46 |
485 flags | pkt->data_len,
486 pkt->buf_physaddr + pkt->data_off);
487 _mm_store_si128((__m128i *)&txdp->read, descriptor);
491 vtx(volatile union ixgbe_adv_tx_desc *txdp,
492 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
496 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
497 vtx1(txdp, *pkt, flags);
501 ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
504 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
505 volatile union ixgbe_adv_tx_desc *txdp;
506 struct ixgbe_tx_entry_v *txep;
507 uint16_t n, nb_commit, tx_id;
508 uint64_t flags = DCMD_DTYP_FLAGS;
509 uint64_t rs = IXGBE_ADVTXD_DCMD_RS|DCMD_DTYP_FLAGS;
512 /* cross rx_thresh boundary is not allowed */
513 nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
515 if (txq->nb_tx_free < txq->tx_free_thresh)
516 ixgbe_tx_free_bufs(txq);
518 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
519 if (unlikely(nb_pkts == 0))
522 tx_id = txq->tx_tail;
523 txdp = &txq->tx_ring[tx_id];
524 txep = &txq->sw_ring_v[tx_id];
526 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
528 n = (uint16_t)(txq->nb_tx_desc - tx_id);
529 if (nb_commit >= n) {
531 tx_backlog_entry(txep, tx_pkts, n);
533 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
534 vtx1(txdp, *tx_pkts, flags);
536 vtx1(txdp, *tx_pkts++, rs);
538 nb_commit = (uint16_t)(nb_commit - n);
541 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
543 /* avoid reach the end of ring */
544 txdp = &(txq->tx_ring[tx_id]);
545 txep = &txq->sw_ring_v[tx_id];
548 tx_backlog_entry(txep, tx_pkts, nb_commit);
550 vtx(txdp, tx_pkts, nb_commit, flags);
552 tx_id = (uint16_t)(tx_id + nb_commit);
553 if (tx_id > txq->tx_next_rs) {
554 txq->tx_ring[txq->tx_next_rs].read.cmd_type_len |=
555 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
556 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
560 txq->tx_tail = tx_id;
562 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
567 static void __attribute__((cold))
568 ixgbe_tx_queue_release_mbufs_vec(struct ixgbe_tx_queue *txq)
570 _ixgbe_tx_queue_release_mbufs_vec(txq);
573 void __attribute__((cold))
574 ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq)
576 _ixgbe_rx_queue_release_mbufs_vec(rxq);
579 static void __attribute__((cold))
580 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
582 _ixgbe_tx_free_swring_vec(txq);
585 static void __attribute__((cold))
586 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
588 _ixgbe_reset_tx_queue_vec(txq);
591 static const struct ixgbe_txq_ops vec_txq_ops = {
592 .release_mbufs = ixgbe_tx_queue_release_mbufs_vec,
593 .free_swring = ixgbe_tx_free_swring,
594 .reset = ixgbe_reset_tx_queue,
597 int __attribute__((cold))
598 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq)
600 return ixgbe_rxq_vec_setup_default(rxq);
603 int __attribute__((cold))
604 ixgbe_txq_vec_setup(struct ixgbe_tx_queue *txq)
606 return ixgbe_txq_vec_setup_default(txq, &vec_txq_ops);
609 int __attribute__((cold))
610 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
612 return ixgbe_rx_vec_dev_conf_condition_check_default(dev);