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35 #include <rte_ethdev.h>
36 #include <rte_malloc.h>
38 #include "ixgbe_ethdev.h"
39 #include "ixgbe_rxtx.h"
40 #include "ixgbe_rxtx_vec_common.h"
42 #include <tmmintrin.h>
44 #ifndef __INTEL_COMPILER
45 #pragma GCC diagnostic ignored "-Wcast-qual"
49 ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq)
53 volatile union ixgbe_adv_rx_desc *rxdp;
54 struct ixgbe_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
55 struct rte_mbuf *mb0, *mb1;
56 __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
57 RTE_PKTMBUF_HEADROOM);
58 __m128i dma_addr0, dma_addr1;
60 const __m128i hba_msk = _mm_set_epi64x(0, UINT64_MAX);
62 rxdp = rxq->rx_ring + rxq->rxrearm_start;
64 /* Pull 'n' more MBUFs into the software ring */
65 if (rte_mempool_get_bulk(rxq->mb_pool,
67 RTE_IXGBE_RXQ_REARM_THRESH) < 0) {
68 if (rxq->rxrearm_nb + RTE_IXGBE_RXQ_REARM_THRESH >=
70 dma_addr0 = _mm_setzero_si128();
71 for (i = 0; i < RTE_IXGBE_DESCS_PER_LOOP; i++) {
72 rxep[i].mbuf = &rxq->fake_mbuf;
73 _mm_store_si128((__m128i *)&rxdp[i].read,
77 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
78 RTE_IXGBE_RXQ_REARM_THRESH;
82 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
83 for (i = 0; i < RTE_IXGBE_RXQ_REARM_THRESH; i += 2, rxep += 2) {
84 __m128i vaddr0, vaddr1;
89 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
90 vaddr0 = _mm_loadu_si128((__m128i *)&(mb0->buf_addr));
91 vaddr1 = _mm_loadu_si128((__m128i *)&(mb1->buf_addr));
93 /* convert pa to dma_addr hdr/data */
94 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
95 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
97 /* add headroom to pa values */
98 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
99 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
101 /* set Header Buffer Address to zero */
102 dma_addr0 = _mm_and_si128(dma_addr0, hba_msk);
103 dma_addr1 = _mm_and_si128(dma_addr1, hba_msk);
105 /* flush desc with pa dma_addr */
106 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
107 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
110 rxq->rxrearm_start += RTE_IXGBE_RXQ_REARM_THRESH;
111 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
112 rxq->rxrearm_start = 0;
114 rxq->rxrearm_nb -= RTE_IXGBE_RXQ_REARM_THRESH;
116 rx_id = (uint16_t) ((rxq->rxrearm_start == 0) ?
117 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
119 /* Update the tail pointer on the NIC */
120 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
124 desc_to_olflags_v(__m128i descs[4], __m128i mbuf_init, uint8_t vlan_flags,
125 struct rte_mbuf **rx_pkts)
127 __m128i ptype0, ptype1, vtag0, vtag1, csum;
128 __m128i rearm0, rearm1, rearm2, rearm3;
130 /* mask everything except rss type */
131 const __m128i rsstype_msk = _mm_set_epi16(
132 0x0000, 0x0000, 0x0000, 0x0000,
133 0x000F, 0x000F, 0x000F, 0x000F);
135 /* mask the lower byte of ol_flags */
136 const __m128i ol_flags_msk = _mm_set_epi16(
137 0x0000, 0x0000, 0x0000, 0x0000,
138 0x00FF, 0x00FF, 0x00FF, 0x00FF);
140 /* map rss type to rss hash flag */
141 const __m128i rss_flags = _mm_set_epi8(PKT_RX_FDIR, 0, 0, 0,
142 0, 0, 0, PKT_RX_RSS_HASH,
143 PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0,
144 PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, 0);
146 /* mask everything except vlan present and l4/ip csum error */
147 const __m128i vlan_csum_msk = _mm_set_epi16(
148 (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
149 (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
150 (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
151 (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
152 IXGBE_RXD_STAT_VP, IXGBE_RXD_STAT_VP,
153 IXGBE_RXD_STAT_VP, IXGBE_RXD_STAT_VP);
154 /* map vlan present (0x8), IPE (0x2), L4E (0x1) to ol_flags */
155 const __m128i vlan_csum_map_lo = _mm_set_epi8(
157 vlan_flags | PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD,
158 vlan_flags | PKT_RX_IP_CKSUM_BAD,
159 vlan_flags | PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
160 vlan_flags | PKT_RX_IP_CKSUM_GOOD,
162 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD,
164 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
165 PKT_RX_IP_CKSUM_GOOD);
167 const __m128i vlan_csum_map_hi = _mm_set_epi8(
169 0, PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t), 0,
170 PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t),
172 0, PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t), 0,
173 PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t));
175 ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
176 ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
177 vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
178 vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
180 ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
181 ptype0 = _mm_and_si128(ptype0, rsstype_msk);
182 ptype0 = _mm_shuffle_epi8(rss_flags, ptype0);
184 vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
185 vtag1 = _mm_and_si128(vtag1, vlan_csum_msk);
187 /* csum bits are in the most significant, to use shuffle we need to
188 * shift them. Change mask to 0xc000 to 0x0003.
190 csum = _mm_srli_epi16(vtag1, 14);
192 /* now or the most significant 64 bits containing the checksum
193 * flags with the vlan present flags.
195 csum = _mm_srli_si128(csum, 8);
196 vtag1 = _mm_or_si128(csum, vtag1);
198 /* convert VP, IPE, L4E to ol_flags */
199 vtag0 = _mm_shuffle_epi8(vlan_csum_map_hi, vtag1);
200 vtag0 = _mm_slli_epi16(vtag0, sizeof(uint8_t));
202 vtag1 = _mm_shuffle_epi8(vlan_csum_map_lo, vtag1);
203 vtag1 = _mm_and_si128(vtag1, ol_flags_msk);
204 vtag1 = _mm_or_si128(vtag0, vtag1);
206 vtag1 = _mm_or_si128(ptype0, vtag1);
209 * At this point, we have the 4 sets of flags in the low 64-bits
211 * We want to extract these, and merge them with the mbuf init data
212 * so we can do a single 16-byte write to the mbuf to set the flags
213 * and all the other initialization fields. Extracting the
214 * appropriate flags means that we have to do a shift and blend for
215 * each mbuf before we do the write.
217 #ifdef RTE_MACHINE_CPUFLAG_SSE4_2
219 rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 8), 0x10);
220 rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 6), 0x10);
221 rearm2 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 4), 0x10);
222 rearm3 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 2), 0x10);
225 rearm0 = _mm_slli_si128(vtag1, 14);
226 rearm1 = _mm_slli_si128(vtag1, 12);
227 rearm2 = _mm_slli_si128(vtag1, 10);
228 rearm3 = _mm_slli_si128(vtag1, 8);
230 rearm0 = _mm_or_si128(mbuf_init, _mm_srli_epi64(rearm0, 48));
231 rearm1 = _mm_or_si128(mbuf_init, _mm_srli_epi64(rearm1, 48));
232 rearm2 = _mm_or_si128(mbuf_init, _mm_srli_epi64(rearm2, 48));
233 rearm3 = _mm_or_si128(mbuf_init, _mm_srli_epi64(rearm3, 48));
235 #endif /* RTE_MACHINE_CPUFLAG_SSE4_2 */
237 _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);
238 _mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);
239 _mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);
240 _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);
244 * vPMD raw receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP)
247 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
248 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
250 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
252 static inline uint16_t
253 _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
254 uint16_t nb_pkts, uint8_t *split_packet)
256 volatile union ixgbe_adv_rx_desc *rxdp;
257 struct ixgbe_rx_entry *sw_ring;
258 uint16_t nb_pkts_recd;
262 __m128i crc_adjust = _mm_set_epi16(
263 0, 0, 0, /* ignore non-length fields */
264 -rxq->crc_len, /* sub crc on data_len */
265 0, /* ignore high-16bits of pkt_len */
266 -rxq->crc_len, /* sub crc on pkt_len */
267 0, 0 /* ignore pkt_type field */
269 __m128i dd_check, eop_check;
273 /* nb_pkts shall be less equal than RTE_IXGBE_MAX_RX_BURST */
274 nb_pkts = RTE_MIN(nb_pkts, RTE_IXGBE_MAX_RX_BURST);
276 /* nb_pkts has to be floor-aligned to RTE_IXGBE_DESCS_PER_LOOP */
277 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_IXGBE_DESCS_PER_LOOP);
279 /* Just the act of getting into the function from the application is
280 * going to cost about 7 cycles
282 rxdp = rxq->rx_ring + rxq->rx_tail;
286 /* See if we need to rearm the RX queue - gives the prefetch a bit
289 if (rxq->rxrearm_nb > RTE_IXGBE_RXQ_REARM_THRESH)
290 ixgbe_rxq_rearm(rxq);
292 /* Before we start moving massive data around, check to see if
293 * there is actually a packet available
295 if (!(rxdp->wb.upper.status_error &
296 rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
299 /* 4 packets DD mask */
300 dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
302 /* 4 packets EOP mask */
303 eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
305 /* mask to shuffle from desc. to mbuf */
306 shuf_msk = _mm_set_epi8(
307 7, 6, 5, 4, /* octet 4~7, 32bits rss */
308 15, 14, /* octet 14~15, low 16 bits vlan_macip */
309 13, 12, /* octet 12~13, 16 bits data_len */
310 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
311 13, 12, /* octet 12~13, low 16 bits pkt_len */
312 0xFF, 0xFF, /* skip 32 bit pkt_type */
316 mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
318 /* Cache is empty -> need to scan the buffer rings, but first move
319 * the next 'n' mbufs into the cache
321 sw_ring = &rxq->sw_ring[rxq->rx_tail];
323 /* ensure these 2 flags are in the lower 8 bits */
324 RTE_BUILD_BUG_ON((PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED) > UINT8_MAX);
325 vlan_flags = rxq->vlan_flags & UINT8_MAX;
327 /* A. load 4 packet in one loop
328 * [A*. mask out 4 unused dirty field in desc]
329 * B. copy 4 mbuf point from swring to rx_pkts
330 * C. calc the number of DD bits among the 4 packets
331 * [C*. extract the end-of-packet bit, if requested]
332 * D. fill info. from desc to mbuf
334 for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
335 pos += RTE_IXGBE_DESCS_PER_LOOP,
336 rxdp += RTE_IXGBE_DESCS_PER_LOOP) {
337 __m128i descs[RTE_IXGBE_DESCS_PER_LOOP];
338 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
339 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
340 /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */
342 #if defined(RTE_ARCH_X86_64)
346 /* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */
347 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
349 /* Read desc statuses backwards to avoid race condition */
350 /* A.1 load 4 pkts desc */
351 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
352 rte_compiler_barrier();
354 /* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */
355 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
357 #if defined(RTE_ARCH_X86_64)
358 /* B.1 load 2 64 bit mbuf points */
359 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
362 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
363 rte_compiler_barrier();
364 /* B.1 load 2 mbuf point */
365 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
366 rte_compiler_barrier();
367 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
369 #if defined(RTE_ARCH_X86_64)
370 /* B.2 copy 2 mbuf point into rx_pkts */
371 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
375 rte_mbuf_prefetch_part2(rx_pkts[pos]);
376 rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
377 rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
378 rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
381 /* avoid compiler reorder optimization */
382 rte_compiler_barrier();
384 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
385 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
386 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
388 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
389 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
390 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
392 /* C.1 4=>2 filter staterr info only */
393 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
394 /* C.1 4=>2 filter staterr info only */
395 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
397 /* set ol_flags with vlan packet type */
398 desc_to_olflags_v(descs, mbuf_init, vlan_flags, &rx_pkts[pos]);
400 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
401 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
402 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
404 /* C.2 get 4 pkts staterr value */
405 zero = _mm_xor_si128(dd_check, dd_check);
406 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
408 /* D.3 copy final 3,4 data to rx_pkts */
409 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
411 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
414 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
415 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
416 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
418 /* C* extract and record EOP bit */
420 __m128i eop_shuf_mask = _mm_set_epi8(
421 0xFF, 0xFF, 0xFF, 0xFF,
422 0xFF, 0xFF, 0xFF, 0xFF,
423 0xFF, 0xFF, 0xFF, 0xFF,
424 0x04, 0x0C, 0x00, 0x08
427 /* and with mask to extract bits, flipping 1-0 */
428 __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
429 /* the staterr values are not in order, as the count
430 * count of dd bits doesn't care. However, for end of
431 * packet tracking, we do care, so shuffle. This also
432 * compresses the 32-bit values to 8-bit
434 eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
435 /* store the resulting 32-bit value */
436 *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
437 split_packet += RTE_IXGBE_DESCS_PER_LOOP;
440 /* C.3 calc available number of desc */
441 staterr = _mm_and_si128(staterr, dd_check);
442 staterr = _mm_packs_epi32(staterr, zero);
444 /* D.3 copy final 1,2 data to rx_pkts */
445 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
447 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
450 /* C.4 calc avaialbe number of desc */
451 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
453 if (likely(var != RTE_IXGBE_DESCS_PER_LOOP))
457 /* Update our internal tail pointer */
458 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
459 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
460 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
466 * vPMD receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP)
469 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
470 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
472 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
475 ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
478 return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
482 * vPMD receive routine that reassembles scattered packets
485 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
486 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
488 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
491 ixgbe_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
494 struct ixgbe_rx_queue *rxq = rx_queue;
495 uint8_t split_flags[RTE_IXGBE_MAX_RX_BURST] = {0};
497 /* get some new buffers */
498 uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
503 /* happy day case, full burst + no packets to be joined */
504 const uint64_t *split_fl64 = (uint64_t *)split_flags;
505 if (rxq->pkt_first_seg == NULL &&
506 split_fl64[0] == 0 && split_fl64[1] == 0 &&
507 split_fl64[2] == 0 && split_fl64[3] == 0)
510 /* reassemble any packets that need reassembly*/
512 if (rxq->pkt_first_seg == NULL) {
513 /* find the first split flag, and only reassemble then*/
514 while (i < nb_bufs && !split_flags[i])
519 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
524 vtx1(volatile union ixgbe_adv_tx_desc *txdp,
525 struct rte_mbuf *pkt, uint64_t flags)
527 __m128i descriptor = _mm_set_epi64x((uint64_t)pkt->pkt_len << 46 |
528 flags | pkt->data_len,
529 pkt->buf_physaddr + pkt->data_off);
530 _mm_store_si128((__m128i *)&txdp->read, descriptor);
534 vtx(volatile union ixgbe_adv_tx_desc *txdp,
535 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
539 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
540 vtx1(txdp, *pkt, flags);
544 ixgbe_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
547 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
548 volatile union ixgbe_adv_tx_desc *txdp;
549 struct ixgbe_tx_entry_v *txep;
550 uint16_t n, nb_commit, tx_id;
551 uint64_t flags = DCMD_DTYP_FLAGS;
552 uint64_t rs = IXGBE_ADVTXD_DCMD_RS|DCMD_DTYP_FLAGS;
555 /* cross rx_thresh boundary is not allowed */
556 nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
558 if (txq->nb_tx_free < txq->tx_free_thresh)
559 ixgbe_tx_free_bufs(txq);
561 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
562 if (unlikely(nb_pkts == 0))
565 tx_id = txq->tx_tail;
566 txdp = &txq->tx_ring[tx_id];
567 txep = &txq->sw_ring_v[tx_id];
569 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
571 n = (uint16_t)(txq->nb_tx_desc - tx_id);
572 if (nb_commit >= n) {
574 tx_backlog_entry(txep, tx_pkts, n);
576 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
577 vtx1(txdp, *tx_pkts, flags);
579 vtx1(txdp, *tx_pkts++, rs);
581 nb_commit = (uint16_t)(nb_commit - n);
584 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
586 /* avoid reach the end of ring */
587 txdp = &(txq->tx_ring[tx_id]);
588 txep = &txq->sw_ring_v[tx_id];
591 tx_backlog_entry(txep, tx_pkts, nb_commit);
593 vtx(txdp, tx_pkts, nb_commit, flags);
595 tx_id = (uint16_t)(tx_id + nb_commit);
596 if (tx_id > txq->tx_next_rs) {
597 txq->tx_ring[txq->tx_next_rs].read.cmd_type_len |=
598 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
599 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
603 txq->tx_tail = tx_id;
605 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
610 static void __attribute__((cold))
611 ixgbe_tx_queue_release_mbufs_vec(struct ixgbe_tx_queue *txq)
613 _ixgbe_tx_queue_release_mbufs_vec(txq);
616 void __attribute__((cold))
617 ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq)
619 _ixgbe_rx_queue_release_mbufs_vec(rxq);
622 static void __attribute__((cold))
623 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
625 _ixgbe_tx_free_swring_vec(txq);
628 static void __attribute__((cold))
629 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
631 _ixgbe_reset_tx_queue_vec(txq);
634 static const struct ixgbe_txq_ops vec_txq_ops = {
635 .release_mbufs = ixgbe_tx_queue_release_mbufs_vec,
636 .free_swring = ixgbe_tx_free_swring,
637 .reset = ixgbe_reset_tx_queue,
640 int __attribute__((cold))
641 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq)
643 return ixgbe_rxq_vec_setup_default(rxq);
646 int __attribute__((cold))
647 ixgbe_txq_vec_setup(struct ixgbe_tx_queue *txq)
649 return ixgbe_txq_vec_setup_default(txq, &vec_txq_ops);
652 int __attribute__((cold))
653 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
655 return ixgbe_rx_vec_dev_conf_condition_check_default(dev);