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35 #include <rte_ethdev.h>
36 #include <rte_malloc.h>
38 #include "ixgbe_ethdev.h"
39 #include "ixgbe_rxtx.h"
40 #include "ixgbe_rxtx_vec_common.h"
42 #include <tmmintrin.h>
44 #ifndef __INTEL_COMPILER
45 #pragma GCC diagnostic ignored "-Wcast-qual"
49 ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq)
53 volatile union ixgbe_adv_rx_desc *rxdp;
54 struct ixgbe_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
55 struct rte_mbuf *mb0, *mb1;
56 __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
57 RTE_PKTMBUF_HEADROOM);
58 __m128i dma_addr0, dma_addr1;
60 const __m128i hba_msk = _mm_set_epi64x(0, UINT64_MAX);
62 rxdp = rxq->rx_ring + rxq->rxrearm_start;
64 /* Pull 'n' more MBUFs into the software ring */
65 if (rte_mempool_get_bulk(rxq->mb_pool,
67 RTE_IXGBE_RXQ_REARM_THRESH) < 0) {
68 if (rxq->rxrearm_nb + RTE_IXGBE_RXQ_REARM_THRESH >=
70 dma_addr0 = _mm_setzero_si128();
71 for (i = 0; i < RTE_IXGBE_DESCS_PER_LOOP; i++) {
72 rxep[i].mbuf = &rxq->fake_mbuf;
73 _mm_store_si128((__m128i *)&rxdp[i].read,
77 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
78 RTE_IXGBE_RXQ_REARM_THRESH;
82 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
83 for (i = 0; i < RTE_IXGBE_RXQ_REARM_THRESH; i += 2, rxep += 2) {
84 __m128i vaddr0, vaddr1;
89 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
90 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_physaddr) !=
91 offsetof(struct rte_mbuf, buf_addr) + 8);
92 vaddr0 = _mm_loadu_si128((__m128i *)&(mb0->buf_addr));
93 vaddr1 = _mm_loadu_si128((__m128i *)&(mb1->buf_addr));
95 /* convert pa to dma_addr hdr/data */
96 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
97 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
99 /* add headroom to pa values */
100 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
101 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
103 /* set Header Buffer Address to zero */
104 dma_addr0 = _mm_and_si128(dma_addr0, hba_msk);
105 dma_addr1 = _mm_and_si128(dma_addr1, hba_msk);
107 /* flush desc with pa dma_addr */
108 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
109 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
112 rxq->rxrearm_start += RTE_IXGBE_RXQ_REARM_THRESH;
113 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
114 rxq->rxrearm_start = 0;
116 rxq->rxrearm_nb -= RTE_IXGBE_RXQ_REARM_THRESH;
118 rx_id = (uint16_t) ((rxq->rxrearm_start == 0) ?
119 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
121 /* Update the tail pointer on the NIC */
122 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
126 desc_to_olflags_v_ipsec(__m128i descs[4], struct rte_mbuf **rx_pkts)
128 __m128i sterr0, sterr1, sterr2, sterr3;
129 __m128i tmp1, tmp2, tmp3, tmp4;
130 __m128i rearm0, rearm1, rearm2, rearm3;
132 const __m128i ipsec_sterr_msk = _mm_set_epi32(
133 0, IXGBE_RXDADV_IPSEC_STATUS_SECP |
134 IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED,
136 const __m128i ipsec_proc_msk = _mm_set_epi32(
137 0, IXGBE_RXDADV_IPSEC_STATUS_SECP, 0, 0);
138 const __m128i ipsec_err_flag = _mm_set_epi32(
139 0, PKT_RX_SEC_OFFLOAD_FAILED | PKT_RX_SEC_OFFLOAD,
141 const __m128i ipsec_proc_flag = _mm_set_epi32(
142 0, PKT_RX_SEC_OFFLOAD, 0, 0);
144 rearm0 = _mm_load_si128((__m128i *)&rx_pkts[0]->rearm_data);
145 rearm1 = _mm_load_si128((__m128i *)&rx_pkts[1]->rearm_data);
146 rearm2 = _mm_load_si128((__m128i *)&rx_pkts[2]->rearm_data);
147 rearm3 = _mm_load_si128((__m128i *)&rx_pkts[3]->rearm_data);
148 sterr0 = _mm_and_si128(descs[0], ipsec_sterr_msk);
149 sterr1 = _mm_and_si128(descs[1], ipsec_sterr_msk);
150 sterr2 = _mm_and_si128(descs[2], ipsec_sterr_msk);
151 sterr3 = _mm_and_si128(descs[3], ipsec_sterr_msk);
152 tmp1 = _mm_cmpeq_epi32(sterr0, ipsec_sterr_msk);
153 tmp2 = _mm_cmpeq_epi32(sterr0, ipsec_proc_msk);
154 tmp3 = _mm_cmpeq_epi32(sterr1, ipsec_sterr_msk);
155 tmp4 = _mm_cmpeq_epi32(sterr1, ipsec_proc_msk);
156 sterr0 = _mm_or_si128(_mm_and_si128(tmp1, ipsec_err_flag),
157 _mm_and_si128(tmp2, ipsec_proc_flag));
158 sterr1 = _mm_or_si128(_mm_and_si128(tmp3, ipsec_err_flag),
159 _mm_and_si128(tmp4, ipsec_proc_flag));
160 tmp1 = _mm_cmpeq_epi32(sterr2, ipsec_sterr_msk);
161 tmp2 = _mm_cmpeq_epi32(sterr2, ipsec_proc_msk);
162 tmp3 = _mm_cmpeq_epi32(sterr3, ipsec_sterr_msk);
163 tmp4 = _mm_cmpeq_epi32(sterr3, ipsec_proc_msk);
164 sterr2 = _mm_or_si128(_mm_and_si128(tmp1, ipsec_err_flag),
165 _mm_and_si128(tmp2, ipsec_proc_flag));
166 sterr3 = _mm_or_si128(_mm_and_si128(tmp3, ipsec_err_flag),
167 _mm_and_si128(tmp4, ipsec_proc_flag));
168 rearm0 = _mm_or_si128(rearm0, sterr0);
169 rearm1 = _mm_or_si128(rearm1, sterr1);
170 rearm2 = _mm_or_si128(rearm2, sterr2);
171 rearm3 = _mm_or_si128(rearm3, sterr3);
172 _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);
173 _mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);
174 _mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);
175 _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);
179 desc_to_olflags_v(__m128i descs[4], __m128i mbuf_init, uint8_t vlan_flags,
180 struct rte_mbuf **rx_pkts)
182 __m128i ptype0, ptype1, vtag0, vtag1, csum;
183 __m128i rearm0, rearm1, rearm2, rearm3;
185 /* mask everything except rss type */
186 const __m128i rsstype_msk = _mm_set_epi16(
187 0x0000, 0x0000, 0x0000, 0x0000,
188 0x000F, 0x000F, 0x000F, 0x000F);
190 /* mask the lower byte of ol_flags */
191 const __m128i ol_flags_msk = _mm_set_epi16(
192 0x0000, 0x0000, 0x0000, 0x0000,
193 0x00FF, 0x00FF, 0x00FF, 0x00FF);
195 /* map rss type to rss hash flag */
196 const __m128i rss_flags = _mm_set_epi8(PKT_RX_FDIR, 0, 0, 0,
197 0, 0, 0, PKT_RX_RSS_HASH,
198 PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0,
199 PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, 0);
201 /* mask everything except vlan present and l4/ip csum error */
202 const __m128i vlan_csum_msk = _mm_set_epi16(
203 (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
204 (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
205 (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
206 (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
207 IXGBE_RXD_STAT_VP, IXGBE_RXD_STAT_VP,
208 IXGBE_RXD_STAT_VP, IXGBE_RXD_STAT_VP);
209 /* map vlan present (0x8), IPE (0x2), L4E (0x1) to ol_flags */
210 const __m128i vlan_csum_map_lo = _mm_set_epi8(
212 vlan_flags | PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD,
213 vlan_flags | PKT_RX_IP_CKSUM_BAD,
214 vlan_flags | PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
215 vlan_flags | PKT_RX_IP_CKSUM_GOOD,
217 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD,
219 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
220 PKT_RX_IP_CKSUM_GOOD);
222 const __m128i vlan_csum_map_hi = _mm_set_epi8(
224 0, PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t), 0,
225 PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t),
227 0, PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t), 0,
228 PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t));
230 ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
231 ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
232 vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
233 vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
235 ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
236 ptype0 = _mm_and_si128(ptype0, rsstype_msk);
237 ptype0 = _mm_shuffle_epi8(rss_flags, ptype0);
239 vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
240 vtag1 = _mm_and_si128(vtag1, vlan_csum_msk);
242 /* csum bits are in the most significant, to use shuffle we need to
243 * shift them. Change mask to 0xc000 to 0x0003.
245 csum = _mm_srli_epi16(vtag1, 14);
247 /* now or the most significant 64 bits containing the checksum
248 * flags with the vlan present flags.
250 csum = _mm_srli_si128(csum, 8);
251 vtag1 = _mm_or_si128(csum, vtag1);
253 /* convert VP, IPE, L4E to ol_flags */
254 vtag0 = _mm_shuffle_epi8(vlan_csum_map_hi, vtag1);
255 vtag0 = _mm_slli_epi16(vtag0, sizeof(uint8_t));
257 vtag1 = _mm_shuffle_epi8(vlan_csum_map_lo, vtag1);
258 vtag1 = _mm_and_si128(vtag1, ol_flags_msk);
259 vtag1 = _mm_or_si128(vtag0, vtag1);
261 vtag1 = _mm_or_si128(ptype0, vtag1);
264 * At this point, we have the 4 sets of flags in the low 64-bits
266 * We want to extract these, and merge them with the mbuf init data
267 * so we can do a single 16-byte write to the mbuf to set the flags
268 * and all the other initialization fields. Extracting the
269 * appropriate flags means that we have to do a shift and blend for
270 * each mbuf before we do the write.
272 rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 8), 0x10);
273 rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 6), 0x10);
274 rearm2 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 4), 0x10);
275 rearm3 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 2), 0x10);
277 /* write the rearm data and the olflags in one write */
278 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
279 offsetof(struct rte_mbuf, rearm_data) + 8);
280 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
281 RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
282 _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);
283 _mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);
284 _mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);
285 _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);
288 static inline uint32_t get_packet_type(int index,
291 uint32_t tunnel_check)
293 if (etqf_check & (0x02 << (index * RTE_IXGBE_DESCS_PER_LOOP)))
294 return RTE_PTYPE_UNKNOWN;
296 if (tunnel_check & (0x02 << (index * RTE_IXGBE_DESCS_PER_LOOP))) {
297 pkt_info &= IXGBE_PACKET_TYPE_MASK_TUNNEL;
298 return ptype_table_tn[pkt_info];
301 pkt_info &= IXGBE_PACKET_TYPE_MASK_82599;
302 return ptype_table[pkt_info];
306 desc_to_ptype_v(__m128i descs[4], uint16_t pkt_type_mask,
307 struct rte_mbuf **rx_pkts)
309 __m128i etqf_mask = _mm_set_epi64x(0x800000008000LL, 0x800000008000LL);
310 __m128i ptype_mask = _mm_set_epi32(
311 pkt_type_mask, pkt_type_mask, pkt_type_mask, pkt_type_mask);
312 __m128i tunnel_mask =
313 _mm_set_epi64x(0x100000001000LL, 0x100000001000LL);
315 uint32_t etqf_check, tunnel_check, pkt_info;
317 __m128i ptype0 = _mm_unpacklo_epi32(descs[0], descs[2]);
318 __m128i ptype1 = _mm_unpacklo_epi32(descs[1], descs[3]);
320 /* interleave low 32 bits,
321 * now we have 4 ptypes in a XMM register
323 ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
325 /* create a etqf bitmask based on the etqf bit. */
326 etqf_check = _mm_movemask_epi8(_mm_and_si128(ptype0, etqf_mask));
328 /* shift left by IXGBE_PACKET_TYPE_SHIFT, and apply ptype mask */
329 ptype0 = _mm_and_si128(_mm_srli_epi32(ptype0, IXGBE_PACKET_TYPE_SHIFT),
332 /* create a tunnel bitmask based on the tunnel bit */
333 tunnel_check = _mm_movemask_epi8(
334 _mm_slli_epi32(_mm_and_si128(ptype0, tunnel_mask), 0x3));
336 pkt_info = _mm_extract_epi32(ptype0, 0);
337 rx_pkts[0]->packet_type =
338 get_packet_type(0, pkt_info, etqf_check, tunnel_check);
339 pkt_info = _mm_extract_epi32(ptype0, 1);
340 rx_pkts[1]->packet_type =
341 get_packet_type(1, pkt_info, etqf_check, tunnel_check);
342 pkt_info = _mm_extract_epi32(ptype0, 2);
343 rx_pkts[2]->packet_type =
344 get_packet_type(2, pkt_info, etqf_check, tunnel_check);
345 pkt_info = _mm_extract_epi32(ptype0, 3);
346 rx_pkts[3]->packet_type =
347 get_packet_type(3, pkt_info, etqf_check, tunnel_check);
351 * vPMD raw receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP)
354 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
355 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
357 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
359 static inline uint16_t
360 _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
361 uint16_t nb_pkts, uint8_t *split_packet)
363 volatile union ixgbe_adv_rx_desc *rxdp;
364 struct ixgbe_rx_entry *sw_ring;
365 uint16_t nb_pkts_recd;
366 uint8_t use_ipsec = rxq->using_ipsec;
370 __m128i crc_adjust = _mm_set_epi16(
371 0, 0, 0, /* ignore non-length fields */
372 -rxq->crc_len, /* sub crc on data_len */
373 0, /* ignore high-16bits of pkt_len */
374 -rxq->crc_len, /* sub crc on pkt_len */
375 0, 0 /* ignore pkt_type field */
378 * compile-time check the above crc_adjust layout is correct.
379 * NOTE: the first field (lowest address) is given last in set_epi16
382 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
383 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
384 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
385 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
386 __m128i dd_check, eop_check;
390 /* nb_pkts shall be less equal than RTE_IXGBE_MAX_RX_BURST */
391 nb_pkts = RTE_MIN(nb_pkts, RTE_IXGBE_MAX_RX_BURST);
393 /* nb_pkts has to be floor-aligned to RTE_IXGBE_DESCS_PER_LOOP */
394 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_IXGBE_DESCS_PER_LOOP);
396 /* Just the act of getting into the function from the application is
397 * going to cost about 7 cycles
399 rxdp = rxq->rx_ring + rxq->rx_tail;
403 /* See if we need to rearm the RX queue - gives the prefetch a bit
406 if (rxq->rxrearm_nb > RTE_IXGBE_RXQ_REARM_THRESH)
407 ixgbe_rxq_rearm(rxq);
409 /* Before we start moving massive data around, check to see if
410 * there is actually a packet available
412 if (!(rxdp->wb.upper.status_error &
413 rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
416 /* 4 packets DD mask */
417 dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
419 /* 4 packets EOP mask */
420 eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
422 /* mask to shuffle from desc. to mbuf */
423 shuf_msk = _mm_set_epi8(
424 7, 6, 5, 4, /* octet 4~7, 32bits rss */
425 15, 14, /* octet 14~15, low 16 bits vlan_macip */
426 13, 12, /* octet 12~13, 16 bits data_len */
427 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
428 13, 12, /* octet 12~13, low 16 bits pkt_len */
429 0xFF, 0xFF, /* skip 32 bit pkt_type */
433 * Compile-time verify the shuffle mask
434 * NOTE: some field positions already verified above, but duplicated
435 * here for completeness in case of future modifications.
437 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
438 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
439 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
440 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
441 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
442 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
443 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
444 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
446 mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
448 /* Cache is empty -> need to scan the buffer rings, but first move
449 * the next 'n' mbufs into the cache
451 sw_ring = &rxq->sw_ring[rxq->rx_tail];
453 /* ensure these 2 flags are in the lower 8 bits */
454 RTE_BUILD_BUG_ON((PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED) > UINT8_MAX);
455 vlan_flags = rxq->vlan_flags & UINT8_MAX;
457 /* A. load 4 packet in one loop
458 * [A*. mask out 4 unused dirty field in desc]
459 * B. copy 4 mbuf point from swring to rx_pkts
460 * C. calc the number of DD bits among the 4 packets
461 * [C*. extract the end-of-packet bit, if requested]
462 * D. fill info. from desc to mbuf
464 for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
465 pos += RTE_IXGBE_DESCS_PER_LOOP,
466 rxdp += RTE_IXGBE_DESCS_PER_LOOP) {
467 __m128i descs[RTE_IXGBE_DESCS_PER_LOOP];
468 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
469 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
470 /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */
472 #if defined(RTE_ARCH_X86_64)
476 /* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */
477 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
479 /* Read desc statuses backwards to avoid race condition */
480 /* A.1 load 4 pkts desc */
481 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
482 rte_compiler_barrier();
484 /* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */
485 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
487 #if defined(RTE_ARCH_X86_64)
488 /* B.1 load 2 64 bit mbuf points */
489 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
492 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
493 rte_compiler_barrier();
494 /* B.1 load 2 mbuf point */
495 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
496 rte_compiler_barrier();
497 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
499 #if defined(RTE_ARCH_X86_64)
500 /* B.2 copy 2 mbuf point into rx_pkts */
501 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
505 rte_mbuf_prefetch_part2(rx_pkts[pos]);
506 rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
507 rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
508 rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
511 /* avoid compiler reorder optimization */
512 rte_compiler_barrier();
514 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
515 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
516 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
518 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
519 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
520 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
522 /* C.1 4=>2 filter staterr info only */
523 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
524 /* C.1 4=>2 filter staterr info only */
525 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
527 /* set ol_flags with vlan packet type */
528 desc_to_olflags_v(descs, mbuf_init, vlan_flags, &rx_pkts[pos]);
530 if (unlikely(use_ipsec))
531 desc_to_olflags_v_ipsec(descs, rx_pkts);
533 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
534 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
535 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
537 /* C.2 get 4 pkts staterr value */
538 zero = _mm_xor_si128(dd_check, dd_check);
539 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
541 /* D.3 copy final 3,4 data to rx_pkts */
542 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
544 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
547 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
548 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
549 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
551 /* C* extract and record EOP bit */
553 __m128i eop_shuf_mask = _mm_set_epi8(
554 0xFF, 0xFF, 0xFF, 0xFF,
555 0xFF, 0xFF, 0xFF, 0xFF,
556 0xFF, 0xFF, 0xFF, 0xFF,
557 0x04, 0x0C, 0x00, 0x08
560 /* and with mask to extract bits, flipping 1-0 */
561 __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
562 /* the staterr values are not in order, as the count
563 * count of dd bits doesn't care. However, for end of
564 * packet tracking, we do care, so shuffle. This also
565 * compresses the 32-bit values to 8-bit
567 eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
568 /* store the resulting 32-bit value */
569 *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
570 split_packet += RTE_IXGBE_DESCS_PER_LOOP;
573 /* C.3 calc available number of desc */
574 staterr = _mm_and_si128(staterr, dd_check);
575 staterr = _mm_packs_epi32(staterr, zero);
577 /* D.3 copy final 1,2 data to rx_pkts */
578 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
580 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
583 desc_to_ptype_v(descs, rxq->pkt_type_mask, &rx_pkts[pos]);
585 /* C.4 calc avaialbe number of desc */
586 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
588 if (likely(var != RTE_IXGBE_DESCS_PER_LOOP))
592 /* Update our internal tail pointer */
593 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
594 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
595 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
601 * vPMD receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP)
604 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
605 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
607 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
610 ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
613 return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
617 * vPMD receive routine that reassembles scattered packets
620 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
621 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
623 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
626 ixgbe_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
629 struct ixgbe_rx_queue *rxq = rx_queue;
630 uint8_t split_flags[RTE_IXGBE_MAX_RX_BURST] = {0};
632 /* get some new buffers */
633 uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
638 /* happy day case, full burst + no packets to be joined */
639 const uint64_t *split_fl64 = (uint64_t *)split_flags;
640 if (rxq->pkt_first_seg == NULL &&
641 split_fl64[0] == 0 && split_fl64[1] == 0 &&
642 split_fl64[2] == 0 && split_fl64[3] == 0)
645 /* reassemble any packets that need reassembly*/
647 if (rxq->pkt_first_seg == NULL) {
648 /* find the first split flag, and only reassemble then*/
649 while (i < nb_bufs && !split_flags[i])
654 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
659 vtx1(volatile union ixgbe_adv_tx_desc *txdp,
660 struct rte_mbuf *pkt, uint64_t flags)
662 __m128i descriptor = _mm_set_epi64x((uint64_t)pkt->pkt_len << 46 |
663 flags | pkt->data_len,
664 pkt->buf_physaddr + pkt->data_off);
665 _mm_store_si128((__m128i *)&txdp->read, descriptor);
669 vtx(volatile union ixgbe_adv_tx_desc *txdp,
670 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
674 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
675 vtx1(txdp, *pkt, flags);
679 ixgbe_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
682 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
683 volatile union ixgbe_adv_tx_desc *txdp;
684 struct ixgbe_tx_entry_v *txep;
685 uint16_t n, nb_commit, tx_id;
686 uint64_t flags = DCMD_DTYP_FLAGS;
687 uint64_t rs = IXGBE_ADVTXD_DCMD_RS|DCMD_DTYP_FLAGS;
690 /* cross rx_thresh boundary is not allowed */
691 nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
693 if (txq->nb_tx_free < txq->tx_free_thresh)
694 ixgbe_tx_free_bufs(txq);
696 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
697 if (unlikely(nb_pkts == 0))
700 tx_id = txq->tx_tail;
701 txdp = &txq->tx_ring[tx_id];
702 txep = &txq->sw_ring_v[tx_id];
704 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
706 n = (uint16_t)(txq->nb_tx_desc - tx_id);
707 if (nb_commit >= n) {
709 tx_backlog_entry(txep, tx_pkts, n);
711 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
712 vtx1(txdp, *tx_pkts, flags);
714 vtx1(txdp, *tx_pkts++, rs);
716 nb_commit = (uint16_t)(nb_commit - n);
719 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
721 /* avoid reach the end of ring */
722 txdp = &(txq->tx_ring[tx_id]);
723 txep = &txq->sw_ring_v[tx_id];
726 tx_backlog_entry(txep, tx_pkts, nb_commit);
728 vtx(txdp, tx_pkts, nb_commit, flags);
730 tx_id = (uint16_t)(tx_id + nb_commit);
731 if (tx_id > txq->tx_next_rs) {
732 txq->tx_ring[txq->tx_next_rs].read.cmd_type_len |=
733 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
734 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
738 txq->tx_tail = tx_id;
740 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
745 static void __attribute__((cold))
746 ixgbe_tx_queue_release_mbufs_vec(struct ixgbe_tx_queue *txq)
748 _ixgbe_tx_queue_release_mbufs_vec(txq);
751 void __attribute__((cold))
752 ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq)
754 _ixgbe_rx_queue_release_mbufs_vec(rxq);
757 static void __attribute__((cold))
758 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
760 _ixgbe_tx_free_swring_vec(txq);
763 static void __attribute__((cold))
764 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
766 _ixgbe_reset_tx_queue_vec(txq);
769 static const struct ixgbe_txq_ops vec_txq_ops = {
770 .release_mbufs = ixgbe_tx_queue_release_mbufs_vec,
771 .free_swring = ixgbe_tx_free_swring,
772 .reset = ixgbe_reset_tx_queue,
775 int __attribute__((cold))
776 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq)
778 return ixgbe_rxq_vec_setup_default(rxq);
781 int __attribute__((cold))
782 ixgbe_txq_vec_setup(struct ixgbe_tx_queue *txq)
784 return ixgbe_txq_vec_setup_default(txq, &vec_txq_ops);
787 int __attribute__((cold))
788 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
790 return ixgbe_rx_vec_dev_conf_condition_check_default(dev);