drivers/net/ixgbe/ixgbe_tm.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include "ixgbe_ethdev.h"
  35
  36 static int ixgbe_tm_capabilities_get(struct rte_eth_dev *dev,
  37                                      struct rte_tm_capabilities *cap,
  38                                      struct rte_tm_error *error);
  39
  40 const struct rte_tm_ops ixgbe_tm_ops = {
  41         .capabilities_get = ixgbe_tm_capabilities_get,
  42 };
  43
  44 int
  45 ixgbe_tm_ops_get(struct rte_eth_dev *dev __rte_unused,
  46                  void *arg)
  47 {
  48         if (!arg)
  49                 return -EINVAL;
  50
  51         *(const void **)arg = &ixgbe_tm_ops;
  52
  53         return 0;
  54 }
  55
  56 static inline uint8_t
  57 ixgbe_tc_nb_get(struct rte_eth_dev *dev)
  58 {
  59         struct rte_eth_conf *eth_conf;
  60         uint8_t nb_tcs = 0;
  61
  62         eth_conf = &dev->data->dev_conf;
  63         if (eth_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
  64                 nb_tcs = eth_conf->tx_adv_conf.dcb_tx_conf.nb_tcs;
  65         } else if (eth_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
  66                 if (eth_conf->tx_adv_conf.vmdq_dcb_tx_conf.nb_queue_pools ==
  67                     ETH_32_POOLS)
  68                         nb_tcs = ETH_4_TCS;
  69                 else
  70                         nb_tcs = ETH_8_TCS;
  71         } else {
  72                 nb_tcs = 1;
  73         }
  74
  75         return nb_tcs;
  76 }
  77
  78 static int
  79 ixgbe_tm_capabilities_get(struct rte_eth_dev *dev,
  80                           struct rte_tm_capabilities *cap,
  81                           struct rte_tm_error *error)
  82 {
  83         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
  84         uint8_t tc_nb = ixgbe_tc_nb_get(dev);
  85
  86         if (!cap || !error)
  87                 return -EINVAL;
  88
  89         if (tc_nb > hw->mac.max_tx_queues)
  90                 return -EINVAL;
  91
  92         error->type = RTE_TM_ERROR_TYPE_NONE;
  93
  94         /* set all the parameters to 0 first. */
  95         memset(cap, 0, sizeof(struct rte_tm_capabilities));
  96
  97         /**
  98          * here is the max capability not the current configuration.
  99          */
 100         /* port + TCs + queues */
 101         cap->n_nodes_max = 1 + IXGBE_DCB_MAX_TRAFFIC_CLASS +
 102                            hw->mac.max_tx_queues;
 103         cap->n_levels_max = 3;
 104         cap->non_leaf_nodes_identical = 1;
 105         cap->leaf_nodes_identical = 1;
 106         cap->shaper_n_max = cap->n_nodes_max;
 107         cap->shaper_private_n_max = cap->n_nodes_max;
 108         cap->shaper_private_dual_rate_n_max = 0;
 109         cap->shaper_private_rate_min = 0;
 110         /* 10Gbps -> 1.25GBps */
 111         cap->shaper_private_rate_max = 1250000000ull;
 112         cap->shaper_shared_n_max = 0;
 113         cap->shaper_shared_n_nodes_per_shaper_max = 0;
 114         cap->shaper_shared_n_shapers_per_node_max = 0;
 115         cap->shaper_shared_dual_rate_n_max = 0;
 116         cap->shaper_shared_rate_min = 0;
 117         cap->shaper_shared_rate_max = 0;
 118         cap->sched_n_children_max = hw->mac.max_tx_queues;
 119         /**
 120          * HW supports SP. But no plan to support it now.
 121          * So, all the nodes should have the same priority.
 122          */
 123         cap->sched_sp_n_priorities_max = 1;
 124         cap->sched_wfq_n_children_per_group_max = 0;
 125         cap->sched_wfq_n_groups_max = 0;
 126         /**
 127          * SW only supports fair round robin now.
 128          * So, all the nodes should have the same weight.
 129          */
 130         cap->sched_wfq_weight_max = 1;
 131         cap->cman_head_drop_supported = 0;
 132         cap->dynamic_update_mask = 0;
 133         cap->shaper_pkt_length_adjust_min = RTE_TM_ETH_FRAMING_OVERHEAD;
 134         cap->shaper_pkt_length_adjust_max = RTE_TM_ETH_FRAMING_OVERHEAD_FCS;
 135         cap->cman_wred_context_n_max = 0;
 136         cap->cman_wred_context_private_n_max = 0;
 137         cap->cman_wred_context_shared_n_max = 0;
 138         cap->cman_wred_context_shared_n_nodes_per_context_max = 0;
 139         cap->cman_wred_context_shared_n_contexts_per_node_max = 0;
 140         cap->stats_mask = 0;
 141
 142         return 0;
 143 }