1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
5 #include <rte_ethdev_driver.h>
7 #include "base/ixgbe_api.h"
8 #include "base/ixgbe_x550.h"
9 #include "ixgbe_ethdev.h"
10 #include "rte_pmd_ixgbe.h"
13 rte_pmd_ixgbe_set_vf_mac_addr(uint16_t port, uint16_t vf,
14 struct rte_ether_addr *mac_addr)
17 struct ixgbe_vf_info *vfinfo;
19 uint8_t *new_mac = (uint8_t *)(mac_addr);
20 struct rte_eth_dev *dev;
21 struct rte_pci_device *pci_dev;
23 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
25 dev = &rte_eth_devices[port];
26 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
28 if (!is_ixgbe_supported(dev))
31 if (vf >= pci_dev->max_vfs)
34 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
35 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
36 rar_entry = hw->mac.num_rar_entries - (vf + 1);
38 if (rte_is_valid_assigned_ether_addr(
39 (struct rte_ether_addr *)new_mac)) {
40 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
42 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
49 rte_pmd_ixgbe_ping_vf(uint16_t port, uint16_t vf)
52 struct ixgbe_vf_info *vfinfo;
53 struct rte_eth_dev *dev;
54 struct rte_pci_device *pci_dev;
57 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
59 dev = &rte_eth_devices[port];
60 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
62 if (!is_ixgbe_supported(dev))
65 if (vf >= pci_dev->max_vfs)
68 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
69 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
71 ctrl = IXGBE_PF_CONTROL_MSG;
72 if (vfinfo[vf].clear_to_send)
73 ctrl |= IXGBE_VT_MSGTYPE_CTS;
75 ixgbe_write_mbx(hw, &ctrl, 1, vf);
81 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint16_t port, uint16_t vf, uint8_t on)
84 struct ixgbe_mac_info *mac;
85 struct rte_eth_dev *dev;
86 struct rte_pci_device *pci_dev;
88 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
90 dev = &rte_eth_devices[port];
91 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
93 if (!is_ixgbe_supported(dev))
96 if (vf >= pci_dev->max_vfs)
102 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
105 mac->ops.set_vlan_anti_spoofing(hw, on, vf);
111 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint16_t port, uint16_t vf, uint8_t on)
114 struct ixgbe_mac_info *mac;
115 struct rte_eth_dev *dev;
116 struct rte_pci_device *pci_dev;
118 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
120 dev = &rte_eth_devices[port];
121 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
123 if (!is_ixgbe_supported(dev))
126 if (vf >= pci_dev->max_vfs)
132 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
134 mac->ops.set_mac_anti_spoofing(hw, on, vf);
140 rte_pmd_ixgbe_set_vf_vlan_insert(uint16_t port, uint16_t vf, uint16_t vlan_id)
144 struct rte_eth_dev *dev;
145 struct rte_pci_device *pci_dev;
147 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
149 dev = &rte_eth_devices[port];
150 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
152 if (!is_ixgbe_supported(dev))
155 if (vf >= pci_dev->max_vfs)
158 if (vlan_id > RTE_ETHER_MAX_VLAN_ID)
161 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
162 ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
165 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
170 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
176 rte_pmd_ixgbe_set_tx_loopback(uint16_t port, uint8_t on)
180 struct rte_eth_dev *dev;
182 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
184 dev = &rte_eth_devices[port];
186 if (!is_ixgbe_supported(dev))
192 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
193 ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
194 /* enable or disable VMDQ loopback */
196 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
198 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
200 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
206 rte_pmd_ixgbe_set_all_queues_drop_en(uint16_t port, uint8_t on)
211 int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
212 struct rte_eth_dev *dev;
214 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
216 dev = &rte_eth_devices[port];
218 if (!is_ixgbe_supported(dev))
224 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
225 for (i = 0; i <= num_queues; i++) {
226 reg_value = IXGBE_QDE_WRITE |
227 (i << IXGBE_QDE_IDX_SHIFT) |
228 (on & IXGBE_QDE_ENABLE);
229 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
236 rte_pmd_ixgbe_set_vf_split_drop_en(uint16_t port, uint16_t vf, uint8_t on)
240 struct rte_eth_dev *dev;
241 struct rte_pci_device *pci_dev;
243 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
245 dev = &rte_eth_devices[port];
246 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
248 if (!is_ixgbe_supported(dev))
251 /* only support VF's 0 to 63 */
252 if ((vf >= pci_dev->max_vfs) || (vf > 63))
258 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
259 reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
261 reg_value |= IXGBE_SRRCTL_DROP_EN;
263 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
265 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
271 rte_pmd_ixgbe_set_vf_vlan_stripq(uint16_t port, uint16_t vf, uint8_t on)
273 struct rte_eth_dev *dev;
274 struct rte_pci_device *pci_dev;
276 uint16_t queues_per_pool;
279 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
281 dev = &rte_eth_devices[port];
282 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
283 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
285 if (!is_ixgbe_supported(dev))
288 if (vf >= pci_dev->max_vfs)
294 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
296 /* The PF has 128 queue pairs and in SRIOV configuration
297 * those queues will be assigned to VF's, so RXDCTL
298 * registers will be dealing with queues which will be
300 * Let's say we have SRIOV configured with 31 VF's then the
301 * first 124 queues 0-123 will be allocated to VF's and only
302 * the last 4 queues 123-127 will be assigned to the PF.
304 if (hw->mac.type == ixgbe_mac_82598EB)
305 queues_per_pool = (uint16_t)hw->mac.max_rx_queues /
308 queues_per_pool = (uint16_t)hw->mac.max_rx_queues /
311 for (q = 0; q < queues_per_pool; q++)
312 (*dev->dev_ops->vlan_strip_queue_set)(dev,
313 q + vf * queues_per_pool, on);
318 rte_pmd_ixgbe_set_vf_rxmode(uint16_t port, uint16_t vf,
319 uint16_t rx_mask, uint8_t on)
322 struct rte_eth_dev *dev;
323 struct rte_pci_device *pci_dev;
327 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
329 dev = &rte_eth_devices[port];
330 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
332 if (!is_ixgbe_supported(dev))
335 if (vf >= pci_dev->max_vfs)
341 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
342 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
344 if (hw->mac.type == ixgbe_mac_82598EB) {
345 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
346 " on 82599 hardware and newer");
349 if (ixgbe_vt_check(hw) < 0)
352 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
359 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
365 rte_pmd_ixgbe_set_vf_rx(uint16_t port, uint16_t vf, uint8_t on)
367 struct rte_eth_dev *dev;
368 struct rte_pci_device *pci_dev;
371 const uint8_t bit1 = 0x1;
374 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
376 dev = &rte_eth_devices[port];
377 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
379 if (!is_ixgbe_supported(dev))
382 if (vf >= pci_dev->max_vfs)
388 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
390 if (ixgbe_vt_check(hw) < 0)
393 /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
395 addr = IXGBE_VFRE(1);
396 val = bit1 << (vf - 32);
398 addr = IXGBE_VFRE(0);
402 reg = IXGBE_READ_REG(hw, addr);
409 IXGBE_WRITE_REG(hw, addr, reg);
415 rte_pmd_ixgbe_set_vf_tx(uint16_t port, uint16_t vf, uint8_t on)
417 struct rte_eth_dev *dev;
418 struct rte_pci_device *pci_dev;
421 const uint8_t bit1 = 0x1;
425 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
427 dev = &rte_eth_devices[port];
428 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
430 if (!is_ixgbe_supported(dev))
433 if (vf >= pci_dev->max_vfs)
439 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
440 if (ixgbe_vt_check(hw) < 0)
443 /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
445 addr = IXGBE_VFTE(1);
446 val = bit1 << (vf - 32);
448 addr = IXGBE_VFTE(0);
452 reg = IXGBE_READ_REG(hw, addr);
459 IXGBE_WRITE_REG(hw, addr, reg);
465 rte_pmd_ixgbe_set_vf_vlan_filter(uint16_t port, uint16_t vlan,
466 uint64_t vf_mask, uint8_t vlan_on)
468 struct rte_eth_dev *dev;
473 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
475 dev = &rte_eth_devices[port];
477 if (!is_ixgbe_supported(dev))
480 if (vlan > RTE_ETHER_MAX_VLAN_ID || vf_mask == 0)
483 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
484 if (ixgbe_vt_check(hw) < 0)
487 for (vf_idx = 0; vf_idx < 64; vf_idx++) {
488 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
489 ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
500 rte_pmd_ixgbe_set_vf_rate_limit(uint16_t port, uint16_t vf,
501 uint16_t tx_rate, uint64_t q_msk)
503 struct rte_eth_dev *dev;
505 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
507 dev = &rte_eth_devices[port];
509 if (!is_ixgbe_supported(dev))
512 return ixgbe_set_vf_rate_limit(dev, vf, tx_rate, q_msk);
516 rte_pmd_ixgbe_macsec_enable(uint16_t port, uint8_t en, uint8_t rp)
518 struct rte_eth_dev *dev;
519 struct ixgbe_macsec_setting macsec_setting;
521 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
523 dev = &rte_eth_devices[port];
525 macsec_setting.encrypt_en = en;
526 macsec_setting.replayprotect_en = rp;
528 ixgbe_dev_macsec_setting_save(dev, &macsec_setting);
530 ixgbe_dev_macsec_register_enable(dev, &macsec_setting);
536 rte_pmd_ixgbe_macsec_disable(uint16_t port)
538 struct rte_eth_dev *dev;
540 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
542 dev = &rte_eth_devices[port];
544 ixgbe_dev_macsec_setting_reset(dev);
546 ixgbe_dev_macsec_register_disable(dev);
552 rte_pmd_ixgbe_macsec_config_txsc(uint16_t port, uint8_t *mac)
555 struct rte_eth_dev *dev;
558 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
560 dev = &rte_eth_devices[port];
562 if (!is_ixgbe_supported(dev))
565 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
567 ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
568 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
570 ctrl = mac[4] | (mac[5] << 8);
571 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
577 rte_pmd_ixgbe_macsec_config_rxsc(uint16_t port, uint8_t *mac, uint16_t pi)
580 struct rte_eth_dev *dev;
583 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
585 dev = &rte_eth_devices[port];
587 if (!is_ixgbe_supported(dev))
590 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
592 ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
593 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
595 pi = rte_cpu_to_be_16(pi);
596 ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
597 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
603 rte_pmd_ixgbe_macsec_select_txsa(uint16_t port, uint8_t idx, uint8_t an,
604 uint32_t pn, uint8_t *key)
607 struct rte_eth_dev *dev;
610 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
612 dev = &rte_eth_devices[port];
614 if (!is_ixgbe_supported(dev))
617 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
619 if (idx != 0 && idx != 1)
625 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
627 /* Set the PN and key */
628 pn = rte_cpu_to_be_32(pn);
630 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
632 for (i = 0; i < 4; i++) {
633 ctrl = (key[i * 4 + 0] << 0) |
634 (key[i * 4 + 1] << 8) |
635 (key[i * 4 + 2] << 16) |
636 (key[i * 4 + 3] << 24);
637 IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
640 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
642 for (i = 0; i < 4; i++) {
643 ctrl = (key[i * 4 + 0] << 0) |
644 (key[i * 4 + 1] << 8) |
645 (key[i * 4 + 2] << 16) |
646 (key[i * 4 + 3] << 24);
647 IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
651 /* Set AN and select the SA */
652 ctrl = (an << idx * 2) | (idx << 4);
653 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
659 rte_pmd_ixgbe_macsec_select_rxsa(uint16_t port, uint8_t idx, uint8_t an,
660 uint32_t pn, uint8_t *key)
663 struct rte_eth_dev *dev;
666 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
668 dev = &rte_eth_devices[port];
670 if (!is_ixgbe_supported(dev))
673 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
675 if (idx != 0 && idx != 1)
682 pn = rte_cpu_to_be_32(pn);
683 IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
686 for (i = 0; i < 4; i++) {
687 ctrl = (key[i * 4 + 0] << 0) |
688 (key[i * 4 + 1] << 8) |
689 (key[i * 4 + 2] << 16) |
690 (key[i * 4 + 3] << 24);
691 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
694 /* Set the AN and validate the SA */
695 ctrl = an | (1 << 2);
696 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
702 rte_pmd_ixgbe_set_tc_bw_alloc(uint16_t port,
706 struct rte_eth_dev *dev;
707 struct ixgbe_dcb_config *dcb_config;
708 struct ixgbe_dcb_tc_config *tc;
709 struct rte_eth_conf *eth_conf;
710 struct ixgbe_bw_conf *bw_conf;
715 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
717 dev = &rte_eth_devices[port];
719 if (!is_ixgbe_supported(dev))
722 if (tc_num > IXGBE_DCB_MAX_TRAFFIC_CLASS) {
723 PMD_DRV_LOG(ERR, "TCs should be no more than %d.",
724 IXGBE_DCB_MAX_TRAFFIC_CLASS);
728 dcb_config = IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
729 bw_conf = IXGBE_DEV_PRIVATE_TO_BW_CONF(dev->data->dev_private);
730 eth_conf = &dev->data->dev_conf;
732 if (eth_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
733 nb_tcs = eth_conf->tx_adv_conf.dcb_tx_conf.nb_tcs;
734 } else if (eth_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
735 if (eth_conf->tx_adv_conf.vmdq_dcb_tx_conf.nb_queue_pools ==
744 if (nb_tcs != tc_num) {
746 "Weight should be set for all %d enabled TCs.",
752 for (i = 0; i < nb_tcs; i++)
756 "The summary of the TC weight should be 100.");
760 for (i = 0; i < nb_tcs; i++) {
761 tc = &dcb_config->tc_config[i];
762 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = bw_weight[i];
764 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
765 tc = &dcb_config->tc_config[i];
766 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
769 bw_conf->tc_num = nb_tcs;
775 rte_pmd_ixgbe_upd_fctrl_sbp(uint16_t port, int enable)
778 struct rte_eth_dev *dev;
781 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
782 dev = &rte_eth_devices[port];
783 if (!is_ixgbe_supported(dev))
786 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
790 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
792 /* If 'enable' set the SBP bit else clear it */
794 fctrl |= IXGBE_FCTRL_SBP;
796 fctrl &= ~(IXGBE_FCTRL_SBP);
798 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
802 #ifdef RTE_LIBRTE_IXGBE_BYPASS
804 rte_pmd_ixgbe_bypass_init(uint16_t port_id)
806 struct rte_eth_dev *dev;
808 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
810 dev = &rte_eth_devices[port_id];
811 if (!is_ixgbe_supported(dev))
814 ixgbe_bypass_init(dev);
819 rte_pmd_ixgbe_bypass_state_show(uint16_t port_id, uint32_t *state)
821 struct rte_eth_dev *dev;
823 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
825 dev = &rte_eth_devices[port_id];
826 if (!is_ixgbe_supported(dev))
829 return ixgbe_bypass_state_show(dev, state);
833 rte_pmd_ixgbe_bypass_state_set(uint16_t port_id, uint32_t *new_state)
835 struct rte_eth_dev *dev;
837 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
839 dev = &rte_eth_devices[port_id];
840 if (!is_ixgbe_supported(dev))
843 return ixgbe_bypass_state_store(dev, new_state);
847 rte_pmd_ixgbe_bypass_event_show(uint16_t port_id,
851 struct rte_eth_dev *dev;
853 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
855 dev = &rte_eth_devices[port_id];
856 if (!is_ixgbe_supported(dev))
859 return ixgbe_bypass_event_show(dev, event, state);
863 rte_pmd_ixgbe_bypass_event_store(uint16_t port_id,
867 struct rte_eth_dev *dev;
869 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
871 dev = &rte_eth_devices[port_id];
872 if (!is_ixgbe_supported(dev))
875 return ixgbe_bypass_event_store(dev, event, state);
879 rte_pmd_ixgbe_bypass_wd_timeout_store(uint16_t port_id, uint32_t timeout)
881 struct rte_eth_dev *dev;
883 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
885 dev = &rte_eth_devices[port_id];
886 if (!is_ixgbe_supported(dev))
889 return ixgbe_bypass_wd_timeout_store(dev, timeout);
893 rte_pmd_ixgbe_bypass_ver_show(uint16_t port_id, uint32_t *ver)
895 struct rte_eth_dev *dev;
897 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
899 dev = &rte_eth_devices[port_id];
900 if (!is_ixgbe_supported(dev))
903 return ixgbe_bypass_ver_show(dev, ver);
907 rte_pmd_ixgbe_bypass_wd_timeout_show(uint16_t port_id, uint32_t *wd_timeout)
909 struct rte_eth_dev *dev;
911 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
913 dev = &rte_eth_devices[port_id];
914 if (!is_ixgbe_supported(dev))
917 return ixgbe_bypass_wd_timeout_show(dev, wd_timeout);
921 rte_pmd_ixgbe_bypass_wd_reset(uint16_t port_id)
923 struct rte_eth_dev *dev;
925 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
927 dev = &rte_eth_devices[port_id];
928 if (!is_ixgbe_supported(dev))
931 return ixgbe_bypass_wd_reset(dev);
936 * rte_pmd_ixgbe_acquire_swfw - Acquire SWFW semaphore
937 * @hw: pointer to hardware structure
938 * @mask: Mask to specify which semaphore to acquire
940 * Acquires the SWFW semaphore and get the shared phy token as needed
942 STATIC s32 rte_pmd_ixgbe_acquire_swfw(struct ixgbe_hw *hw, u32 mask)
944 int retries = FW_PHY_TOKEN_RETRIES;
945 s32 status = IXGBE_SUCCESS;
948 status = ixgbe_acquire_swfw_semaphore(hw, mask);
950 PMD_DRV_LOG(ERR, "Get SWFW sem failed, Status = %d\n",
954 status = ixgbe_get_phy_token(hw);
955 if (status == IXGBE_SUCCESS)
956 return IXGBE_SUCCESS;
958 if (status == IXGBE_ERR_TOKEN_RETRY)
959 PMD_DRV_LOG(ERR, "Get PHY token failed, Status = %d\n",
962 ixgbe_release_swfw_semaphore(hw, mask);
963 if (status != IXGBE_ERR_TOKEN_RETRY) {
965 "Retry get PHY token failed, Status=%d\n",
970 PMD_DRV_LOG(ERR, "swfw acquisition retries failed!: PHY ID = 0x%08X\n",
976 * rte_pmd_ixgbe_release_swfw_sync - Release SWFW semaphore
977 * @hw: pointer to hardware structure
978 * @mask: Mask to specify which semaphore to release
980 * Releases the SWFW semaphore and puts the shared phy token as needed
982 STATIC void rte_pmd_ixgbe_release_swfw(struct ixgbe_hw *hw, u32 mask)
984 ixgbe_put_phy_token(hw);
985 ixgbe_release_swfw_semaphore(hw, mask);
989 rte_pmd_ixgbe_mdio_lock(uint16_t port)
992 struct rte_eth_dev *dev;
995 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
996 dev = &rte_eth_devices[port];
997 if (!is_ixgbe_supported(dev))
1000 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1005 swfw_mask = IXGBE_GSSR_PHY1_SM;
1007 swfw_mask = IXGBE_GSSR_PHY0_SM;
1009 if (rte_pmd_ixgbe_acquire_swfw(hw, swfw_mask))
1010 return IXGBE_ERR_SWFW_SYNC;
1012 return IXGBE_SUCCESS;
1016 rte_pmd_ixgbe_mdio_unlock(uint16_t port)
1018 struct rte_eth_dev *dev;
1019 struct ixgbe_hw *hw;
1022 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1024 dev = &rte_eth_devices[port];
1025 if (!is_ixgbe_supported(dev))
1028 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1033 swfw_mask = IXGBE_GSSR_PHY1_SM;
1035 swfw_mask = IXGBE_GSSR_PHY0_SM;
1037 rte_pmd_ixgbe_release_swfw(hw, swfw_mask);
1039 return IXGBE_SUCCESS;
1043 rte_pmd_ixgbe_mdio_unlocked_read(uint16_t port, uint32_t reg_addr,
1044 uint32_t dev_type, uint16_t *phy_data)
1046 struct ixgbe_hw *hw;
1047 struct rte_eth_dev *dev;
1048 u32 i, data, command;
1050 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1051 dev = &rte_eth_devices[port];
1052 if (!is_ixgbe_supported(dev))
1055 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1059 /* Setup and write the read command */
1060 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
1061 (dev_type << IXGBE_MSCA_PHY_ADDR_SHIFT) |
1062 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
1063 IXGBE_MSCA_MDI_COMMAND;
1065 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
1067 /* Check every 10 usec to see if the access completed.
1068 * The MDI Command bit will clear when the operation is
1071 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1074 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
1075 if (!(command & IXGBE_MSCA_MDI_COMMAND))
1078 if (command & IXGBE_MSCA_MDI_COMMAND)
1079 return IXGBE_ERR_PHY;
1081 /* Read operation is complete. Get the data from MSRWD */
1082 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
1083 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
1084 *phy_data = (u16)data;
1090 rte_pmd_ixgbe_mdio_unlocked_write(uint16_t port, uint32_t reg_addr,
1091 uint32_t dev_type, uint16_t phy_data)
1093 struct ixgbe_hw *hw;
1095 struct rte_eth_dev *dev;
1097 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1098 dev = &rte_eth_devices[port];
1099 if (!is_ixgbe_supported(dev))
1102 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1106 /* Put the data in the MDI single read and write data register*/
1107 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
1109 /* Setup and write the write command */
1110 command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
1111 (dev_type << IXGBE_MSCA_PHY_ADDR_SHIFT) |
1112 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
1113 IXGBE_MSCA_MDI_COMMAND;
1115 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
1117 /* Check every 10 usec to see if the access completed.
1118 * The MDI Command bit will clear when the operation is
1121 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1124 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
1125 if (!(command & IXGBE_MSCA_MDI_COMMAND))
1128 if (command & IXGBE_MSCA_MDI_COMMAND) {
1129 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1130 "PHY write cmd didn't complete\n");
1131 return IXGBE_ERR_PHY;