drivers/net/ixgbe/rte_pmd_ixgbe.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <rte_ethdev_driver.h>
   6
   7 #include "base/ixgbe_api.h"
   8 #include "base/ixgbe_x550.h"
   9 #include "ixgbe_ethdev.h"
  10 #include "rte_pmd_ixgbe.h"
  11
  12 int
  13 rte_pmd_ixgbe_set_vf_mac_addr(uint16_t port, uint16_t vf,
  14                               struct rte_ether_addr *mac_addr)
  15 {
  16         struct ixgbe_hw *hw;
  17         struct ixgbe_vf_info *vfinfo;
  18         int rar_entry;
  19         uint8_t *new_mac = (uint8_t *)(mac_addr);
  20         struct rte_eth_dev *dev;
  21         struct rte_pci_device *pci_dev;
  22
  23         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
  24
  25         dev = &rte_eth_devices[port];
  26         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
  27
  28         if (!is_ixgbe_supported(dev))
  29                 return -ENOTSUP;
  30
  31         if (vf >= pci_dev->max_vfs)
  32                 return -EINVAL;
  33
  34         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
  35         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
  36         rar_entry = hw->mac.num_rar_entries - (vf + 1);
  37
  38         if (rte_is_valid_assigned_ether_addr(
  39                         (struct rte_ether_addr *)new_mac)) {
  40                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
  41                            RTE_ETHER_ADDR_LEN);
  42                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
  43                                            IXGBE_RAH_AV);
  44         }
  45         return -EINVAL;
  46 }
  47
  48 int
  49 rte_pmd_ixgbe_ping_vf(uint16_t port, uint16_t vf)
  50 {
  51         struct ixgbe_hw *hw;
  52         struct ixgbe_vf_info *vfinfo;
  53         struct rte_eth_dev *dev;
  54         struct rte_pci_device *pci_dev;
  55         uint32_t ctrl;
  56
  57         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
  58
  59         dev = &rte_eth_devices[port];
  60         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
  61
  62         if (!is_ixgbe_supported(dev))
  63                 return -ENOTSUP;
  64
  65         if (vf >= pci_dev->max_vfs)
  66                 return -EINVAL;
  67
  68         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
  69         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
  70
  71         ctrl = IXGBE_PF_CONTROL_MSG;
  72         if (vfinfo[vf].clear_to_send)
  73                 ctrl |= IXGBE_VT_MSGTYPE_CTS;
  74
  75         ixgbe_write_mbx(hw, &ctrl, 1, vf);
  76
  77         return 0;
  78 }
  79
  80 int
  81 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint16_t port, uint16_t vf, uint8_t on)
  82 {
  83         struct ixgbe_hw *hw;
  84         struct ixgbe_mac_info *mac;
  85         struct rte_eth_dev *dev;
  86         struct rte_pci_device *pci_dev;
  87
  88         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
  89
  90         dev = &rte_eth_devices[port];
  91         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
  92
  93         if (!is_ixgbe_supported(dev))
  94                 return -ENOTSUP;
  95
  96         if (vf >= pci_dev->max_vfs)
  97                 return -EINVAL;
  98
  99         if (on > 1)
 100                 return -EINVAL;
 101
 102         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 103         mac = &hw->mac;
 104
 105         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
 106
 107         return 0;
 108 }
 109
 110 int
 111 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint16_t port, uint16_t vf, uint8_t on)
 112 {
 113         struct ixgbe_hw *hw;
 114         struct ixgbe_mac_info *mac;
 115         struct rte_eth_dev *dev;
 116         struct rte_pci_device *pci_dev;
 117
 118         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 119
 120         dev = &rte_eth_devices[port];
 121         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 122
 123         if (!is_ixgbe_supported(dev))
 124                 return -ENOTSUP;
 125
 126         if (vf >= pci_dev->max_vfs)
 127                 return -EINVAL;
 128
 129         if (on > 1)
 130                 return -EINVAL;
 131
 132         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 133         mac = &hw->mac;
 134         mac->ops.set_mac_anti_spoofing(hw, on, vf);
 135
 136         return 0;
 137 }
 138
 139 int
 140 rte_pmd_ixgbe_set_vf_vlan_insert(uint16_t port, uint16_t vf, uint16_t vlan_id)
 141 {
 142         struct ixgbe_hw *hw;
 143         uint32_t ctrl;
 144         struct rte_eth_dev *dev;
 145         struct rte_pci_device *pci_dev;
 146
 147         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 148
 149         dev = &rte_eth_devices[port];
 150         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 151
 152         if (!is_ixgbe_supported(dev))
 153                 return -ENOTSUP;
 154
 155         if (vf >= pci_dev->max_vfs)
 156                 return -EINVAL;
 157
 158         if (vlan_id > RTE_ETHER_MAX_VLAN_ID)
 159                 return -EINVAL;
 160
 161         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 162         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
 163         if (vlan_id) {
 164                 ctrl = vlan_id;
 165                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
 166         } else {
 167                 ctrl = 0;
 168         }
 169
 170         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
 171
 172         return 0;
 173 }
 174
 175 int
 176 rte_pmd_ixgbe_set_tx_loopback(uint16_t port, uint8_t on)
 177 {
 178         struct ixgbe_hw *hw;
 179         uint32_t ctrl;
 180         struct rte_eth_dev *dev;
 181
 182         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 183
 184         dev = &rte_eth_devices[port];
 185
 186         if (!is_ixgbe_supported(dev))
 187                 return -ENOTSUP;
 188
 189         if (on > 1)
 190                 return -EINVAL;
 191
 192         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 193         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
 194         /* enable or disable VMDQ loopback */
 195         if (on)
 196                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
 197         else
 198                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
 199
 200         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
 201
 202         return 0;
 203 }
 204
 205 int
 206 rte_pmd_ixgbe_set_all_queues_drop_en(uint16_t port, uint8_t on)
 207 {
 208         struct ixgbe_hw *hw;
 209         uint32_t reg_value;
 210         int i;
 211         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
 212         struct rte_eth_dev *dev;
 213
 214         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 215
 216         dev = &rte_eth_devices[port];
 217
 218         if (!is_ixgbe_supported(dev))
 219                 return -ENOTSUP;
 220
 221         if (on > 1)
 222                 return -EINVAL;
 223
 224         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 225         for (i = 0; i <= num_queues; i++) {
 226                 reg_value = IXGBE_QDE_WRITE |
 227                                 (i << IXGBE_QDE_IDX_SHIFT) |
 228                                 (on & IXGBE_QDE_ENABLE);
 229                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
 230         }
 231
 232         return 0;
 233 }
 234
 235 int
 236 rte_pmd_ixgbe_set_vf_split_drop_en(uint16_t port, uint16_t vf, uint8_t on)
 237 {
 238         struct ixgbe_hw *hw;
 239         uint32_t reg_value;
 240         struct rte_eth_dev *dev;
 241         struct rte_pci_device *pci_dev;
 242
 243         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 244
 245         dev = &rte_eth_devices[port];
 246         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 247
 248         if (!is_ixgbe_supported(dev))
 249                 return -ENOTSUP;
 250
 251         /* only support VF's 0 to 63 */
 252         if ((vf >= pci_dev->max_vfs) || (vf > 63))
 253                 return -EINVAL;
 254
 255         if (on > 1)
 256                 return -EINVAL;
 257
 258         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 259         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
 260         if (on)
 261                 reg_value |= IXGBE_SRRCTL_DROP_EN;
 262         else
 263                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
 264
 265         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
 266
 267         return 0;
 268 }
 269
 270 int
 271 rte_pmd_ixgbe_set_vf_vlan_stripq(uint16_t port, uint16_t vf, uint8_t on)
 272 {
 273         struct rte_eth_dev *dev;
 274         struct rte_pci_device *pci_dev;
 275         struct ixgbe_hw *hw;
 276         uint16_t queues_per_pool;
 277         uint32_t q;
 278
 279         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 280
 281         dev = &rte_eth_devices[port];
 282         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 283         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 284
 285         if (!is_ixgbe_supported(dev))
 286                 return -ENOTSUP;
 287
 288         if (vf >= pci_dev->max_vfs)
 289                 return -EINVAL;
 290
 291         if (on > 1)
 292                 return -EINVAL;
 293
 294         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
 295
 296         /* The PF has 128 queue pairs and in SRIOV configuration
 297          * those queues will be assigned to VF's, so RXDCTL
 298          * registers will be dealing with queues which will be
 299          * assigned to VF's.
 300          * Let's say we have SRIOV configured with 31 VF's then the
 301          * first 124 queues 0-123 will be allocated to VF's and only
 302          * the last 4 queues 123-127 will be assigned to the PF.
 303          */
 304         if (hw->mac.type == ixgbe_mac_82598EB)
 305                 queues_per_pool = (uint16_t)hw->mac.max_rx_queues /
 306                                   ETH_16_POOLS;
 307         else
 308                 queues_per_pool = (uint16_t)hw->mac.max_rx_queues /
 309                                   ETH_64_POOLS;
 310
 311         for (q = 0; q < queues_per_pool; q++)
 312                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
 313                                 q + vf * queues_per_pool, on);
 314         return 0;
 315 }
 316
 317 int
 318 rte_pmd_ixgbe_set_vf_rxmode(uint16_t port, uint16_t vf,
 319                             uint16_t rx_mask, uint8_t on)
 320 {
 321         int val = 0;
 322         struct rte_eth_dev *dev;
 323         struct rte_pci_device *pci_dev;
 324         struct ixgbe_hw *hw;
 325         uint32_t vmolr;
 326
 327         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 328
 329         dev = &rte_eth_devices[port];
 330         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 331
 332         if (!is_ixgbe_supported(dev))
 333                 return -ENOTSUP;
 334
 335         if (vf >= pci_dev->max_vfs)
 336                 return -EINVAL;
 337
 338         if (on > 1)
 339                 return -EINVAL;
 340
 341         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 342         vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
 343
 344         if (hw->mac.type == ixgbe_mac_82598EB) {
 345                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
 346                              " on 82599 hardware and newer");
 347                 return -ENOTSUP;
 348         }
 349         if (ixgbe_vt_check(hw) < 0)
 350                 return -ENOTSUP;
 351
 352         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
 353
 354         if (on)
 355                 vmolr |= val;
 356         else
 357                 vmolr &= ~val;
 358
 359         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
 360
 361         return 0;
 362 }
 363
 364 int
 365 rte_pmd_ixgbe_set_vf_rx(uint16_t port, uint16_t vf, uint8_t on)
 366 {
 367         struct rte_eth_dev *dev;
 368         struct rte_pci_device *pci_dev;
 369         uint32_t reg, addr;
 370         uint32_t val;
 371         const uint8_t bit1 = 0x1;
 372         struct ixgbe_hw *hw;
 373
 374         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 375
 376         dev = &rte_eth_devices[port];
 377         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 378
 379         if (!is_ixgbe_supported(dev))
 380                 return -ENOTSUP;
 381
 382         if (vf >= pci_dev->max_vfs)
 383                 return -EINVAL;
 384
 385         if (on > 1)
 386                 return -EINVAL;
 387
 388         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 389
 390         if (ixgbe_vt_check(hw) < 0)
 391                 return -ENOTSUP;
 392
 393         /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
 394         if (vf >= 32) {
 395                 addr = IXGBE_VFRE(1);
 396                 val = bit1 << (vf - 32);
 397         } else {
 398                 addr = IXGBE_VFRE(0);
 399                 val = bit1 << vf;
 400         }
 401
 402         reg = IXGBE_READ_REG(hw, addr);
 403
 404         if (on)
 405                 reg |= val;
 406         else
 407                 reg &= ~val;
 408
 409         IXGBE_WRITE_REG(hw, addr, reg);
 410
 411         return 0;
 412 }
 413
 414 int
 415 rte_pmd_ixgbe_set_vf_tx(uint16_t port, uint16_t vf, uint8_t on)
 416 {
 417         struct rte_eth_dev *dev;
 418         struct rte_pci_device *pci_dev;
 419         uint32_t reg, addr;
 420         uint32_t val;
 421         const uint8_t bit1 = 0x1;
 422
 423         struct ixgbe_hw *hw;
 424
 425         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 426
 427         dev = &rte_eth_devices[port];
 428         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 429
 430         if (!is_ixgbe_supported(dev))
 431                 return -ENOTSUP;
 432
 433         if (vf >= pci_dev->max_vfs)
 434                 return -EINVAL;
 435
 436         if (on > 1)
 437                 return -EINVAL;
 438
 439         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 440         if (ixgbe_vt_check(hw) < 0)
 441                 return -ENOTSUP;
 442
 443         /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
 444         if (vf >= 32) {
 445                 addr = IXGBE_VFTE(1);
 446                 val = bit1 << (vf - 32);
 447         } else {
 448                 addr = IXGBE_VFTE(0);
 449                 val = bit1 << vf;
 450         }
 451
 452         reg = IXGBE_READ_REG(hw, addr);
 453
 454         if (on)
 455                 reg |= val;
 456         else
 457                 reg &= ~val;
 458
 459         IXGBE_WRITE_REG(hw, addr, reg);
 460
 461         return 0;
 462 }
 463
 464 int
 465 rte_pmd_ixgbe_set_vf_vlan_filter(uint16_t port, uint16_t vlan,
 466                                  uint64_t vf_mask, uint8_t vlan_on)
 467 {
 468         struct rte_eth_dev *dev;
 469         int ret = 0;
 470         uint16_t vf_idx;
 471         struct ixgbe_hw *hw;
 472
 473         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 474
 475         dev = &rte_eth_devices[port];
 476
 477         if (!is_ixgbe_supported(dev))
 478                 return -ENOTSUP;
 479
 480         if (vlan > RTE_ETHER_MAX_VLAN_ID || vf_mask == 0)
 481                 return -EINVAL;
 482
 483         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 484         if (ixgbe_vt_check(hw) < 0)
 485                 return -ENOTSUP;
 486
 487         for (vf_idx = 0; vf_idx < 64; vf_idx++) {
 488                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
 489                         ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
 490                                                    vlan_on, false);
 491                         if (ret < 0)
 492                                 return ret;
 493                 }
 494         }
 495
 496         return ret;
 497 }
 498
 499 int
 500 rte_pmd_ixgbe_set_vf_rate_limit(uint16_t port, uint16_t vf,
 501                                 uint16_t tx_rate, uint64_t q_msk)
 502 {
 503         struct rte_eth_dev *dev;
 504
 505         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 506
 507         dev = &rte_eth_devices[port];
 508
 509         if (!is_ixgbe_supported(dev))
 510                 return -ENOTSUP;
 511
 512         return ixgbe_set_vf_rate_limit(dev, vf, tx_rate, q_msk);
 513 }
 514
 515 int
 516 rte_pmd_ixgbe_macsec_enable(uint16_t port, uint8_t en, uint8_t rp)
 517 {
 518         struct rte_eth_dev *dev;
 519         struct ixgbe_macsec_setting macsec_setting;
 520
 521         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 522
 523         dev = &rte_eth_devices[port];
 524
 525         macsec_setting.offload_en = 1;
 526         macsec_setting.encrypt_en = en;
 527         macsec_setting.replayprotect_en = rp;
 528
 529         ixgbe_dev_macsec_setting_save(dev, &macsec_setting);
 530
 531         ixgbe_dev_macsec_register_enable(dev, &macsec_setting);
 532
 533         return 0;
 534 }
 535
 536 int
 537 rte_pmd_ixgbe_macsec_disable(uint16_t port)
 538 {
 539         struct rte_eth_dev *dev;
 540
 541         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 542
 543         dev = &rte_eth_devices[port];
 544
 545         ixgbe_dev_macsec_setting_reset(dev);
 546
 547         ixgbe_dev_macsec_register_disable(dev);
 548
 549         return 0;
 550 }
 551
 552 int
 553 rte_pmd_ixgbe_macsec_config_txsc(uint16_t port, uint8_t *mac)
 554 {
 555         struct ixgbe_hw *hw;
 556         struct rte_eth_dev *dev;
 557         uint32_t ctrl;
 558
 559         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 560
 561         dev = &rte_eth_devices[port];
 562
 563         if (!is_ixgbe_supported(dev))
 564                 return -ENOTSUP;
 565
 566         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 567
 568         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
 569         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
 570
 571         ctrl = mac[4] | (mac[5] << 8);
 572         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
 573
 574         return 0;
 575 }
 576
 577 int
 578 rte_pmd_ixgbe_macsec_config_rxsc(uint16_t port, uint8_t *mac, uint16_t pi)
 579 {
 580         struct ixgbe_hw *hw;
 581         struct rte_eth_dev *dev;
 582         uint32_t ctrl;
 583
 584         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 585
 586         dev = &rte_eth_devices[port];
 587
 588         if (!is_ixgbe_supported(dev))
 589                 return -ENOTSUP;
 590
 591         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 592
 593         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
 594         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
 595
 596         pi = rte_cpu_to_be_16(pi);
 597         ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
 598         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
 599
 600         return 0;
 601 }
 602
 603 int
 604 rte_pmd_ixgbe_macsec_select_txsa(uint16_t port, uint8_t idx, uint8_t an,
 605                                  uint32_t pn, uint8_t *key)
 606 {
 607         struct ixgbe_hw *hw;
 608         struct rte_eth_dev *dev;
 609         uint32_t ctrl, i;
 610
 611         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 612
 613         dev = &rte_eth_devices[port];
 614
 615         if (!is_ixgbe_supported(dev))
 616                 return -ENOTSUP;
 617
 618         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 619
 620         if (idx != 0 && idx != 1)
 621                 return -EINVAL;
 622
 623         if (an >= 4)
 624                 return -EINVAL;
 625
 626         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 627
 628         /* Set the PN and key */
 629         pn = rte_cpu_to_be_32(pn);
 630         if (idx == 0) {
 631                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
 632
 633                 for (i = 0; i < 4; i++) {
 634                         ctrl = (key[i * 4 + 0] <<  0) |
 635                                (key[i * 4 + 1] <<  8) |
 636                                (key[i * 4 + 2] << 16) |
 637                                (key[i * 4 + 3] << 24);
 638                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
 639                 }
 640         } else {
 641                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
 642
 643                 for (i = 0; i < 4; i++) {
 644                         ctrl = (key[i * 4 + 0] <<  0) |
 645                                (key[i * 4 + 1] <<  8) |
 646                                (key[i * 4 + 2] << 16) |
 647                                (key[i * 4 + 3] << 24);
 648                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
 649                 }
 650         }
 651
 652         /* Set AN and select the SA */
 653         ctrl = (an << idx * 2) | (idx << 4);
 654         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
 655
 656         return 0;
 657 }
 658
 659 int
 660 rte_pmd_ixgbe_macsec_select_rxsa(uint16_t port, uint8_t idx, uint8_t an,
 661                                  uint32_t pn, uint8_t *key)
 662 {
 663         struct ixgbe_hw *hw;
 664         struct rte_eth_dev *dev;
 665         uint32_t ctrl, i;
 666
 667         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 668
 669         dev = &rte_eth_devices[port];
 670
 671         if (!is_ixgbe_supported(dev))
 672                 return -ENOTSUP;
 673
 674         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 675
 676         if (idx != 0 && idx != 1)
 677                 return -EINVAL;
 678
 679         if (an >= 4)
 680                 return -EINVAL;
 681
 682         /* Set the PN */
 683         pn = rte_cpu_to_be_32(pn);
 684         IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
 685
 686         /* Set the key */
 687         for (i = 0; i < 4; i++) {
 688                 ctrl = (key[i * 4 + 0] <<  0) |
 689                        (key[i * 4 + 1] <<  8) |
 690                        (key[i * 4 + 2] << 16) |
 691                        (key[i * 4 + 3] << 24);
 692                 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
 693         }
 694
 695         /* Set the AN and validate the SA */
 696         ctrl = an | (1 << 2);
 697         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
 698
 699         return 0;
 700 }
 701
 702 int
 703 rte_pmd_ixgbe_set_tc_bw_alloc(uint16_t port,
 704                               uint8_t tc_num,
 705                               uint8_t *bw_weight)
 706 {
 707         struct rte_eth_dev *dev;
 708         struct ixgbe_dcb_config *dcb_config;
 709         struct ixgbe_dcb_tc_config *tc;
 710         struct rte_eth_conf *eth_conf;
 711         struct ixgbe_bw_conf *bw_conf;
 712         uint8_t i;
 713         uint8_t nb_tcs;
 714         uint16_t sum;
 715
 716         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 717
 718         dev = &rte_eth_devices[port];
 719
 720         if (!is_ixgbe_supported(dev))
 721                 return -ENOTSUP;
 722
 723         if (tc_num > IXGBE_DCB_MAX_TRAFFIC_CLASS) {
 724                 PMD_DRV_LOG(ERR, "TCs should be no more than %d.",
 725                             IXGBE_DCB_MAX_TRAFFIC_CLASS);
 726                 return -EINVAL;
 727         }
 728
 729         dcb_config = IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
 730         bw_conf = IXGBE_DEV_PRIVATE_TO_BW_CONF(dev->data->dev_private);
 731         eth_conf = &dev->data->dev_conf;
 732
 733         if (eth_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
 734                 nb_tcs = eth_conf->tx_adv_conf.dcb_tx_conf.nb_tcs;
 735         } else if (eth_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
 736                 if (eth_conf->tx_adv_conf.vmdq_dcb_tx_conf.nb_queue_pools ==
 737                     ETH_32_POOLS)
 738                         nb_tcs = ETH_4_TCS;
 739                 else
 740                         nb_tcs = ETH_8_TCS;
 741         } else {
 742                 nb_tcs = 1;
 743         }
 744
 745         if (nb_tcs != tc_num) {
 746                 PMD_DRV_LOG(ERR,
 747                             "Weight should be set for all %d enabled TCs.",
 748                             nb_tcs);
 749                 return -EINVAL;
 750         }
 751
 752         sum = 0;
 753         for (i = 0; i < nb_tcs; i++)
 754                 sum += bw_weight[i];
 755         if (sum != 100) {
 756                 PMD_DRV_LOG(ERR,
 757                             "The summary of the TC weight should be 100.");
 758                 return -EINVAL;
 759         }
 760
 761         for (i = 0; i < nb_tcs; i++) {
 762                 tc = &dcb_config->tc_config[i];
 763                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = bw_weight[i];
 764         }
 765         for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 766                 tc = &dcb_config->tc_config[i];
 767                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
 768         }
 769
 770         bw_conf->tc_num = nb_tcs;
 771
 772         return 0;
 773 }
 774
 775 int
 776 rte_pmd_ixgbe_upd_fctrl_sbp(uint16_t port, int enable)
 777 {
 778         struct ixgbe_hw *hw;
 779         struct rte_eth_dev *dev;
 780         uint32_t fctrl;
 781
 782         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 783         dev = &rte_eth_devices[port];
 784         if (!is_ixgbe_supported(dev))
 785                 return -ENOTSUP;
 786
 787         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 788         if (!hw)
 789                 return -ENOTSUP;
 790
 791         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
 792
 793         /* If 'enable' set the SBP bit else clear it */
 794         if (enable)
 795                 fctrl |= IXGBE_FCTRL_SBP;
 796         else
 797                 fctrl &= ~(IXGBE_FCTRL_SBP);
 798
 799         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
 800         return 0;
 801 }
 802
 803 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 804 int
 805 rte_pmd_ixgbe_bypass_init(uint16_t port_id)
 806 {
 807         struct rte_eth_dev *dev;
 808
 809         RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
 810
 811         dev = &rte_eth_devices[port_id];
 812         if (!is_ixgbe_supported(dev))
 813                 return -ENOTSUP;
 814
 815         ixgbe_bypass_init(dev);
 816         return 0;
 817 }
 818
 819 int
 820 rte_pmd_ixgbe_bypass_state_show(uint16_t port_id, uint32_t *state)
 821 {
 822         struct rte_eth_dev *dev;
 823
 824         RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
 825
 826         dev = &rte_eth_devices[port_id];
 827         if (!is_ixgbe_supported(dev))
 828                 return -ENOTSUP;
 829
 830         return ixgbe_bypass_state_show(dev, state);
 831 }
 832
 833 int
 834 rte_pmd_ixgbe_bypass_state_set(uint16_t port_id, uint32_t *new_state)
 835 {
 836         struct rte_eth_dev *dev;
 837
 838         RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
 839
 840         dev = &rte_eth_devices[port_id];
 841         if (!is_ixgbe_supported(dev))
 842                 return -ENOTSUP;
 843
 844         return ixgbe_bypass_state_store(dev, new_state);
 845 }
 846
 847 int
 848 rte_pmd_ixgbe_bypass_event_show(uint16_t port_id,
 849                                 uint32_t event,
 850                                 uint32_t *state)
 851 {
 852         struct rte_eth_dev *dev;
 853
 854         RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
 855
 856         dev = &rte_eth_devices[port_id];
 857         if (!is_ixgbe_supported(dev))
 858                 return -ENOTSUP;
 859
 860         return ixgbe_bypass_event_show(dev, event, state);
 861 }
 862
 863 int
 864 rte_pmd_ixgbe_bypass_event_store(uint16_t port_id,
 865                                  uint32_t event,
 866                                  uint32_t state)
 867 {
 868         struct rte_eth_dev *dev;
 869
 870         RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
 871
 872         dev = &rte_eth_devices[port_id];
 873         if (!is_ixgbe_supported(dev))
 874                 return -ENOTSUP;
 875
 876         return ixgbe_bypass_event_store(dev, event, state);
 877 }
 878
 879 int
 880 rte_pmd_ixgbe_bypass_wd_timeout_store(uint16_t port_id, uint32_t timeout)
 881 {
 882         struct rte_eth_dev *dev;
 883
 884         RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
 885
 886         dev = &rte_eth_devices[port_id];
 887         if (!is_ixgbe_supported(dev))
 888                 return -ENOTSUP;
 889
 890         return ixgbe_bypass_wd_timeout_store(dev, timeout);
 891 }
 892
 893 int
 894 rte_pmd_ixgbe_bypass_ver_show(uint16_t port_id, uint32_t *ver)
 895 {
 896         struct rte_eth_dev *dev;
 897
 898         RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
 899
 900         dev = &rte_eth_devices[port_id];
 901         if (!is_ixgbe_supported(dev))
 902                 return -ENOTSUP;
 903
 904         return ixgbe_bypass_ver_show(dev, ver);
 905 }
 906
 907 int
 908 rte_pmd_ixgbe_bypass_wd_timeout_show(uint16_t port_id, uint32_t *wd_timeout)
 909 {
 910         struct rte_eth_dev *dev;
 911
 912         RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
 913
 914         dev = &rte_eth_devices[port_id];
 915         if (!is_ixgbe_supported(dev))
 916                 return -ENOTSUP;
 917
 918         return ixgbe_bypass_wd_timeout_show(dev, wd_timeout);
 919 }
 920
 921 int
 922 rte_pmd_ixgbe_bypass_wd_reset(uint16_t port_id)
 923 {
 924         struct rte_eth_dev *dev;
 925
 926         RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
 927
 928         dev = &rte_eth_devices[port_id];
 929         if (!is_ixgbe_supported(dev))
 930                 return -ENOTSUP;
 931
 932         return ixgbe_bypass_wd_reset(dev);
 933 }
 934 #endif
 935
 936 /**
 937  *  rte_pmd_ixgbe_acquire_swfw - Acquire SWFW semaphore
 938  *  @hw: pointer to hardware structure
 939  *  @mask: Mask to specify which semaphore to acquire
 940  *
 941  *  Acquires the SWFW semaphore and get the shared phy token as needed
 942  */
 943 STATIC s32 rte_pmd_ixgbe_acquire_swfw(struct ixgbe_hw *hw, u32 mask)
 944 {
 945         int retries = FW_PHY_TOKEN_RETRIES;
 946         s32 status = IXGBE_SUCCESS;
 947
 948         while (--retries) {
 949                 status = ixgbe_acquire_swfw_semaphore(hw, mask);
 950                 if (status) {
 951                         PMD_DRV_LOG(ERR, "Get SWFW sem failed, Status = %d\n",
 952                                     status);
 953                         return status;
 954                 }
 955                 status = ixgbe_get_phy_token(hw);
 956                 if (status == IXGBE_SUCCESS)
 957                         return IXGBE_SUCCESS;
 958
 959                 if (status == IXGBE_ERR_TOKEN_RETRY)
 960                         PMD_DRV_LOG(ERR, "Get PHY token failed, Status = %d\n",
 961                                     status);
 962
 963                 ixgbe_release_swfw_semaphore(hw, mask);
 964                 if (status != IXGBE_ERR_TOKEN_RETRY) {
 965                         PMD_DRV_LOG(ERR,
 966                                     "Retry get PHY token failed, Status=%d\n",
 967                                     status);
 968                         return status;
 969                 }
 970         }
 971         PMD_DRV_LOG(ERR, "swfw acquisition retries failed!: PHY ID = 0x%08X\n",
 972                     hw->phy.id);
 973         return status;
 974 }
 975
 976 /**
 977  *  rte_pmd_ixgbe_release_swfw_sync - Release SWFW semaphore
 978  *  @hw: pointer to hardware structure
 979  *  @mask: Mask to specify which semaphore to release
 980  *
 981  *  Releases the SWFW semaphore and puts the shared phy token as needed
 982  */
 983 STATIC void rte_pmd_ixgbe_release_swfw(struct ixgbe_hw *hw, u32 mask)
 984 {
 985         ixgbe_put_phy_token(hw);
 986         ixgbe_release_swfw_semaphore(hw, mask);
 987 }
 988
 989 int
 990 rte_pmd_ixgbe_mdio_lock(uint16_t port)
 991 {
 992         struct ixgbe_hw *hw;
 993         struct rte_eth_dev *dev;
 994         u32 swfw_mask;
 995
 996         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 997         dev = &rte_eth_devices[port];
 998         if (!is_ixgbe_supported(dev))
 999                 return -ENOTSUP;
1000
1001         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1002         if (!hw)
1003                 return -ENOTSUP;
1004
1005         if (hw->bus.lan_id)
1006                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1007         else
1008                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1009
1010         if (rte_pmd_ixgbe_acquire_swfw(hw, swfw_mask))
1011                 return IXGBE_ERR_SWFW_SYNC;
1012
1013         return IXGBE_SUCCESS;
1014 }
1015
1016 int
1017 rte_pmd_ixgbe_mdio_unlock(uint16_t port)
1018 {
1019         struct rte_eth_dev *dev;
1020         struct ixgbe_hw *hw;
1021         u32 swfw_mask;
1022
1023         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1024
1025         dev = &rte_eth_devices[port];
1026         if (!is_ixgbe_supported(dev))
1027                 return -ENOTSUP;
1028
1029         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1030         if (!hw)
1031                 return -ENOTSUP;
1032
1033         if (hw->bus.lan_id)
1034                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1035         else
1036                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1037
1038         rte_pmd_ixgbe_release_swfw(hw, swfw_mask);
1039
1040         return IXGBE_SUCCESS;
1041 }
1042
1043 int
1044 rte_pmd_ixgbe_mdio_unlocked_read(uint16_t port, uint32_t reg_addr,
1045                                  uint32_t dev_type, uint16_t *phy_data)
1046 {
1047         struct ixgbe_hw *hw;
1048         struct rte_eth_dev *dev;
1049         u32 i, data, command;
1050
1051         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1052         dev = &rte_eth_devices[port];
1053         if (!is_ixgbe_supported(dev))
1054                 return -ENOTSUP;
1055
1056         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1057         if (!hw)
1058                 return -ENOTSUP;
1059
1060         /* Setup and write the read command */
1061         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
1062                   (dev_type << IXGBE_MSCA_PHY_ADDR_SHIFT) |
1063                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC |
1064                   IXGBE_MSCA_MDI_COMMAND;
1065
1066         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
1067
1068         /* Check every 10 usec to see if the access completed.
1069          * The MDI Command bit will clear when the operation is
1070          * complete
1071          */
1072         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1073                 usec_delay(10);
1074
1075                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
1076                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
1077                         break;
1078         }
1079         if (command & IXGBE_MSCA_MDI_COMMAND)
1080                 return IXGBE_ERR_PHY;
1081
1082         /* Read operation is complete.  Get the data from MSRWD */
1083         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
1084         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
1085         *phy_data = (u16)data;
1086
1087         return 0;
1088 }
1089
1090 int
1091 rte_pmd_ixgbe_mdio_unlocked_write(uint16_t port, uint32_t reg_addr,
1092                                   uint32_t dev_type, uint16_t phy_data)
1093 {
1094         struct ixgbe_hw *hw;
1095         u32 i, command;
1096         struct rte_eth_dev *dev;
1097
1098         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1099         dev = &rte_eth_devices[port];
1100         if (!is_ixgbe_supported(dev))
1101                 return -ENOTSUP;
1102
1103         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1104         if (!hw)
1105                 return -ENOTSUP;
1106
1107         /* Put the data in the MDI single read and write data register*/
1108         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
1109
1110         /* Setup and write the write command */
1111         command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
1112                   (dev_type << IXGBE_MSCA_PHY_ADDR_SHIFT) |
1113                   IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
1114                   IXGBE_MSCA_MDI_COMMAND;
1115
1116         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
1117
1118         /* Check every 10 usec to see if the access completed.
1119          * The MDI Command bit will clear when the operation is
1120          * complete
1121          */
1122         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1123                 usec_delay(10);
1124
1125                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
1126                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
1127                         break;
1128         }
1129         if (command & IXGBE_MSCA_MDI_COMMAND) {
1130                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1131                               "PHY write cmd didn't complete\n");
1132                 return IXGBE_ERR_PHY;
1133         }
1134         return 0;
1135 }