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34 #include <rte_ethdev.h>
35 #include <rte_cycles.h>
36 #include <rte_malloc.h>
39 #include "lio_23xx_vf.h"
40 #include "lio_23xx_reg.h"
44 cn23xx_vf_reset_io_queues(struct lio_device *lio_dev, uint32_t num_queues)
46 uint32_t loop = CN23XX_VF_BUSY_READING_REG_LOOP_COUNT;
50 PMD_INIT_FUNC_TRACE();
52 for (q_no = 0; q_no < num_queues; q_no++) {
53 /* set RST bit to 1. This bit applies to both IQ and OQ */
54 d64 = lio_read_csr64(lio_dev,
55 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
56 d64 = d64 | CN23XX_PKT_INPUT_CTL_RST;
57 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
61 /* wait until the RST bit is clear or the RST and QUIET bits are set */
62 for (q_no = 0; q_no < num_queues; q_no++) {
63 volatile uint64_t reg_val;
65 reg_val = lio_read_csr64(lio_dev,
66 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
67 while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) &&
68 !(reg_val & CN23XX_PKT_INPUT_CTL_QUIET) &&
70 reg_val = lio_read_csr64(
72 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
78 "clearing the reset reg failed or setting the quiet reg failed for qno: %lu\n",
83 reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST;
84 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
87 reg_val = lio_read_csr64(
88 lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
89 if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {
91 "clearing the reset failed for qno: %lu\n",
101 cn23xx_vf_setup_global_input_regs(struct lio_device *lio_dev)
106 PMD_INIT_FUNC_TRACE();
108 if (cn23xx_vf_reset_io_queues(lio_dev,
109 lio_dev->sriov_info.rings_per_vf))
112 for (q_no = 0; q_no < (lio_dev->sriov_info.rings_per_vf); q_no++) {
113 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_DOORBELL(q_no),
116 d64 = lio_read_csr64(lio_dev,
117 CN23XX_SLI_IQ_INSTR_COUNT64(q_no));
119 d64 &= 0xEFFFFFFFFFFFFFFFL;
121 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_INSTR_COUNT64(q_no),
124 /* Select ES, RO, NS, RDSIZE,DPTR Fomat#0 for
127 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
128 CN23XX_PKT_INPUT_CTL_MASK);
135 cn23xx_vf_setup_global_output_regs(struct lio_device *lio_dev)
140 PMD_INIT_FUNC_TRACE();
142 for (q_no = 0; q_no < lio_dev->sriov_info.rings_per_vf; q_no++) {
143 lio_write_csr(lio_dev, CN23XX_SLI_OQ_PKTS_CREDIT(q_no),
147 lio_read_csr(lio_dev, CN23XX_SLI_OQ_PKTS_SENT(q_no));
149 reg_val &= 0xEFFFFFFFFFFFFFFFL;
152 lio_read_csr(lio_dev, CN23XX_SLI_OQ_PKT_CONTROL(q_no));
154 /* set IPTR & DPTR */
156 (CN23XX_PKT_OUTPUT_CTL_IPTR | CN23XX_PKT_OUTPUT_CTL_DPTR);
159 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_BMODE);
161 /* No Relaxed Ordering, No Snoop, 64-bit Byte swap
162 * for Output Queue Scatter List
165 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR_P);
166 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR_P);
168 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
169 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ES_P);
170 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
171 reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES_P);
173 /* No Relaxed Ordering, No Snoop, 64-bit Byte swap
174 * for Output Queue Data
177 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR);
178 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR);
180 reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES);
182 /* write all the selected settings */
183 lio_write_csr(lio_dev, CN23XX_SLI_OQ_PKT_CONTROL(q_no),
189 cn23xx_vf_setup_device_regs(struct lio_device *lio_dev)
191 PMD_INIT_FUNC_TRACE();
193 if (cn23xx_vf_setup_global_input_regs(lio_dev))
196 cn23xx_vf_setup_global_output_regs(lio_dev);
202 cn23xx_vf_setup_iq_regs(struct lio_device *lio_dev, uint32_t iq_no)
204 struct lio_instr_queue *iq = lio_dev->instr_queue[iq_no];
205 uint64_t pkt_in_done = 0;
207 PMD_INIT_FUNC_TRACE();
209 /* Write the start of the input queue's ring and its size */
210 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_BASE_ADDR64(iq_no),
212 lio_write_csr(lio_dev, CN23XX_SLI_IQ_SIZE(iq_no), iq->max_count);
214 /* Remember the doorbell & instruction count register addr
217 iq->doorbell_reg = (uint8_t *)lio_dev->hw_addr +
218 CN23XX_SLI_IQ_DOORBELL(iq_no);
219 iq->inst_cnt_reg = (uint8_t *)lio_dev->hw_addr +
220 CN23XX_SLI_IQ_INSTR_COUNT64(iq_no);
221 lio_dev_dbg(lio_dev, "InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p\n",
222 iq_no, iq->doorbell_reg, iq->inst_cnt_reg);
224 /* Store the current instruction counter (used in flush_iq
227 pkt_in_done = rte_read64(iq->inst_cnt_reg);
229 /* Clear the count by writing back what we read, but don't
230 * enable data traffic here
232 rte_write64(pkt_in_done, iq->inst_cnt_reg);
236 cn23xx_vf_setup_oq_regs(struct lio_device *lio_dev, uint32_t oq_no)
238 struct lio_droq *droq = lio_dev->droq[oq_no];
240 PMD_INIT_FUNC_TRACE();
242 lio_write_csr64(lio_dev, CN23XX_SLI_OQ_BASE_ADDR64(oq_no),
243 droq->desc_ring_dma);
244 lio_write_csr(lio_dev, CN23XX_SLI_OQ_SIZE(oq_no), droq->max_count);
246 lio_write_csr(lio_dev, CN23XX_SLI_OQ_BUFF_INFO_SIZE(oq_no),
247 (droq->buffer_size | (OCTEON_RH_SIZE << 16)));
249 /* Get the mapped address of the pkt_sent and pkts_credit regs */
250 droq->pkts_sent_reg = (uint8_t *)lio_dev->hw_addr +
251 CN23XX_SLI_OQ_PKTS_SENT(oq_no);
252 droq->pkts_credit_reg = (uint8_t *)lio_dev->hw_addr +
253 CN23XX_SLI_OQ_PKTS_CREDIT(oq_no);
257 cn23xx_vf_free_mbox(struct lio_device *lio_dev)
259 PMD_INIT_FUNC_TRACE();
261 rte_free(lio_dev->mbox[0]);
262 lio_dev->mbox[0] = NULL;
264 rte_free(lio_dev->mbox);
265 lio_dev->mbox = NULL;
269 cn23xx_vf_setup_mbox(struct lio_device *lio_dev)
271 struct lio_mbox *mbox;
273 PMD_INIT_FUNC_TRACE();
275 if (lio_dev->mbox == NULL) {
276 lio_dev->mbox = rte_zmalloc(NULL, sizeof(void *), 0);
277 if (lio_dev->mbox == NULL)
281 mbox = rte_zmalloc(NULL, sizeof(struct lio_mbox), 0);
283 rte_free(lio_dev->mbox);
284 lio_dev->mbox = NULL;
288 rte_spinlock_init(&mbox->lock);
290 mbox->lio_dev = lio_dev;
294 mbox->state = LIO_MBOX_STATE_IDLE;
296 /* VF mbox interrupt reg */
297 mbox->mbox_int_reg = (uint8_t *)lio_dev->hw_addr +
298 CN23XX_VF_SLI_PKT_MBOX_INT(0);
299 /* VF reads from SIG0 reg */
300 mbox->mbox_read_reg = (uint8_t *)lio_dev->hw_addr +
301 CN23XX_SLI_PKT_PF_VF_MBOX_SIG(0, 0);
302 /* VF writes into SIG1 reg */
303 mbox->mbox_write_reg = (uint8_t *)lio_dev->hw_addr +
304 CN23XX_SLI_PKT_PF_VF_MBOX_SIG(0, 1);
306 lio_dev->mbox[0] = mbox;
308 rte_write64(LIO_PFVFSIG, mbox->mbox_read_reg);
314 cn23xx_vf_ask_pf_to_do_flr(struct lio_device *lio_dev)
316 struct lio_mbox_cmd mbox_cmd;
318 mbox_cmd.msg.mbox_msg64 = 0;
319 mbox_cmd.msg.s.type = LIO_MBOX_REQUEST;
320 mbox_cmd.msg.s.resp_needed = 0;
321 mbox_cmd.msg.s.cmd = LIO_VF_FLR_REQUEST;
322 mbox_cmd.msg.s.len = 1;
324 mbox_cmd.recv_len = 0;
325 mbox_cmd.recv_status = 0;
329 lio_mbox_write(lio_dev, &mbox_cmd);
333 cn23xx_pfvf_hs_callback(struct lio_device *lio_dev,
334 struct lio_mbox_cmd *cmd, void *arg)
338 PMD_INIT_FUNC_TRACE();
340 rte_memcpy((uint8_t *)&lio_dev->pfvf_hsword, cmd->msg.s.params, 6);
341 if (cmd->recv_len > 1) {
342 struct lio_version *lio_ver = (struct lio_version *)cmd->data;
344 major = lio_ver->major;
348 rte_atomic64_set((rte_atomic64_t *)arg, major | 1);
352 cn23xx_pfvf_handshake(struct lio_device *lio_dev)
354 struct lio_mbox_cmd mbox_cmd;
355 struct lio_version *lio_ver = (struct lio_version *)&mbox_cmd.data[0];
356 uint32_t q_no, count = 0;
357 rte_atomic64_t status;
362 PMD_INIT_FUNC_TRACE();
364 /* Sending VF_ACTIVE indication to the PF driver */
365 lio_dev_dbg(lio_dev, "requesting info from PF\n");
367 mbox_cmd.msg.mbox_msg64 = 0;
368 mbox_cmd.msg.s.type = LIO_MBOX_REQUEST;
369 mbox_cmd.msg.s.resp_needed = 1;
370 mbox_cmd.msg.s.cmd = LIO_VF_ACTIVE;
371 mbox_cmd.msg.s.len = 2;
372 mbox_cmd.data[0] = 0;
373 lio_ver->major = LIO_BASE_MAJOR_VERSION;
374 lio_ver->minor = LIO_BASE_MINOR_VERSION;
375 lio_ver->micro = LIO_BASE_MICRO_VERSION;
377 mbox_cmd.recv_len = 0;
378 mbox_cmd.recv_status = 0;
379 mbox_cmd.fn = (lio_mbox_callback)cn23xx_pfvf_hs_callback;
380 mbox_cmd.fn_arg = (void *)&status;
382 if (lio_mbox_write(lio_dev, &mbox_cmd)) {
383 lio_dev_err(lio_dev, "Write to mailbox failed\n");
387 rte_atomic64_set(&status, 0);
391 } while ((rte_atomic64_read(&status) == 0) && (count++ < 10000));
393 ret = rte_atomic64_read(&status);
395 lio_dev_err(lio_dev, "cn23xx_pfvf_handshake timeout\n");
399 for (q_no = 0; q_no < lio_dev->num_iqs; q_no++)
400 lio_dev->instr_queue[q_no]->txpciq.s.pkind =
401 lio_dev->pfvf_hsword.pkind;
403 vfmajor = LIO_BASE_MAJOR_VERSION;
405 if (pfmajor != vfmajor) {
407 "VF LiquidIO driver (major version %d) is not compatible with LiquidIO PF driver (major version %d)\n",
412 "VF LiquidIO driver (major version %d), LiquidIO PF driver (major version %d)\n",
417 lio_dev_dbg(lio_dev, "got data from PF pkind is %d\n",
418 lio_dev->pfvf_hsword.pkind);
424 cn23xx_vf_handle_mbox(struct lio_device *lio_dev)
426 uint64_t mbox_int_val;
428 /* read and clear by writing 1 */
429 mbox_int_val = rte_read64(lio_dev->mbox[0]->mbox_int_reg);
430 rte_write64(mbox_int_val, lio_dev->mbox[0]->mbox_int_reg);
431 if (lio_mbox_read(lio_dev->mbox[0]))
432 lio_mbox_process_message(lio_dev->mbox[0]);
436 cn23xx_vf_setup_device(struct lio_device *lio_dev)
440 PMD_INIT_FUNC_TRACE();
442 /* INPUT_CONTROL[RPVF] gives the VF IOq count */
443 reg_val = lio_read_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(0));
445 lio_dev->pf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_PF_NUM_POS) &
446 CN23XX_PKT_INPUT_CTL_PF_NUM_MASK;
447 lio_dev->vf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_VF_NUM_POS) &
448 CN23XX_PKT_INPUT_CTL_VF_NUM_MASK;
450 reg_val = reg_val >> CN23XX_PKT_INPUT_CTL_RPVF_POS;
452 lio_dev->sriov_info.rings_per_vf =
453 reg_val & CN23XX_PKT_INPUT_CTL_RPVF_MASK;
455 lio_dev->default_config = lio_get_conf(lio_dev);
456 if (lio_dev->default_config == NULL)
459 lio_dev->fn_list.setup_iq_regs = cn23xx_vf_setup_iq_regs;
460 lio_dev->fn_list.setup_oq_regs = cn23xx_vf_setup_oq_regs;
461 lio_dev->fn_list.setup_mbox = cn23xx_vf_setup_mbox;
462 lio_dev->fn_list.free_mbox = cn23xx_vf_free_mbox;
464 lio_dev->fn_list.setup_device_regs = cn23xx_vf_setup_device_regs;
470 cn23xx_vf_set_io_queues_off(struct lio_device *lio_dev)
472 uint32_t loop = CN23XX_VF_BUSY_READING_REG_LOOP_COUNT;
475 /* Disable the i/p and o/p queues for this Octeon.
476 * IOQs will already be in reset.
477 * If RST bit is set, wait for Quiet bit to be set
478 * Once Quiet bit is set, clear the RST bit
480 PMD_INIT_FUNC_TRACE();
482 for (q_no = 0; q_no < lio_dev->sriov_info.rings_per_vf; q_no++) {
483 volatile uint64_t reg_val;
485 reg_val = lio_read_csr64(lio_dev,
486 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
487 while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) && !(reg_val &
488 CN23XX_PKT_INPUT_CTL_QUIET) && loop) {
489 reg_val = lio_read_csr64(
491 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
497 "clearing the reset reg failed or setting the quiet reg failed for qno %lu\n",
498 (unsigned long)q_no);
502 reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST;
503 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
506 reg_val = lio_read_csr64(lio_dev,
507 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
508 if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {
509 lio_dev_err(lio_dev, "unable to reset qno %lu\n",
510 (unsigned long)q_no);