4 * Copyright(c) 2017 Cavium, Inc.. All rights reserved.
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34 #include <rte_ethdev.h>
35 #include <rte_cycles.h>
36 #include <rte_malloc.h>
39 #include "lio_23xx_vf.h"
40 #include "lio_23xx_reg.h"
44 cn23xx_vf_reset_io_queues(struct lio_device *lio_dev, uint32_t num_queues)
46 uint32_t loop = CN23XX_VF_BUSY_READING_REG_LOOP_COUNT;
50 PMD_INIT_FUNC_TRACE();
52 for (q_no = 0; q_no < num_queues; q_no++) {
53 /* set RST bit to 1. This bit applies to both IQ and OQ */
54 d64 = lio_read_csr64(lio_dev,
55 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
56 d64 = d64 | CN23XX_PKT_INPUT_CTL_RST;
57 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
61 /* wait until the RST bit is clear or the RST and QUIET bits are set */
62 for (q_no = 0; q_no < num_queues; q_no++) {
63 volatile uint64_t reg_val;
65 reg_val = lio_read_csr64(lio_dev,
66 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
67 while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) &&
68 !(reg_val & CN23XX_PKT_INPUT_CTL_QUIET) &&
70 reg_val = lio_read_csr64(
72 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
78 "clearing the reset reg failed or setting the quiet reg failed for qno: %lu\n",
83 reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST;
84 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
87 reg_val = lio_read_csr64(
88 lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
89 if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {
91 "clearing the reset failed for qno: %lu\n",
101 cn23xx_vf_setup_global_input_regs(struct lio_device *lio_dev)
106 PMD_INIT_FUNC_TRACE();
108 if (cn23xx_vf_reset_io_queues(lio_dev,
109 lio_dev->sriov_info.rings_per_vf))
112 for (q_no = 0; q_no < (lio_dev->sriov_info.rings_per_vf); q_no++) {
113 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_DOORBELL(q_no),
116 d64 = lio_read_csr64(lio_dev,
117 CN23XX_SLI_IQ_INSTR_COUNT64(q_no));
119 d64 &= 0xEFFFFFFFFFFFFFFFL;
121 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_INSTR_COUNT64(q_no),
124 /* Select ES, RO, NS, RDSIZE,DPTR Fomat#0 for
127 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
128 CN23XX_PKT_INPUT_CTL_MASK);
135 cn23xx_vf_setup_global_output_regs(struct lio_device *lio_dev)
140 PMD_INIT_FUNC_TRACE();
142 for (q_no = 0; q_no < lio_dev->sriov_info.rings_per_vf; q_no++) {
143 lio_write_csr(lio_dev, CN23XX_SLI_OQ_PKTS_CREDIT(q_no),
147 lio_read_csr(lio_dev, CN23XX_SLI_OQ_PKTS_SENT(q_no));
149 reg_val &= 0xEFFFFFFFFFFFFFFFL;
152 lio_read_csr(lio_dev, CN23XX_SLI_OQ_PKT_CONTROL(q_no));
154 /* set IPTR & DPTR */
156 (CN23XX_PKT_OUTPUT_CTL_IPTR | CN23XX_PKT_OUTPUT_CTL_DPTR);
159 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_BMODE);
161 /* No Relaxed Ordering, No Snoop, 64-bit Byte swap
162 * for Output Queue Scatter List
165 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR_P);
166 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR_P);
168 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
169 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ES_P);
170 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
171 reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES_P);
173 /* No Relaxed Ordering, No Snoop, 64-bit Byte swap
174 * for Output Queue Data
177 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR);
178 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR);
180 reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES);
182 /* write all the selected settings */
183 lio_write_csr(lio_dev, CN23XX_SLI_OQ_PKT_CONTROL(q_no),
189 cn23xx_vf_setup_device_regs(struct lio_device *lio_dev)
191 PMD_INIT_FUNC_TRACE();
193 if (cn23xx_vf_setup_global_input_regs(lio_dev))
196 cn23xx_vf_setup_global_output_regs(lio_dev);
202 cn23xx_vf_free_mbox(struct lio_device *lio_dev)
204 PMD_INIT_FUNC_TRACE();
206 rte_free(lio_dev->mbox[0]);
207 lio_dev->mbox[0] = NULL;
209 rte_free(lio_dev->mbox);
210 lio_dev->mbox = NULL;
214 cn23xx_vf_setup_mbox(struct lio_device *lio_dev)
216 struct lio_mbox *mbox;
218 PMD_INIT_FUNC_TRACE();
220 if (lio_dev->mbox == NULL) {
221 lio_dev->mbox = rte_zmalloc(NULL, sizeof(void *), 0);
222 if (lio_dev->mbox == NULL)
226 mbox = rte_zmalloc(NULL, sizeof(struct lio_mbox), 0);
228 rte_free(lio_dev->mbox);
229 lio_dev->mbox = NULL;
233 rte_spinlock_init(&mbox->lock);
235 mbox->lio_dev = lio_dev;
239 mbox->state = LIO_MBOX_STATE_IDLE;
241 /* VF mbox interrupt reg */
242 mbox->mbox_int_reg = (uint8_t *)lio_dev->hw_addr +
243 CN23XX_VF_SLI_PKT_MBOX_INT(0);
244 /* VF reads from SIG0 reg */
245 mbox->mbox_read_reg = (uint8_t *)lio_dev->hw_addr +
246 CN23XX_SLI_PKT_PF_VF_MBOX_SIG(0, 0);
247 /* VF writes into SIG1 reg */
248 mbox->mbox_write_reg = (uint8_t *)lio_dev->hw_addr +
249 CN23XX_SLI_PKT_PF_VF_MBOX_SIG(0, 1);
251 lio_dev->mbox[0] = mbox;
253 rte_write64(LIO_PFVFSIG, mbox->mbox_read_reg);
259 cn23xx_vf_setup_device(struct lio_device *lio_dev)
263 PMD_INIT_FUNC_TRACE();
265 /* INPUT_CONTROL[RPVF] gives the VF IOq count */
266 reg_val = lio_read_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(0));
268 lio_dev->pf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_PF_NUM_POS) &
269 CN23XX_PKT_INPUT_CTL_PF_NUM_MASK;
270 lio_dev->vf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_VF_NUM_POS) &
271 CN23XX_PKT_INPUT_CTL_VF_NUM_MASK;
273 reg_val = reg_val >> CN23XX_PKT_INPUT_CTL_RPVF_POS;
275 lio_dev->sriov_info.rings_per_vf =
276 reg_val & CN23XX_PKT_INPUT_CTL_RPVF_MASK;
278 lio_dev->default_config = lio_get_conf(lio_dev);
279 if (lio_dev->default_config == NULL)
282 lio_dev->fn_list.setup_mbox = cn23xx_vf_setup_mbox;
283 lio_dev->fn_list.free_mbox = cn23xx_vf_free_mbox;
285 lio_dev->fn_list.setup_device_regs = cn23xx_vf_setup_device_regs;
291 cn23xx_vf_set_io_queues_off(struct lio_device *lio_dev)
293 uint32_t loop = CN23XX_VF_BUSY_READING_REG_LOOP_COUNT;
296 /* Disable the i/p and o/p queues for this Octeon.
297 * IOQs will already be in reset.
298 * If RST bit is set, wait for Quiet bit to be set
299 * Once Quiet bit is set, clear the RST bit
301 PMD_INIT_FUNC_TRACE();
303 for (q_no = 0; q_no < lio_dev->sriov_info.rings_per_vf; q_no++) {
304 volatile uint64_t reg_val;
306 reg_val = lio_read_csr64(lio_dev,
307 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
308 while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) && !(reg_val &
309 CN23XX_PKT_INPUT_CTL_QUIET) && loop) {
310 reg_val = lio_read_csr64(
312 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
318 "clearing the reset reg failed or setting the quiet reg failed for qno %lu\n",
319 (unsigned long)q_no);
323 reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST;
324 lio_write_csr64(lio_dev, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
327 reg_val = lio_read_csr64(lio_dev,
328 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
329 if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {
330 lio_dev_err(lio_dev, "unable to reset qno %lu\n",
331 (unsigned long)q_no);