4 * Copyright(c) 2017 Cavium, Inc.. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Cavium, Inc. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _LIO_HW_DEFS_H_
35 #define _LIO_HW_DEFS_H_
39 #ifndef PCI_VENDOR_ID_CAVIUM
40 #define PCI_VENDOR_ID_CAVIUM 0x177D
43 #define LIO_CN23XX_VF_VID 0x9712
45 /* --------------------------CONFIG VALUES------------------------ */
47 /* CN23xx IQ configuration macros */
48 #define CN23XX_MAX_RINGS_PER_PF 64
49 #define CN23XX_MAX_RINGS_PER_VF 8
51 #define CN23XX_MAX_INPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
52 #define CN23XX_MAX_IQ_DESCRIPTORS 512
53 #define CN23XX_MIN_IQ_DESCRIPTORS 128
55 #define CN23XX_MAX_OUTPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
56 #define CN23XX_MAX_OQ_DESCRIPTORS 512
57 #define CN23XX_MIN_OQ_DESCRIPTORS 128
58 #define CN23XX_OQ_BUF_SIZE 1536
60 #define CN23XX_OQ_REFIL_THRESHOLD 16
62 #define CN23XX_DEFAULT_NUM_PORTS 1
64 #define CN23XX_CFG_IO_QUEUES CN23XX_MAX_RINGS_PER_PF
66 /* common OCTEON configuration macros */
67 #define OCTEON_64BYTE_INSTR 64
68 #define OCTEON_OQ_INFOPTR_MODE 1
70 /* Max IOQs per LIO Link */
71 #define LIO_MAX_IOQS_PER_IF 64
77 #define LIO_23XX_NAME "23xx"
79 #define LIO_DEV_RUNNING 0xc
81 #define LIO_OQ_REFILL_THRESHOLD_CFG(cfg) \
82 ((cfg)->default_config->oq.refill_threshold)
83 #define LIO_NUM_DEF_TX_DESCS_CFG(cfg) \
84 ((cfg)->default_config->num_def_tx_descs)
86 #define LIO_IQ_INSTR_TYPE(cfg) ((cfg)->default_config->iq.instr_type)
88 /* The following config values are fixed and should not be modified. */
90 /* Maximum number of Instruction queues */
91 #define LIO_MAX_INSTR_QUEUES(lio_dev) CN23XX_MAX_RINGS_PER_VF
93 #define LIO_MAX_POSSIBLE_INSTR_QUEUES CN23XX_MAX_INPUT_QUEUES
94 #define LIO_MAX_POSSIBLE_OUTPUT_QUEUES CN23XX_MAX_OUTPUT_QUEUES
96 #define LIO_DEVICE_NAME_LEN 32
97 #define LIO_BASE_MAJOR_VERSION 1
98 #define LIO_BASE_MINOR_VERSION 5
99 #define LIO_BASE_MICRO_VERSION 1
101 #define LIO_FW_VERSION_LENGTH 32
103 /** Tag types used by Octeon cores in its work. */
104 enum octeon_tag_type {
105 OCTEON_ORDERED_TAG = 0,
106 OCTEON_ATOMIC_TAG = 1,
109 /* pre-defined host->NIC tag values */
110 #define LIO_CONTROL (0x11111110)
112 /* used for NIC operations */
115 /** LIO_OPCODE subcodes */
116 /* This subcode is sent by core PCI driver to indicate cores are ready. */
117 #define LIO_OPCODE_IF_CFG 0x09
119 #define LIO_MAX_RX_PKTLEN (64 * 1024)
121 /* Interface flags communicated between host driver and core app. */
123 LIO_IFFLAG_UNICAST = 0x10
126 /* Routines for reading and writing CSRs */
127 #ifdef RTE_LIBRTE_LIO_DEBUG_REGS
128 #define lio_write_csr(lio_dev, reg_off, value) \
130 typeof(lio_dev) _dev = lio_dev; \
131 typeof(reg_off) _reg_off = reg_off; \
132 typeof(value) _value = value; \
134 "Write32: Reg: 0x%08lx Val: 0x%08lx\n", \
135 (unsigned long)_reg_off, \
136 (unsigned long)_value); \
137 rte_write32(_value, _dev->hw_addr + _reg_off); \
140 #define lio_write_csr64(lio_dev, reg_off, val64) \
142 typeof(lio_dev) _dev = lio_dev; \
143 typeof(reg_off) _reg_off = reg_off; \
144 typeof(val64) _val64 = val64; \
147 "Write64: Reg: 0x%08lx Val: 0x%016llx\n", \
148 (unsigned long)_reg_off, \
149 (unsigned long long)_val64); \
150 rte_write64(_val64, _dev->hw_addr + _reg_off); \
153 #define lio_read_csr(lio_dev, reg_off) \
155 typeof(lio_dev) _dev = lio_dev; \
156 typeof(reg_off) _reg_off = reg_off; \
157 uint32_t val = rte_read32(_dev->hw_addr + _reg_off); \
159 "Read32: Reg: 0x%08lx Val: 0x%08lx\n", \
160 (unsigned long)_reg_off, \
161 (unsigned long)val); \
165 #define lio_read_csr64(lio_dev, reg_off) \
167 typeof(lio_dev) _dev = lio_dev; \
168 typeof(reg_off) _reg_off = reg_off; \
169 uint64_t val64 = rte_read64(_dev->hw_addr + _reg_off); \
172 "Read64: Reg: 0x%08lx Val: 0x%016llx\n", \
173 (unsigned long)_reg_off, \
174 (unsigned long long)val64); \
178 #define lio_write_csr(lio_dev, reg_off, value) \
179 rte_write32(value, (lio_dev)->hw_addr + (reg_off))
181 #define lio_write_csr64(lio_dev, reg_off, val64) \
182 rte_write64(val64, (lio_dev)->hw_addr + (reg_off))
184 #define lio_read_csr(lio_dev, reg_off) \
185 rte_read32((lio_dev)->hw_addr + (reg_off))
187 #define lio_read_csr64(lio_dev, reg_off) \
188 rte_read64((lio_dev)->hw_addr + (reg_off))
190 #endif /* _LIO_HW_DEFS_H_ */