4 * Copyright(c) 2017 Cavium, Inc.. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Cavium, Inc. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _LIO_HW_DEFS_H_
35 #define _LIO_HW_DEFS_H_
39 #ifndef PCI_VENDOR_ID_CAVIUM
40 #define PCI_VENDOR_ID_CAVIUM 0x177D
43 #define LIO_CN23XX_VF_VID 0x9712
45 #define LIO_DEVICE_NAME_LEN 32
47 /* Routines for reading and writing CSRs */
48 #ifdef RTE_LIBRTE_LIO_DEBUG_REGS
49 #define lio_write_csr(lio_dev, reg_off, value) \
51 typeof(lio_dev) _dev = lio_dev; \
52 typeof(reg_off) _reg_off = reg_off; \
53 typeof(value) _value = value; \
55 "Write32: Reg: 0x%08lx Val: 0x%08lx\n", \
56 (unsigned long)_reg_off, \
57 (unsigned long)_value); \
58 rte_write32(_value, _dev->hw_addr + _reg_off); \
61 #define lio_write_csr64(lio_dev, reg_off, val64) \
63 typeof(lio_dev) _dev = lio_dev; \
64 typeof(reg_off) _reg_off = reg_off; \
65 typeof(val64) _val64 = val64; \
68 "Write64: Reg: 0x%08lx Val: 0x%016llx\n", \
69 (unsigned long)_reg_off, \
70 (unsigned long long)_val64); \
71 rte_write64(_val64, _dev->hw_addr + _reg_off); \
74 #define lio_read_csr(lio_dev, reg_off) \
76 typeof(lio_dev) _dev = lio_dev; \
77 typeof(reg_off) _reg_off = reg_off; \
78 uint32_t val = rte_read32(_dev->hw_addr + _reg_off); \
80 "Read32: Reg: 0x%08lx Val: 0x%08lx\n", \
81 (unsigned long)_reg_off, \
82 (unsigned long)val); \
86 #define lio_read_csr64(lio_dev, reg_off) \
88 typeof(lio_dev) _dev = lio_dev; \
89 typeof(reg_off) _reg_off = reg_off; \
90 uint64_t val64 = rte_read64(_dev->hw_addr + _reg_off); \
93 "Read64: Reg: 0x%08lx Val: 0x%016llx\n", \
94 (unsigned long)_reg_off, \
95 (unsigned long long)val64); \
99 #define lio_write_csr(lio_dev, reg_off, value) \
100 rte_write32(value, (lio_dev)->hw_addr + (reg_off))
102 #define lio_write_csr64(lio_dev, reg_off, val64) \
103 rte_write64(val64, (lio_dev)->hw_addr + (reg_off))
105 #define lio_read_csr(lio_dev, reg_off) \
106 rte_read32((lio_dev)->hw_addr + (reg_off))
108 #define lio_read_csr64(lio_dev, reg_off) \
109 rte_read64((lio_dev)->hw_addr + (reg_off))
111 #endif /* _LIO_HW_DEFS_H_ */