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34 #ifndef _LIO_HW_DEFS_H_
35 #define _LIO_HW_DEFS_H_
39 #ifndef PCI_VENDOR_ID_CAVIUM
40 #define PCI_VENDOR_ID_CAVIUM 0x177D
43 #define LIO_CN23XX_VF_VID 0x9712
45 /* --------------------------CONFIG VALUES------------------------ */
47 /* CN23xx IQ configuration macros */
48 #define CN23XX_MAX_RINGS_PER_PF 64
49 #define CN23XX_MAX_RINGS_PER_VF 8
51 #define CN23XX_MAX_INPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
52 #define CN23XX_MAX_IQ_DESCRIPTORS 512
53 #define CN23XX_MIN_IQ_DESCRIPTORS 128
55 #define CN23XX_MAX_OUTPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
56 #define CN23XX_MAX_OQ_DESCRIPTORS 512
57 #define CN23XX_MIN_OQ_DESCRIPTORS 128
58 #define CN23XX_OQ_BUF_SIZE 1536
60 #define CN23XX_OQ_REFIL_THRESHOLD 16
62 #define CN23XX_DEFAULT_NUM_PORTS 1
64 #define CN23XX_CFG_IO_QUEUES CN23XX_MAX_RINGS_PER_PF
66 /* common OCTEON configuration macros */
67 #define OCTEON_64BYTE_INSTR 64
68 #define OCTEON_OQ_INFOPTR_MODE 1
70 /* Max IOQs per LIO Link */
71 #define LIO_MAX_IOQS_PER_IF 64
77 #define LIO_23XX_NAME "23xx"
79 #define LIO_DEVICE_NAME_LEN 32
81 /* Routines for reading and writing CSRs */
82 #ifdef RTE_LIBRTE_LIO_DEBUG_REGS
83 #define lio_write_csr(lio_dev, reg_off, value) \
85 typeof(lio_dev) _dev = lio_dev; \
86 typeof(reg_off) _reg_off = reg_off; \
87 typeof(value) _value = value; \
89 "Write32: Reg: 0x%08lx Val: 0x%08lx\n", \
90 (unsigned long)_reg_off, \
91 (unsigned long)_value); \
92 rte_write32(_value, _dev->hw_addr + _reg_off); \
95 #define lio_write_csr64(lio_dev, reg_off, val64) \
97 typeof(lio_dev) _dev = lio_dev; \
98 typeof(reg_off) _reg_off = reg_off; \
99 typeof(val64) _val64 = val64; \
102 "Write64: Reg: 0x%08lx Val: 0x%016llx\n", \
103 (unsigned long)_reg_off, \
104 (unsigned long long)_val64); \
105 rte_write64(_val64, _dev->hw_addr + _reg_off); \
108 #define lio_read_csr(lio_dev, reg_off) \
110 typeof(lio_dev) _dev = lio_dev; \
111 typeof(reg_off) _reg_off = reg_off; \
112 uint32_t val = rte_read32(_dev->hw_addr + _reg_off); \
114 "Read32: Reg: 0x%08lx Val: 0x%08lx\n", \
115 (unsigned long)_reg_off, \
116 (unsigned long)val); \
120 #define lio_read_csr64(lio_dev, reg_off) \
122 typeof(lio_dev) _dev = lio_dev; \
123 typeof(reg_off) _reg_off = reg_off; \
124 uint64_t val64 = rte_read64(_dev->hw_addr + _reg_off); \
127 "Read64: Reg: 0x%08lx Val: 0x%016llx\n", \
128 (unsigned long)_reg_off, \
129 (unsigned long long)val64); \
133 #define lio_write_csr(lio_dev, reg_off, value) \
134 rte_write32(value, (lio_dev)->hw_addr + (reg_off))
136 #define lio_write_csr64(lio_dev, reg_off, val64) \
137 rte_write64(val64, (lio_dev)->hw_addr + (reg_off))
139 #define lio_read_csr(lio_dev, reg_off) \
140 rte_read32((lio_dev)->hw_addr + (reg_off))
142 #define lio_read_csr64(lio_dev, reg_off) \
143 rte_read64((lio_dev)->hw_addr + (reg_off))
145 #endif /* _LIO_HW_DEFS_H_ */