4 * Copyright(c) 2017 Cavium, Inc.. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Cavium, Inc. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _LIO_HW_DEFS_H_
35 #define _LIO_HW_DEFS_H_
39 #ifndef PCI_VENDOR_ID_CAVIUM
40 #define PCI_VENDOR_ID_CAVIUM 0x177D
43 #define LIO_CN23XX_VF_VID 0x9712
45 /* CN23xx subsystem device ids */
46 #define PCI_SUBSYS_DEV_ID_CN2350_210 0x0004
47 #define PCI_SUBSYS_DEV_ID_CN2360_210 0x0005
48 #define PCI_SUBSYS_DEV_ID_CN2360_225 0x0006
49 #define PCI_SUBSYS_DEV_ID_CN2350_225 0x0007
51 /* --------------------------CONFIG VALUES------------------------ */
53 /* CN23xx IQ configuration macros */
54 #define CN23XX_MAX_RINGS_PER_PF 64
55 #define CN23XX_MAX_RINGS_PER_VF 8
57 #define CN23XX_MAX_INPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
58 #define CN23XX_MAX_IQ_DESCRIPTORS 512
59 #define CN23XX_MIN_IQ_DESCRIPTORS 128
61 #define CN23XX_MAX_OUTPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
62 #define CN23XX_MAX_OQ_DESCRIPTORS 512
63 #define CN23XX_MIN_OQ_DESCRIPTORS 128
64 #define CN23XX_OQ_BUF_SIZE 1536
66 #define CN23XX_OQ_REFIL_THRESHOLD 16
68 #define CN23XX_DEFAULT_NUM_PORTS 1
70 #define CN23XX_CFG_IO_QUEUES CN23XX_MAX_RINGS_PER_PF
72 /* common OCTEON configuration macros */
73 #define OCTEON_64BYTE_INSTR 64
74 #define OCTEON_OQ_INFOPTR_MODE 1
76 /* Max IOQs per LIO Link */
77 #define LIO_MAX_IOQS_PER_IF 64
83 #define LIO_23XX_NAME "23xx"
85 #define LIO_DEV_RUNNING 0xc
87 #define LIO_OQ_REFILL_THRESHOLD_CFG(cfg) \
88 ((cfg)->default_config->oq.refill_threshold)
89 #define LIO_NUM_DEF_TX_DESCS_CFG(cfg) \
90 ((cfg)->default_config->num_def_tx_descs)
92 #define LIO_IQ_INSTR_TYPE(cfg) ((cfg)->default_config->iq.instr_type)
94 /* The following config values are fixed and should not be modified. */
96 /* Maximum number of Instruction queues */
97 #define LIO_MAX_INSTR_QUEUES(lio_dev) CN23XX_MAX_RINGS_PER_VF
99 #define LIO_MAX_POSSIBLE_INSTR_QUEUES CN23XX_MAX_INPUT_QUEUES
100 #define LIO_MAX_POSSIBLE_OUTPUT_QUEUES CN23XX_MAX_OUTPUT_QUEUES
102 #define LIO_DEVICE_NAME_LEN 32
103 #define LIO_BASE_MAJOR_VERSION 1
104 #define LIO_BASE_MINOR_VERSION 5
105 #define LIO_BASE_MICRO_VERSION 1
107 #define LIO_FW_VERSION_LENGTH 32
109 /** Tag types used by Octeon cores in its work. */
110 enum octeon_tag_type {
111 OCTEON_ORDERED_TAG = 0,
112 OCTEON_ATOMIC_TAG = 1,
115 /* pre-defined host->NIC tag values */
116 #define LIO_CONTROL (0x11111110)
117 #define LIO_DATA(i) (0x11111111 + (i))
119 /* used for NIC operations */
122 /* Subcodes are used by host driver/apps to identify the sub-operation
123 * for the core. They only need to by unique for a given subsystem.
125 #define LIO_OPCODE_SUBCODE(op, sub) \
126 ((((op) & 0x0f) << 8) | ((sub) & 0x7f))
128 /** LIO_OPCODE subcodes */
129 /* This subcode is sent by core PCI driver to indicate cores are ready. */
130 #define LIO_OPCODE_NW_DATA 0x02 /* network packet data */
131 #define LIO_OPCODE_CMD 0x03
132 #define LIO_OPCODE_INFO 0x04
133 #define LIO_OPCODE_PORT_STATS 0x05
134 #define LIO_OPCODE_IF_CFG 0x09
136 #define LIO_MIN_RX_BUF_SIZE 64
137 #define LIO_MAX_RX_PKTLEN (64 * 1024)
139 /* NIC Command types */
140 #define LIO_CMD_CHANGE_DEVFLAGS 0x3
141 #define LIO_CMD_RX_CTL 0x4
142 #define LIO_CMD_CLEAR_STATS 0x6
143 #define LIO_CMD_SET_RSS 0xD
144 #define LIO_CMD_TNL_RX_CSUM_CTL 0x10
145 #define LIO_CMD_TNL_TX_CSUM_CTL 0x11
146 #define LIO_CMD_ADD_VLAN_FILTER 0x17
147 #define LIO_CMD_DEL_VLAN_FILTER 0x18
148 #define LIO_CMD_VXLAN_PORT_CONFIG 0x19
150 #define LIO_CMD_VXLAN_PORT_ADD 0x0
151 #define LIO_CMD_VXLAN_PORT_DEL 0x1
152 #define LIO_CMD_RXCSUM_ENABLE 0x0
153 #define LIO_CMD_TXCSUM_ENABLE 0x0
155 /* RX(packets coming from wire) Checksum verification flags */
157 #define LIO_L4_CSUM_VERIFIED 0x1
158 #define LIO_IP_CSUM_VERIFIED 0x2
161 #define LIO_RSS_PARAM_DISABLE_RSS 0x10
162 #define LIO_RSS_PARAM_HASH_KEY_UNCHANGED 0x08
163 #define LIO_RSS_PARAM_ITABLE_UNCHANGED 0x04
164 #define LIO_RSS_PARAM_HASH_INFO_UNCHANGED 0x02
166 #define LIO_RSS_HASH_IPV4 0x100
167 #define LIO_RSS_HASH_TCP_IPV4 0x200
168 #define LIO_RSS_HASH_IPV6 0x400
169 #define LIO_RSS_HASH_TCP_IPV6 0x1000
170 #define LIO_RSS_HASH_IPV6_EX 0x800
171 #define LIO_RSS_HASH_TCP_IPV6_EX 0x2000
173 #define LIO_RSS_OFFLOAD_ALL ( \
174 LIO_RSS_HASH_IPV4 | \
175 LIO_RSS_HASH_TCP_IPV4 | \
176 LIO_RSS_HASH_IPV6 | \
177 LIO_RSS_HASH_TCP_IPV6 | \
178 LIO_RSS_HASH_IPV6_EX | \
179 LIO_RSS_HASH_TCP_IPV6_EX)
181 #define LIO_RSS_MAX_TABLE_SZ 128
182 #define LIO_RSS_MAX_KEY_SZ 40
183 #define LIO_RSS_PARAM_SIZE 16
185 /* Interface flags communicated between host driver and core app. */
187 LIO_IFFLAG_ALLMULTI = 0x02,
188 LIO_IFFLAG_UNICAST = 0x10
191 /* Routines for reading and writing CSRs */
192 #ifdef RTE_LIBRTE_LIO_DEBUG_REGS
193 #define lio_write_csr(lio_dev, reg_off, value) \
195 typeof(lio_dev) _dev = lio_dev; \
196 typeof(reg_off) _reg_off = reg_off; \
197 typeof(value) _value = value; \
199 "Write32: Reg: 0x%08lx Val: 0x%08lx\n", \
200 (unsigned long)_reg_off, \
201 (unsigned long)_value); \
202 rte_write32(_value, _dev->hw_addr + _reg_off); \
205 #define lio_write_csr64(lio_dev, reg_off, val64) \
207 typeof(lio_dev) _dev = lio_dev; \
208 typeof(reg_off) _reg_off = reg_off; \
209 typeof(val64) _val64 = val64; \
212 "Write64: Reg: 0x%08lx Val: 0x%016llx\n", \
213 (unsigned long)_reg_off, \
214 (unsigned long long)_val64); \
215 rte_write64(_val64, _dev->hw_addr + _reg_off); \
218 #define lio_read_csr(lio_dev, reg_off) \
220 typeof(lio_dev) _dev = lio_dev; \
221 typeof(reg_off) _reg_off = reg_off; \
222 uint32_t val = rte_read32(_dev->hw_addr + _reg_off); \
224 "Read32: Reg: 0x%08lx Val: 0x%08lx\n", \
225 (unsigned long)_reg_off, \
226 (unsigned long)val); \
230 #define lio_read_csr64(lio_dev, reg_off) \
232 typeof(lio_dev) _dev = lio_dev; \
233 typeof(reg_off) _reg_off = reg_off; \
234 uint64_t val64 = rte_read64(_dev->hw_addr + _reg_off); \
237 "Read64: Reg: 0x%08lx Val: 0x%016llx\n", \
238 (unsigned long)_reg_off, \
239 (unsigned long long)val64); \
243 #define lio_write_csr(lio_dev, reg_off, value) \
244 rte_write32(value, (lio_dev)->hw_addr + (reg_off))
246 #define lio_write_csr64(lio_dev, reg_off, val64) \
247 rte_write64(val64, (lio_dev)->hw_addr + (reg_off))
249 #define lio_read_csr(lio_dev, reg_off) \
250 rte_read32((lio_dev)->hw_addr + (reg_off))
252 #define lio_read_csr64(lio_dev, reg_off) \
253 rte_read64((lio_dev)->hw_addr + (reg_off))
255 #endif /* _LIO_HW_DEFS_H_ */