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34 #ifndef _LIO_HW_DEFS_H_
35 #define _LIO_HW_DEFS_H_
39 #ifndef PCI_VENDOR_ID_CAVIUM
40 #define PCI_VENDOR_ID_CAVIUM 0x177D
43 #define LIO_CN23XX_VF_VID 0x9712
45 /* --------------------------CONFIG VALUES------------------------ */
47 /* CN23xx IQ configuration macros */
48 #define CN23XX_MAX_RINGS_PER_PF 64
49 #define CN23XX_MAX_RINGS_PER_VF 8
51 #define CN23XX_MAX_INPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
52 #define CN23XX_MAX_IQ_DESCRIPTORS 512
53 #define CN23XX_MIN_IQ_DESCRIPTORS 128
55 #define CN23XX_MAX_OUTPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
56 #define CN23XX_MAX_OQ_DESCRIPTORS 512
57 #define CN23XX_MIN_OQ_DESCRIPTORS 128
58 #define CN23XX_OQ_BUF_SIZE 1536
60 #define CN23XX_OQ_REFIL_THRESHOLD 16
62 #define CN23XX_DEFAULT_NUM_PORTS 1
64 #define CN23XX_CFG_IO_QUEUES CN23XX_MAX_RINGS_PER_PF
66 /* common OCTEON configuration macros */
67 #define OCTEON_64BYTE_INSTR 64
68 #define OCTEON_OQ_INFOPTR_MODE 1
70 /* Max IOQs per LIO Link */
71 #define LIO_MAX_IOQS_PER_IF 64
77 #define LIO_23XX_NAME "23xx"
79 #define LIO_DEV_RUNNING 0xc
81 #define LIO_NUM_DEF_TX_DESCS_CFG(cfg) \
82 ((cfg)->default_config->num_def_tx_descs)
84 #define LIO_IQ_INSTR_TYPE(cfg) ((cfg)->default_config->iq.instr_type)
86 /* The following config values are fixed and should not be modified. */
88 /* Maximum number of Instruction queues */
89 #define LIO_MAX_INSTR_QUEUES(lio_dev) CN23XX_MAX_RINGS_PER_VF
91 #define LIO_MAX_POSSIBLE_INSTR_QUEUES CN23XX_MAX_INPUT_QUEUES
93 #define LIO_DEVICE_NAME_LEN 32
94 #define LIO_BASE_MAJOR_VERSION 1
95 #define LIO_BASE_MINOR_VERSION 5
96 #define LIO_BASE_MICRO_VERSION 1
98 #define LIO_FW_VERSION_LENGTH 32
100 /** Tag types used by Octeon cores in its work. */
101 enum octeon_tag_type {
102 OCTEON_ORDERED_TAG = 0,
103 OCTEON_ATOMIC_TAG = 1,
106 /* pre-defined host->NIC tag values */
107 #define LIO_CONTROL (0x11111110)
109 /* used for NIC operations */
112 /** LIO_OPCODE subcodes */
113 /* This subcode is sent by core PCI driver to indicate cores are ready. */
114 #define LIO_OPCODE_IF_CFG 0x09
116 /* Interface flags communicated between host driver and core app. */
118 LIO_IFFLAG_UNICAST = 0x10
121 /* Routines for reading and writing CSRs */
122 #ifdef RTE_LIBRTE_LIO_DEBUG_REGS
123 #define lio_write_csr(lio_dev, reg_off, value) \
125 typeof(lio_dev) _dev = lio_dev; \
126 typeof(reg_off) _reg_off = reg_off; \
127 typeof(value) _value = value; \
129 "Write32: Reg: 0x%08lx Val: 0x%08lx\n", \
130 (unsigned long)_reg_off, \
131 (unsigned long)_value); \
132 rte_write32(_value, _dev->hw_addr + _reg_off); \
135 #define lio_write_csr64(lio_dev, reg_off, val64) \
137 typeof(lio_dev) _dev = lio_dev; \
138 typeof(reg_off) _reg_off = reg_off; \
139 typeof(val64) _val64 = val64; \
142 "Write64: Reg: 0x%08lx Val: 0x%016llx\n", \
143 (unsigned long)_reg_off, \
144 (unsigned long long)_val64); \
145 rte_write64(_val64, _dev->hw_addr + _reg_off); \
148 #define lio_read_csr(lio_dev, reg_off) \
150 typeof(lio_dev) _dev = lio_dev; \
151 typeof(reg_off) _reg_off = reg_off; \
152 uint32_t val = rte_read32(_dev->hw_addr + _reg_off); \
154 "Read32: Reg: 0x%08lx Val: 0x%08lx\n", \
155 (unsigned long)_reg_off, \
156 (unsigned long)val); \
160 #define lio_read_csr64(lio_dev, reg_off) \
162 typeof(lio_dev) _dev = lio_dev; \
163 typeof(reg_off) _reg_off = reg_off; \
164 uint64_t val64 = rte_read64(_dev->hw_addr + _reg_off); \
167 "Read64: Reg: 0x%08lx Val: 0x%016llx\n", \
168 (unsigned long)_reg_off, \
169 (unsigned long long)val64); \
173 #define lio_write_csr(lio_dev, reg_off, value) \
174 rte_write32(value, (lio_dev)->hw_addr + (reg_off))
176 #define lio_write_csr64(lio_dev, reg_off, val64) \
177 rte_write64(val64, (lio_dev)->hw_addr + (reg_off))
179 #define lio_read_csr(lio_dev, reg_off) \
180 rte_read32((lio_dev)->hw_addr + (reg_off))
182 #define lio_read_csr64(lio_dev, reg_off) \
183 rte_read64((lio_dev)->hw_addr + (reg_off))
185 #endif /* _LIO_HW_DEFS_H_ */