4 * Copyright(c) 2017 Cavium, Inc.. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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15 * the documentation and/or other materials provided with the
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40 #include <rte_spinlock.h>
41 #include <rte_memory.h>
43 #include "lio_struct.h"
45 #define LIO_STQUEUE_FIRST_ENTRY(ptr, type, elem) \
46 (type *)((char *)((ptr)->stqh_first) - offsetof(type, elem))
48 #define lio_check_timeout(cur_time, chk_time) ((cur_time) > (chk_time))
51 (size_t)(rte_get_timer_cycles() / rte_get_timer_hz())
53 #define LIO_IQ_SEND_OK 0
54 #define LIO_IQ_SEND_STOP 1
55 #define LIO_IQ_SEND_FAILED -1
58 #define LIO_REQTYPE_NONE 0
59 #define LIO_REQTYPE_NORESP_NET 1
60 #define LIO_REQTYPE_NORESP_NET_SG 2
61 #define LIO_REQTYPE_SOFT_COMMAND 3
63 struct lio_request_list {
68 /*---------------------- INSTRUCTION FORMAT ----------------------------*/
70 struct lio_instr3_64B {
71 /** Pointer where the input data is available. */
74 /** Instruction Header. */
77 /** Instruction Header. */
80 /** Input Request Header. */
83 /** opcode/subcode specific parameters */
86 /** Return Data Parameters */
89 /** Pointer where the response for a RAW mode packet will be written
97 struct lio_instr3_64B cmd3;
100 /** The size of each buffer in soft command buffer pool */
101 #define LIO_SOFT_COMMAND_BUFFER_SIZE 1536
103 /** Maximum number of buffers to allocate into soft command buffer pool */
104 #define LIO_MAX_SOFT_COMMAND_BUFFERS 255
106 struct lio_soft_command {
107 /** Soft command buffer info. */
108 struct lio_stailq_node node;
112 /** Command and return status */
113 union lio_instr_64B cmd;
115 #define LIO_COMPLETION_WORD_INIT 0xffffffffffffffffULL
116 uint64_t *status_word;
118 /** Data buffer info */
123 /** Return buffer info */
128 /** Context buffer info */
132 /** Time out and callback */
136 void (*callback)(uint32_t, void *);
138 struct rte_mbuf *mbuf;
141 struct lio_iq_post_status {
167 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
170 uint64_t more : 6; /* How many udd words follow the command */
172 uint64_t reserved : 29;
174 uint64_t param1 : 16;
178 #elif RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
182 uint64_t param1 : 16;
184 uint64_t reserved : 29;
194 #define OCTEON_CMD_SIZE (sizeof(union octeon_cmd))
196 /* Instruction Header */
197 struct octeon_instr_ih3 {
198 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
201 uint64_t reserved3 : 1;
203 /** Gather indicator 1=gather*/
206 /** Data length OR no. of entries in gather list */
207 uint64_t dlengsz : 14;
209 /** Front Data size */
213 uint64_t reserved2 : 4;
215 /** PKI port kind - PKIND */
219 uint64_t reserved1 : 32;
221 #elif RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
223 uint64_t reserved1 : 32;
225 /** PKI port kind - PKIND */
229 uint64_t reserved2 : 4;
231 /** Front Data size */
234 /** Data length OR no. of entries in gather list */
235 uint64_t dlengsz : 14;
237 /** Gather indicator 1=gather*/
241 uint64_t reserved3 : 1;
246 /* PKI Instruction Header(PKI IH) */
247 struct octeon_instr_pki_ih3 {
248 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
253 /** Raw mode indicator 1 = RAW */
263 uint64_t reserved2 : 1;
275 uint64_t tagtype : 2;
278 uint64_t reserved1 : 2;
286 #elif RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
295 uint64_t reserved1 : 2;
298 uint64_t tagtype : 2;
310 uint64_t reserved2 : 1;
318 /** Raw mode indicator 1 = RAW */
326 /** Input Request Header */
327 struct octeon_instr_irh {
328 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
331 uint64_t subcode : 7;
333 uint64_t priority : 3;
334 uint64_t reserved : 5;
335 uint64_t ossp : 32; /* opcode/subcode specific parameters */
336 #elif RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
337 uint64_t ossp : 32; /* opcode/subcode specific parameters */
338 uint64_t reserved : 5;
339 uint64_t priority : 3;
341 uint64_t subcode : 7;
347 /* pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */
348 #define OCTEON_SOFT_CMD_RESP_IH3 (40 + 8)
349 /* pki_h3 + irh + ossp[0] + ossp[1] = 32 bytes */
350 #define OCTEON_PCI_CMD_O3 (24 + 8)
352 /** Return Data Parameters */
353 struct octeon_instr_rdp {
354 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
355 uint64_t reserved : 49;
356 uint64_t pcie_port : 3;
358 #elif RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
360 uint64_t pcie_port : 3;
361 uint64_t reserved : 49;
365 int lio_setup_sc_buffer_pool(struct lio_device *lio_dev);
366 void lio_free_sc_buffer_pool(struct lio_device *lio_dev);
368 struct lio_soft_command *
369 lio_alloc_soft_command(struct lio_device *lio_dev,
370 uint32_t datasize, uint32_t rdatasize,
372 void lio_prepare_soft_command(struct lio_device *lio_dev,
373 struct lio_soft_command *sc,
374 uint8_t opcode, uint8_t subcode,
375 uint32_t irh_ossp, uint64_t ossp0,
377 int lio_send_soft_command(struct lio_device *lio_dev,
378 struct lio_soft_command *sc);
379 void lio_free_soft_command(struct lio_soft_command *sc);
381 /** Maximum ordered requests to process in every invocation of
382 * lio_process_ordered_list(). The function will continue to process requests
383 * as long as it can find one that has finished processing. If it keeps
384 * finding requests that have completed, the function can run for ever. The
385 * value defined here sets an upper limit on the number of requests it can
386 * process before it returns control to the poll thread.
388 #define LIO_MAX_ORD_REQS_TO_PROCESS 4096
390 /** Error codes used in Octeon Host-Core communication.
393 * ----------------------------
395 * ----------------------------
396 * Error codes are 32-bit wide. The upper 16-bits, called Major Error Number,
397 * are reserved to identify the group to which the error code belongs. The
398 * lower 16-bits, called Minor Error Number, carry the actual code.
400 * So error codes are (MAJOR NUMBER << 16)| MINOR_NUMBER.
402 /** Status for a request.
403 * If the request is successfully queued, the driver will return
404 * a LIO_REQUEST_PENDING status. LIO_REQUEST_TIMEOUT is only returned by
405 * the driver if the response for request failed to arrive before a
406 * time-out period or if the request processing * got interrupted due to
407 * a signal respectively.
410 /** A value of 0x00000000 indicates no error i.e. success */
411 LIO_REQUEST_DONE = 0x00000000,
412 /** (Major number: 0x0000; Minor Number: 0x0001) */
413 LIO_REQUEST_PENDING = 0x00000001,
414 LIO_REQUEST_TIMEOUT = 0x00000003,
418 /*------ Error codes used by firmware (bits 15..0 set by firmware */
419 #define LIO_FIRMWARE_MAJOR_ERROR_CODE 0x0001
420 #define LIO_FIRMWARE_STATUS_CODE(status) \
421 ((LIO_FIRMWARE_MAJOR_ERROR_CODE << 16) | (status))
423 /** Initialize the response lists. The number of response lists to create is
425 * @param lio_dev - the lio device structure.
427 void lio_setup_response_list(struct lio_device *lio_dev);
429 /** Check the status of first entry in the ordered list. If the instruction at
430 * that entry finished processing or has timed-out, the entry is cleaned.
431 * @param lio_dev - the lio device structure.
432 * @return 1 if the ordered list is empty, 0 otherwise.
434 int lio_process_ordered_list(struct lio_device *lio_dev);
437 lio_swap_8B_data(uint64_t *data, uint32_t blocks)
440 *data = rte_cpu_to_be_64(*data);
446 /* Macro to increment index.
447 * Index is incremented by count; if the sum exceeds
448 * max, index is wrapped-around to the start.
450 static inline uint32_t
451 lio_incr_index(uint32_t index, uint32_t count, uint32_t max)
453 if ((index + count) >= max)
454 index = index + count - max;
461 /** Setup instruction queue zero for the device
462 * @param lio_dev which lio device to setup
464 * @return 0 if success. -1 if fails
466 int lio_setup_instr_queue0(struct lio_device *lio_dev);
467 void lio_free_instr_queue0(struct lio_device *lio_dev);
468 #endif /* _LIO_RXTX_H_ */