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34 #ifndef _LIO_STRUCT_H_
35 #define _LIO_STRUCT_H_
39 #include <sys/queue.h>
41 #include <rte_spinlock.h>
42 #include <rte_atomic.h>
44 #include "lio_hw_defs.h"
46 struct lio_stailq_node {
47 STAILQ_ENTRY(lio_stailq_node) entries;
50 STAILQ_HEAD(lio_stailq_head, lio_stailq_node);
59 /** Output Queue statistics. Each output queue has four stats fields. */
60 struct lio_droq_stats {
61 /** Number of packets received in this queue. */
62 uint64_t pkts_received;
64 /** Bytes received by this queue. */
65 uint64_t bytes_received;
67 /** Packets dropped due to no memory available. */
68 uint64_t dropped_nomem;
70 /** Packets dropped due to large number of pkts to process. */
71 uint64_t dropped_toomany;
73 /** Number of packets sent to stack from this queue. */
74 uint64_t rx_pkts_received;
76 /** Number of Bytes sent to stack from this queue. */
77 uint64_t rx_bytes_received;
79 /** Num of Packets dropped due to receive path failures. */
82 /** Num of vxlan packets received; */
85 /** Num of failures of lio_recv_buffer_alloc() */
86 uint64_t rx_alloc_failure;
90 /** The Descriptor Ring Output Queue structure.
91 * This structure has all the information required to implement a
95 /** A spinlock to protect access to this ring. */
102 struct lio_device *lio_dev;
104 /** The 8B aligned descriptor ring starts at this address. */
105 struct lio_droq_desc *desc_ring;
107 /** Index in the ring where the driver should read the next packet */
110 /** Index in the ring where Octeon will write the next packet */
113 /** Index in the ring where the driver will refill the descriptor's
118 /** Packets pending to be processed */
119 rte_atomic64_t pkts_pending;
121 /** Number of descriptors in this ring. */
124 /** The number of descriptors pending refill. */
125 uint32_t refill_count;
127 uint32_t refill_threshold;
129 /** The 8B aligned info ptrs begin from this address. */
130 struct lio_droq_info *info_list;
132 /** The receive buffer list. This list has the virtual addresses of the
135 struct lio_recv_buffer *recv_buf_list;
137 /** The size of each buffer pointed by the buffer pointer. */
138 uint32_t buffer_size;
140 /** Pointer to the mapped packet credit register.
141 * Host writes number of info/buffer ptrs available to this register
143 void *pkts_credit_reg;
145 /** Pointer to the mapped packet sent register.
146 * Octeon writes the number of packets DMA'ed to host memory
151 /** Statistics for this DROQ. */
152 struct lio_droq_stats stats;
154 /** DMA mapped address of the DROQ descriptor ring. */
155 size_t desc_ring_dma;
157 /** Info ptr list are allocated at this virtual address. */
158 size_t info_base_addr;
160 /** DMA mapped address of the info list */
161 size_t info_list_dma;
163 /** Allocated size of info list. */
164 uint32_t info_alloc_size;
167 const struct rte_memzone *desc_ring_mz;
168 const struct rte_memzone *info_mz;
169 struct rte_mempool *mpool;
172 /** Receive Header */
174 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
178 uint64_t subcode : 8;
179 uint64_t len : 3; /** additional 64-bit words */
180 uint64_t reserved : 17;
181 uint64_t ossp : 32; /** opcode/subcode specific parameters */
185 uint64_t subcode : 8;
186 uint64_t len : 3; /** additional 64-bit words */
189 uint64_t priority : 3;
190 uint64_t csum_verified : 3; /** checksum verified. */
191 uint64_t has_hwtstamp : 1; /** Has hardware timestamp.1 = yes.*/
192 uint64_t encap_on : 1;
193 uint64_t has_hash : 1; /** Has hash (rth or rss). 1 = yes. */
197 uint64_t subcode : 8;
198 uint64_t len : 3; /** additional 64-bit words */
199 uint64_t reserved : 8;
201 uint64_t gmxport : 16;
206 uint64_t ossp : 32; /** opcode/subcode specific parameters */
207 uint64_t reserved : 17;
208 uint64_t len : 3; /** additional 64-bit words */
209 uint64_t subcode : 8;
213 uint64_t has_hash : 1; /** Has hash (rth or rss). 1 = yes. */
214 uint64_t encap_on : 1;
215 uint64_t has_hwtstamp : 1; /** 1 = has hwtstamp */
216 uint64_t csum_verified : 3; /** checksum verified. */
217 uint64_t priority : 3;
220 uint64_t len : 3; /** additional 64-bit words */
221 uint64_t subcode : 8;
225 uint64_t gmxport : 16;
227 uint64_t reserved : 8;
228 uint64_t len : 3; /** additional 64-bit words */
229 uint64_t subcode : 8;
235 #define OCTEON_RH_SIZE (sizeof(union octeon_rh))
237 /** The txpciq info passed to host from the firmware */
238 union octeon_txpciq {
242 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
246 uint64_t use_qpg : 1;
248 uint64_t aura_num : 10;
249 uint64_t reserved : 20;
251 uint64_t reserved : 20;
252 uint64_t aura_num : 10;
254 uint64_t use_qpg : 1;
262 /** The instruction (input) queue.
263 * The input queue is used to post raw (instruction) mode data or packet
264 * data to Octeon device from the host. Each input queue for
265 * a LIO device has one such structure to represent it.
267 struct lio_instr_queue {
268 /** A spinlock to protect access to the input ring. */
271 rte_spinlock_t post_lock;
273 struct lio_device *lio_dev;
275 uint32_t pkt_in_done;
277 rte_atomic64_t iq_flush_running;
279 /** Flag that indicates if the queue uses 64 byte commands. */
280 uint32_t iqcmd_64B:1;
283 union octeon_txpciq txpciq;
289 /** Maximum no. of instructions in this queue. */
292 /** Index in input ring where the driver should write the next packet */
293 uint32_t host_write_index;
295 /** Index in input ring where Octeon is expected to read the next
298 uint32_t lio_read_index;
300 /** This index aids in finding the window in the queue where Octeon
301 * has read the commands.
303 uint32_t flush_index;
305 /** This field keeps track of the instructions pending in this queue. */
306 rte_atomic64_t instr_pending;
308 /** Pointer to the Virtual Base addr of the input ring. */
311 struct lio_request_list *request_list;
313 /** Octeon doorbell register for the ring. */
316 /** Octeon instruction count register for this ring. */
319 /** Number of instructions pending to be posted to Octeon. */
322 /** DMA mapped base address of the input descriptor ring. */
323 uint64_t base_addr_dma;
325 /** Application context */
328 /* network stack queue index */
332 const struct rte_memzone *iq_mz;
335 /** This structure is used by driver to store information required
336 * to free the mbuff when the packet has been fetched by Octeon.
337 * Bytes offset below assume worst-case of a 64-bit system.
339 struct lio_buf_free_info {
340 /** Bytes 1-8. Pointer to network device private structure. */
341 struct lio_device *lio_dev;
343 /** Bytes 9-16. Pointer to mbuff. */
344 struct rte_mbuf *mbuf;
346 /** Bytes 17-24. Pointer to gather list. */
347 struct lio_gather *g;
349 /** Bytes 25-32. Physical address of mbuf->data or gather list. */
352 /** Bytes 33-47. Piggybacked soft command, if any */
353 struct lio_soft_command *sc;
355 /** Bytes 48-63. iq no */
359 /* The Scatter-Gather List Entry. The scatter or gather component used with
360 * input instruction has this format.
362 struct lio_sg_entry {
363 /** The first 64 bit gives the size of data in each dptr. */
369 /** The 4 dptr pointers for this entry. */
373 #define LIO_SG_ENTRY_SIZE (sizeof(struct lio_sg_entry))
375 /** Structure of a node in list of gather components maintained by
376 * driver for each network device.
379 /** List manipulation. Next and prev pointers. */
380 struct lio_stailq_node list;
382 /** Size of the gather component at sg in bytes. */
385 /** Number of bytes that sg was adjusted to make it 8B-aligned. */
388 /** Gather component that can accommodate max sized fragment list
389 * received from the IP layer.
391 struct lio_sg_entry *sg;
395 uint16_t hash_key_size;
396 uint8_t hash_key[LIO_RSS_MAX_KEY_SZ];
397 /* Ideally a factor of number of queues */
398 uint8_t itable[LIO_RSS_MAX_TABLE_SZ];
403 uint8_t ipv6_tcp_hash;
405 uint8_t ipv6_tcp_ex_hash;
406 uint8_t hash_disable;
409 struct lio_io_enable {
416 void (*setup_iq_regs)(struct lio_device *, uint32_t);
417 void (*setup_oq_regs)(struct lio_device *, uint32_t);
419 int (*setup_mbox)(struct lio_device *);
420 void (*free_mbox)(struct lio_device *);
422 int (*setup_device_regs)(struct lio_device *);
423 int (*enable_io_queues)(struct lio_device *);
424 void (*disable_io_queues)(struct lio_device *);
427 struct lio_pf_vf_hs_word {
428 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
429 /** PKIND value assigned for the DPI interface */
432 /** OCTEON core clock multiplier */
433 uint64_t core_tics_per_us : 16;
435 /** OCTEON coprocessor clock multiplier */
436 uint64_t coproc_tics_per_us : 16;
438 /** app that currently running on OCTEON */
439 uint64_t app_mode : 8;
442 uint64_t reserved : 16;
444 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
447 uint64_t reserved : 16;
449 /** app that currently running on OCTEON */
450 uint64_t app_mode : 8;
452 /** OCTEON coprocessor clock multiplier */
453 uint64_t coproc_tics_per_us : 16;
455 /** OCTEON core clock multiplier */
456 uint64_t core_tics_per_us : 16;
458 /** PKIND value assigned for the DPI interface */
463 struct lio_sriov_info {
464 /** Number of rings assigned to VF */
465 uint32_t rings_per_vf;
467 /** Number of VF devices enabled */
471 /* Head of a response list */
472 struct lio_response_list {
473 /** List structure to add delete pending entries to */
474 struct lio_stailq_head head;
476 /** A lock for this response list */
479 rte_atomic64_t pending_req_count;
482 /* Structure to define the configuration attributes for each Input queue. */
483 struct lio_iq_config {
484 /* Max number of IQs available */
487 /** Pending list size (usually set to the sum of the size of all Input
490 uint32_t pending_list_size;
492 /** Command size - 32 or 64 bytes */
496 /* Structure to define the configuration attributes for each Output queue. */
497 struct lio_oq_config {
498 /* Max number of OQs available */
501 /** If set, the Output queue uses info-pointer mode. (Default: 1 ) */
504 /** The number of buffers that were consumed during packet processing by
505 * the driver on this Output queue before the driver attempts to
506 * replenish the descriptor ring with new buffers.
508 uint32_t refill_threshold;
511 /* Structure to define the configuration. */
514 const char *card_name;
516 /** Input Queue attributes. */
517 struct lio_iq_config iq;
519 /** Output Queue attributes. */
520 struct lio_oq_config oq;
524 int num_def_tx_descs;
526 /* Num of desc for rx rings */
527 int num_def_rx_descs;
532 /** Status of a RGMII Link on Octeon as seen by core driver. */
533 union octeon_link_status {
534 uint64_t link_status64;
537 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
541 uint64_t link_up : 1;
542 uint64_t autoneg : 1;
543 uint64_t if_mode : 5;
545 uint64_t flashing : 1;
546 uint64_t reserved : 15;
548 uint64_t reserved : 15;
549 uint64_t flashing : 1;
551 uint64_t if_mode : 5;
552 uint64_t autoneg : 1;
553 uint64_t link_up : 1;
561 /** The rxpciq info passed to host from the firmware */
562 union octeon_rxpciq {
566 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
568 uint64_t reserved : 56;
570 uint64_t reserved : 56;
576 /** Information for a OCTEON ethernet interface shared between core & host. */
577 struct octeon_link_info {
578 union octeon_link_status link;
581 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
582 uint64_t gmxport : 16;
583 uint64_t macaddr_is_admin_assigned : 1;
584 uint64_t vlan_is_admin_assigned : 1;
586 uint64_t num_txpciq : 8;
587 uint64_t num_rxpciq : 8;
589 uint64_t num_rxpciq : 8;
590 uint64_t num_txpciq : 8;
592 uint64_t vlan_is_admin_assigned : 1;
593 uint64_t macaddr_is_admin_assigned : 1;
594 uint64_t gmxport : 16;
597 union octeon_txpciq txpciq[LIO_MAX_IOQS_PER_IF];
598 union octeon_rxpciq rxpciq[LIO_MAX_IOQS_PER_IF];
601 /* ----------------------- THE LIO DEVICE --------------------------- */
603 * Each lio device has this structure to represent all its
607 /** PCI device pointer */
608 struct rte_pci_device *pci_dev;
610 /** Octeon Chip type */
615 /** This device's PCIe port used for traffic. */
618 /** The state of this device */
619 rte_atomic64_t status;
623 struct octeon_link_info linfo;
627 struct lio_fn_list fn_list;
631 /** Guards each glist */
632 rte_spinlock_t *glist_lock;
633 /** Array of gather component linked lists */
634 struct lio_stailq_head *glist_head;
636 /* The pool containing pre allocated buffers used for soft commands */
637 struct rte_mempool *sc_buf_pool;
639 /** The input instruction queues */
640 struct lio_instr_queue *instr_queue[LIO_MAX_POSSIBLE_INSTR_QUEUES];
642 /** The singly-linked tail queues of instruction response */
643 struct lio_response_list response_list;
647 /** The DROQ output queues */
648 struct lio_droq *droq[LIO_MAX_POSSIBLE_OUTPUT_QUEUES];
650 struct lio_io_enable io_qmask;
652 struct lio_sriov_info sriov_info;
654 struct lio_pf_vf_hs_word pfvf_hsword;
656 /** Mail Box details of each lio queue. */
657 struct lio_mbox **mbox;
659 char dev_string[LIO_DEVICE_NAME_LEN]; /* Device print string */
661 const struct lio_config *default_config;
663 struct rte_eth_dev *eth_dev;
666 uint8_t max_rx_queues;
667 uint8_t max_tx_queues;
668 uint8_t nb_rx_queues;
669 uint8_t nb_tx_queues;
670 uint8_t port_configured;
671 struct lio_rss_ctx rss_state;
674 #endif /* _LIO_STRUCT_H_ */