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34 #ifndef _LIO_STRUCT_H_
35 #define _LIO_STRUCT_H_
39 #include <sys/queue.h>
41 #include <rte_spinlock.h>
42 #include <rte_atomic.h>
44 #include "lio_hw_defs.h"
46 struct lio_stailq_node {
47 STAILQ_ENTRY(lio_stailq_node) entries;
50 STAILQ_HEAD(lio_stailq_head, lio_stailq_node);
59 /** The txpciq info passed to host from the firmware */
64 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
70 uint64_t aura_num : 10;
71 uint64_t reserved : 20;
73 uint64_t reserved : 20;
74 uint64_t aura_num : 10;
84 /** The instruction (input) queue.
85 * The input queue is used to post raw (instruction) mode data or packet
86 * data to Octeon device from the host. Each input queue for
87 * a LIO device has one such structure to represent it.
89 struct lio_instr_queue {
90 /** A spinlock to protect access to the input ring. */
93 rte_spinlock_t post_lock;
95 struct lio_device *lio_dev;
99 rte_atomic64_t iq_flush_running;
101 /** Flag that indicates if the queue uses 64 byte commands. */
102 uint32_t iqcmd_64B:1;
105 union octeon_txpciq txpciq;
111 /** Maximum no. of instructions in this queue. */
114 /** Index in input ring where the driver should write the next packet */
115 uint32_t host_write_index;
117 /** Index in input ring where Octeon is expected to read the next
120 uint32_t lio_read_index;
122 /** This index aids in finding the window in the queue where Octeon
123 * has read the commands.
125 uint32_t flush_index;
127 /** This field keeps track of the instructions pending in this queue. */
128 rte_atomic64_t instr_pending;
130 /** Pointer to the Virtual Base addr of the input ring. */
133 struct lio_request_list *request_list;
135 /** Octeon doorbell register for the ring. */
138 /** Octeon instruction count register for this ring. */
141 /** Number of instructions pending to be posted to Octeon. */
144 /** DMA mapped base address of the input descriptor ring. */
145 uint64_t base_addr_dma;
147 /** Application context */
150 /* network stack queue index */
154 const struct rte_memzone *iq_mz;
157 struct lio_io_enable {
164 void (*setup_iq_regs)(struct lio_device *, uint32_t);
166 int (*setup_mbox)(struct lio_device *);
167 void (*free_mbox)(struct lio_device *);
169 int (*setup_device_regs)(struct lio_device *);
172 struct lio_pf_vf_hs_word {
173 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
174 /** PKIND value assigned for the DPI interface */
177 /** OCTEON core clock multiplier */
178 uint64_t core_tics_per_us : 16;
180 /** OCTEON coprocessor clock multiplier */
181 uint64_t coproc_tics_per_us : 16;
183 /** app that currently running on OCTEON */
184 uint64_t app_mode : 8;
187 uint64_t reserved : 16;
189 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
192 uint64_t reserved : 16;
194 /** app that currently running on OCTEON */
195 uint64_t app_mode : 8;
197 /** OCTEON coprocessor clock multiplier */
198 uint64_t coproc_tics_per_us : 16;
200 /** OCTEON core clock multiplier */
201 uint64_t core_tics_per_us : 16;
203 /** PKIND value assigned for the DPI interface */
208 struct lio_sriov_info {
209 /** Number of rings assigned to VF */
210 uint32_t rings_per_vf;
212 /** Number of VF devices enabled */
216 /* Head of a response list */
217 struct lio_response_list {
218 /** List structure to add delete pending entries to */
219 struct lio_stailq_head head;
221 /** A lock for this response list */
224 rte_atomic64_t pending_req_count;
227 /* Structure to define the configuration attributes for each Input queue. */
228 struct lio_iq_config {
229 /* Max number of IQs available */
232 /** Pending list size (usually set to the sum of the size of all Input
235 uint32_t pending_list_size;
237 /** Command size - 32 or 64 bytes */
241 /* Structure to define the configuration attributes for each Output queue. */
242 struct lio_oq_config {
243 /* Max number of OQs available */
246 /** If set, the Output queue uses info-pointer mode. (Default: 1 ) */
249 /** The number of buffers that were consumed during packet processing by
250 * the driver on this Output queue before the driver attempts to
251 * replenish the descriptor ring with new buffers.
253 uint32_t refill_threshold;
256 /* Structure to define the configuration. */
259 const char *card_name;
261 /** Input Queue attributes. */
262 struct lio_iq_config iq;
264 /** Output Queue attributes. */
265 struct lio_oq_config oq;
269 int num_def_tx_descs;
271 /* Num of desc for rx rings */
272 int num_def_rx_descs;
277 /* ----------------------- THE LIO DEVICE --------------------------- */
279 * Each lio device has this structure to represent all its
283 /** PCI device pointer */
284 struct rte_pci_device *pci_dev;
286 /** Octeon Chip type */
293 struct lio_fn_list fn_list;
297 /* The pool containing pre allocated buffers used for soft commands */
298 struct rte_mempool *sc_buf_pool;
300 /** The input instruction queues */
301 struct lio_instr_queue *instr_queue[LIO_MAX_POSSIBLE_INSTR_QUEUES];
303 /** The singly-linked tail queues of instruction response */
304 struct lio_response_list response_list;
306 struct lio_io_enable io_qmask;
308 struct lio_sriov_info sriov_info;
310 struct lio_pf_vf_hs_word pfvf_hsword;
312 /** Mail Box details of each lio queue. */
313 struct lio_mbox **mbox;
315 char dev_string[LIO_DEVICE_NAME_LEN]; /* Device print string */
317 const struct lio_config *default_config;
319 struct rte_eth_dev *eth_dev;
321 uint8_t max_rx_queues;
322 uint8_t max_tx_queues;
323 uint8_t nb_rx_queues;
324 uint8_t nb_tx_queues;
325 uint8_t port_configured;
328 #endif /* _LIO_STRUCT_H_ */