4 * Copyright 2012 6WIND S.A.
5 * Copyright 2012 Mellanox
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of 6WIND S.A. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef RTE_PMD_MLX4_H_
35 #define RTE_PMD_MLX4_H_
40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
46 #pragma GCC diagnostic error "-Wpedantic"
49 /* Request send completion once in every 64 sends, might be less. */
50 #define MLX4_PMD_TX_PER_COMP_REQ 64
52 /* Maximum size for inline data. */
53 #define MLX4_PMD_MAX_INLINE 0
56 * Maximum number of cached Memory Pools (MPs) per TX queue. Each RTE MP
57 * from which buffers are to be transmitted will have to be mapped by this
58 * driver to their own Memory Region (MR). This is a slow operation.
60 * This value is always 1 for RX queues.
62 #ifndef MLX4_PMD_TX_MP_CACHE
63 #define MLX4_PMD_TX_MP_CACHE 8
67 #define MLX4_ALARM_TIMEOUT_US 100000
70 #define MLX4_PMD_PORT_KVARG "port"
73 PCI_VENDOR_ID_MELLANOX = 0x15b3,
77 PCI_DEVICE_ID_MELLANOX_CONNECTX3 = 0x1003,
78 PCI_DEVICE_ID_MELLANOX_CONNECTX3VF = 0x1004,
79 PCI_DEVICE_ID_MELLANOX_CONNECTX3PRO = 0x1007,
82 #define MLX4_DRIVER_NAME "net_mlx4"
84 struct mlx4_rxq_stats {
85 unsigned int idx; /**< Mapping index. */
86 uint64_t ipackets; /**< Total of successfully received packets. */
87 uint64_t ibytes; /**< Total of successfully received bytes. */
88 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
89 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
94 struct ibv_recv_wr wr; /* Work Request. */
95 struct ibv_sge sge; /* Scatter/Gather Element. */
96 struct rte_mbuf *buf; /**< Buffer. */
99 /* RX queue descriptor. */
101 struct priv *priv; /* Back pointer to private data. */
102 struct rte_mempool *mp; /* Memory Pool for allocations. */
103 struct ibv_mr *mr; /* Memory Region (for mp). */
104 struct ibv_cq *cq; /* Completion Queue. */
105 struct ibv_qp *qp; /* Queue Pair. */
106 struct ibv_comp_channel *channel;
107 unsigned int port_id; /* Port ID for incoming packets. */
108 unsigned int elts_n; /* (*elts)[] length. */
109 unsigned int elts_head; /* Current index in (*elts)[]. */
110 struct rxq_elt (*elts)[]; /* Rx elements. */
111 struct mlx4_rxq_stats stats; /* RX queue counters. */
112 unsigned int socket; /* CPU socket ID for allocations. */
117 struct ibv_send_wr wr; /* Work request. */
118 struct ibv_sge sge; /* Scatter/gather element. */
119 struct rte_mbuf *buf;
122 struct mlx4_txq_stats {
123 unsigned int idx; /**< Mapping index. */
124 uint64_t opackets; /**< Total of successfully sent packets. */
125 uint64_t obytes; /**< Total of successfully sent bytes. */
126 uint64_t odropped; /**< Total of packets not sent when TX ring full. */
129 /* TX queue descriptor. */
131 struct priv *priv; /* Back pointer to private data. */
133 const struct rte_mempool *mp; /* Cached Memory Pool. */
134 struct ibv_mr *mr; /* Memory Region (for mp). */
135 uint32_t lkey; /* mr->lkey */
136 } mp2mr[MLX4_PMD_TX_MP_CACHE]; /* MP to MR translation table. */
137 struct ibv_cq *cq; /* Completion Queue. */
138 struct ibv_qp *qp; /* Queue Pair. */
139 uint32_t max_inline; /* Max inline send size <= MLX4_PMD_MAX_INLINE. */
140 unsigned int elts_n; /* (*elts)[] length. */
141 struct txq_elt (*elts)[]; /* TX elements. */
142 unsigned int elts_head; /* Current index in (*elts)[]. */
143 unsigned int elts_tail; /* First element awaiting completion. */
144 unsigned int elts_comp; /* Number of completion requests. */
145 unsigned int elts_comp_cd; /* Countdown for next completion request. */
146 unsigned int elts_comp_cd_init; /* Initial value for countdown. */
147 struct mlx4_txq_stats stats; /* TX queue counters. */
148 unsigned int socket; /* CPU socket ID for allocations. */
154 struct rte_eth_dev *dev; /* Ethernet device. */
155 struct ibv_context *ctx; /* Verbs context. */
156 struct ibv_device_attr device_attr; /* Device properties. */
157 struct ibv_pd *pd; /* Protection Domain. */
158 struct ether_addr mac; /* MAC address. */
159 struct ibv_flow *mac_flow; /* Flow associated with MAC address. */
160 /* Device properties. */
161 uint16_t mtu; /* Configured MTU. */
162 uint8_t port; /* Physical port number. */
163 unsigned int started:1; /* Device started, flows enabled. */
164 unsigned int vf:1; /* This is a VF device. */
165 unsigned int pending_alarm:1; /* An alarm is pending. */
166 unsigned int isolated:1; /* Toggle isolated mode. */
168 unsigned int rxqs_n; /* RX queues array size. */
169 unsigned int txqs_n; /* TX queues array size. */
170 struct rxq *(*rxqs)[]; /* RX queues. */
171 struct txq *(*txqs)[]; /* TX queues. */
172 struct rte_intr_handle intr_handle; /* Port interrupt handle. */
173 struct rte_flow_drop *flow_drop_queue; /* Flow drop queue. */
174 LIST_HEAD(mlx4_flows, rte_flow) flows;
175 struct rte_intr_conf intr_conf; /* Active interrupt configuration. */
178 #endif /* RTE_PMD_MLX4_H_ */