1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2012 6WIND S.A.
3 * Copyright 2012 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX4_H_
7 #define RTE_PMD_MLX4_H_
11 #include <sys/queue.h>
13 /* Verbs headers do not support -pedantic. */
15 #pragma GCC diagnostic ignored "-Wpedantic"
17 #include <infiniband/verbs.h>
19 #pragma GCC diagnostic error "-Wpedantic"
22 #include <rte_ethdev_driver.h>
23 #include <rte_ether.h>
24 #include <rte_interrupts.h>
25 #include <rte_mempool.h>
26 #include <rte_rwlock.h>
30 #ifndef IBV_RX_HASH_INNER
31 /** This is not necessarily defined by supported RDMA core versions. */
32 #define IBV_RX_HASH_INNER (1ull << 31)
33 #endif /* IBV_RX_HASH_INNER */
35 /** Maximum number of simultaneous MAC addresses. This value is arbitrary. */
36 #define MLX4_MAX_MAC_ADDRESSES 128
38 /** Request send completion once in every 64 sends, might be less. */
39 #define MLX4_PMD_TX_PER_COMP_REQ 64
41 /** Maximum size for inline data. */
42 #define MLX4_PMD_MAX_INLINE 0
44 /** Fixed RSS hash key size in bytes. Cannot be modified. */
45 #define MLX4_RSS_HASH_KEY_SIZE 40
47 /** Interrupt alarm timeout value in microseconds. */
48 #define MLX4_INTR_ALARM_TIMEOUT 100000
50 /* Maximum packet headers size (L2+L3+L4) for TSO. */
51 #define MLX4_MAX_TSO_HEADER 192
53 /** Port parameter. */
54 #define MLX4_PMD_PORT_KVARG "port"
57 PCI_VENDOR_ID_MELLANOX = 0x15b3,
61 PCI_DEVICE_ID_MELLANOX_CONNECTX3 = 0x1003,
62 PCI_DEVICE_ID_MELLANOX_CONNECTX3VF = 0x1004,
63 PCI_DEVICE_ID_MELLANOX_CONNECTX3PRO = 0x1007,
66 /** Driver name reported to lower layers and used in log output. */
67 #define MLX4_DRIVER_NAME "net_mlx4"
76 * Type of objet being allocated.
78 enum mlx4_verbs_alloc_type {
79 MLX4_VERBS_ALLOC_TYPE_NONE,
80 MLX4_VERBS_ALLOC_TYPE_TX_QUEUE,
81 MLX4_VERBS_ALLOC_TYPE_RX_QUEUE,
85 * Verbs allocator needs a context to know in the callback which kind of
86 * resources it is allocating.
88 struct mlx4_verbs_alloc_ctx {
89 enum mlx4_verbs_alloc_type type; /* Kind of object being allocated. */
90 const void *obj; /* Pointer to the DPDK object. */
93 LIST_HEAD(mlx4_dev_list, mlx4_priv);
94 LIST_HEAD(mlx4_mr_list, mlx4_mr);
96 /** Private data structure. */
98 LIST_ENTRY(mlx4_priv) mem_event_cb;
99 /**< Called by memory event callback. */
100 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
101 struct ibv_context *ctx; /**< Verbs context. */
102 struct ibv_device_attr device_attr; /**< Device properties. */
103 struct ibv_pd *pd; /**< Protection Domain. */
104 /* Device properties. */
105 uint16_t mtu; /**< Configured MTU. */
106 uint8_t port; /**< Physical port number. */
107 uint32_t started:1; /**< Device started, flows enabled. */
108 uint32_t vf:1; /**< This is a VF device. */
109 uint32_t intr_alarm:1; /**< An interrupt alarm is scheduled. */
110 uint32_t isolated:1; /**< Toggle isolated mode. */
111 uint32_t rss_init:1; /**< Common RSS context is initialized. */
112 uint32_t hw_csum:1; /**< Checksum offload is supported. */
113 uint32_t hw_csum_l2tun:1; /**< Checksum support for L2 tunnels. */
114 uint32_t hw_fcs_strip:1; /**< FCS stripping toggling is supported. */
115 uint32_t tso:1; /**< Transmit segmentation offload is supported. */
116 uint32_t tso_max_payload_sz; /**< Max supported TSO payload size. */
117 uint32_t hw_rss_max_qps; /**< Max Rx Queues supported by RSS. */
118 uint64_t hw_rss_sup; /**< Supported RSS hash fields (Verbs format). */
119 struct rte_intr_handle intr_handle; /**< Port interrupt handle. */
120 struct mlx4_drop *drop; /**< Shared resources for drop flow rules. */
122 uint32_t dev_gen; /* Generation number to flush local caches. */
123 rte_rwlock_t rwlock; /* MR Lock. */
124 struct mlx4_mr_btree cache; /* Global MR cache table. */
125 struct mlx4_mr_list mr_list; /* Registered MR list. */
126 struct mlx4_mr_list mr_free_list; /* Freed MR list. */
128 LIST_HEAD(, mlx4_rss) rss; /**< Shared targets for Rx flow rules. */
129 LIST_HEAD(, rte_flow) flows; /**< Configured flow rule handles. */
130 struct ether_addr mac[MLX4_MAX_MAC_ADDRESSES];
131 /**< Configured MAC addresses. Unused entries are zeroed. */
132 struct mlx4_verbs_alloc_ctx verbs_alloc_ctx;
133 /**< Context for Verbs allocator. */
136 #define PORT_ID(priv) ((priv)->dev_data->port_id)
137 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
141 int mlx4_get_ifname(const struct mlx4_priv *priv, char (*ifname)[IF_NAMESIZE]);
142 int mlx4_get_mac(struct mlx4_priv *priv, uint8_t (*mac)[ETHER_ADDR_LEN]);
143 int mlx4_mtu_get(struct mlx4_priv *priv, uint16_t *mtu);
144 int mlx4_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
145 int mlx4_dev_set_link_down(struct rte_eth_dev *dev);
146 int mlx4_dev_set_link_up(struct rte_eth_dev *dev);
147 void mlx4_promiscuous_enable(struct rte_eth_dev *dev);
148 void mlx4_promiscuous_disable(struct rte_eth_dev *dev);
149 void mlx4_allmulticast_enable(struct rte_eth_dev *dev);
150 void mlx4_allmulticast_disable(struct rte_eth_dev *dev);
151 void mlx4_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
152 int mlx4_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
153 uint32_t index, uint32_t vmdq);
154 int mlx4_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr);
155 int mlx4_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
156 int mlx4_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
157 void mlx4_stats_reset(struct rte_eth_dev *dev);
158 int mlx4_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
159 void mlx4_dev_infos_get(struct rte_eth_dev *dev,
160 struct rte_eth_dev_info *info);
161 int mlx4_link_update(struct rte_eth_dev *dev, int wait_to_complete);
162 int mlx4_flow_ctrl_get(struct rte_eth_dev *dev,
163 struct rte_eth_fc_conf *fc_conf);
164 int mlx4_flow_ctrl_set(struct rte_eth_dev *dev,
165 struct rte_eth_fc_conf *fc_conf);
166 const uint32_t *mlx4_dev_supported_ptypes_get(struct rte_eth_dev *dev);
167 int mlx4_is_removed(struct rte_eth_dev *dev);
171 int mlx4_intr_uninstall(struct mlx4_priv *priv);
172 int mlx4_intr_install(struct mlx4_priv *priv);
173 int mlx4_rxq_intr_enable(struct mlx4_priv *priv);
174 void mlx4_rxq_intr_disable(struct mlx4_priv *priv);
175 int mlx4_rx_intr_disable(struct rte_eth_dev *dev, uint16_t idx);
176 int mlx4_rx_intr_enable(struct rte_eth_dev *dev, uint16_t idx);
178 #endif /* RTE_PMD_MLX4_H_ */