4 * Copyright 2012 6WIND S.A.
5 * Copyright 2012 Mellanox
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34 #ifndef RTE_PMD_MLX4_H_
35 #define RTE_PMD_MLX4_H_
41 * Runtime logging through RTE_LOG() is enabled when not in debugging mode.
42 * Intermediate LOG_*() macros add the required end-of-line characters.
45 #define INFO(...) DEBUG(__VA_ARGS__)
46 #define WARN(...) DEBUG(__VA_ARGS__)
47 #define ERROR(...) DEBUG(__VA_ARGS__)
49 #define LOG__(level, m, ...) \
50 RTE_LOG(level, PMD, MLX4_DRIVER_NAME ": " m "%c", __VA_ARGS__)
51 #define LOG_(level, ...) LOG__(level, __VA_ARGS__, '\n')
52 #define INFO(...) LOG_(INFO, __VA_ARGS__)
53 #define WARN(...) LOG_(WARNING, __VA_ARGS__)
54 #define ERROR(...) LOG_(ERR, __VA_ARGS__)
58 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
60 #pragma GCC diagnostic ignored "-Wpedantic"
62 #include <infiniband/verbs.h>
64 #pragma GCC diagnostic error "-Wpedantic"
68 * Maximum number of simultaneous MAC addresses supported.
70 * According to ConnectX's Programmer Reference Manual:
71 * The L2 Address Match is implemented by comparing a MAC/VLAN combination
72 * of 128 MAC addresses and 127 VLAN values, comprising 128x127 possible
75 #define MLX4_MAX_MAC_ADDRESSES 128
77 /* Maximum number of simultaneous VLAN filters supported. See above. */
78 #define MLX4_MAX_VLAN_IDS 127
80 /* Request send completion once in every 64 sends, might be less. */
81 #define MLX4_PMD_TX_PER_COMP_REQ 64
83 /* Maximum number of Scatter/Gather Elements per Work Request. */
84 #define MLX4_PMD_SGE_WR_N 4
86 /* Maximum size for inline data. */
87 #define MLX4_PMD_MAX_INLINE 0
90 * Maximum number of cached Memory Pools (MPs) per TX queue. Each RTE MP
91 * from which buffers are to be transmitted will have to be mapped by this
92 * driver to their own Memory Region (MR). This is a slow operation.
94 * This value is always 1 for RX queues.
96 #ifndef MLX4_PMD_TX_MP_CACHE
97 #define MLX4_PMD_TX_MP_CACHE 8
101 #define MLX4_ALARM_TIMEOUT_US 100000
103 /* Port parameter. */
104 #define MLX4_PMD_PORT_KVARG "port"
107 PCI_VENDOR_ID_MELLANOX = 0x15b3,
111 PCI_DEVICE_ID_MELLANOX_CONNECTX3 = 0x1003,
112 PCI_DEVICE_ID_MELLANOX_CONNECTX3VF = 0x1004,
113 PCI_DEVICE_ID_MELLANOX_CONNECTX3PRO = 0x1007,
116 #define MLX4_DRIVER_NAME "net_mlx4"
118 /* Bit-field manipulation. */
119 #define BITFIELD_DECLARE(bf, type, size) \
120 type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \
121 !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))]
122 #define BITFIELD_DEFINE(bf, type, size) \
123 BITFIELD_DECLARE((bf), type, (size)) = { 0 }
124 #define BITFIELD_SET(bf, b) \
125 (assert((size_t)(b) < (sizeof(bf) * CHAR_BIT)), \
126 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \
127 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))))
128 #define BITFIELD_RESET(bf, b) \
129 (assert((size_t)(b) < (sizeof(bf) * CHAR_BIT)), \
130 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \
131 ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))))
132 #define BITFIELD_ISSET(bf, b) \
133 (assert((size_t)(b) < (sizeof(bf) * CHAR_BIT)), \
134 !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \
135 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))))
137 /* Number of elements in array. */
138 #define elemof(a) (sizeof(a) / sizeof((a)[0]))
143 #define DEBUG__(m, ...) \
144 (fprintf(stderr, "%s:%d: %s(): " m "%c", \
145 __FILE__, __LINE__, __func__, __VA_ARGS__), \
149 * Save/restore errno around DEBUG__().
150 * XXX somewhat undefined behavior, but works.
152 #define DEBUG_(...) \
153 (errno = ((int []){ \
154 *(volatile int *)&errno, \
155 (DEBUG__(__VA_ARGS__), 0) \
157 #define DEBUG(...) DEBUG_(__VA_ARGS__, '\n')
158 #ifndef MLX4_PMD_DEBUG_BROKEN_VERBS
159 #define claim_zero(...) assert((__VA_ARGS__) == 0)
160 #else /* MLX4_PMD_DEBUG_BROKEN_VERBS */
161 #define claim_zero(...) \
162 (void)(((__VA_ARGS__) == 0) || \
163 DEBUG("Assertion `(" # __VA_ARGS__ ") == 0' failed (IGNORED)."))
164 #endif /* MLX4_PMD_DEBUG_BROKEN_VERBS */
165 #define claim_nonzero(...) assert((__VA_ARGS__) != 0)
166 #define claim_positive(...) assert((__VA_ARGS__) >= 0)
169 #define DEBUG(...) (void)0
170 #define claim_zero(...) (__VA_ARGS__)
171 #define claim_nonzero(...) (__VA_ARGS__)
172 #define claim_positive(...) (__VA_ARGS__)
175 struct mlx4_rxq_stats {
176 unsigned int idx; /**< Mapping index. */
177 uint64_t ipackets; /**< Total of successfully received packets. */
178 uint64_t ibytes; /**< Total of successfully received bytes. */
179 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
180 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
183 /* RX element (scattered packets). */
185 struct ibv_recv_wr wr; /* Work Request. */
186 struct ibv_sge sges[MLX4_PMD_SGE_WR_N]; /* Scatter/Gather Elements. */
187 struct rte_mbuf *bufs[MLX4_PMD_SGE_WR_N]; /* SGEs buffers. */
192 struct ibv_recv_wr wr; /* Work Request. */
193 struct ibv_sge sge; /* Scatter/Gather Element. */
194 /* mbuf pointer is derived from WR_ID(wr.wr_id).offset. */
197 /* RX queue descriptor. */
199 LIST_ENTRY(rxq) next; /* Used by parent queue only */
200 struct priv *priv; /* Back pointer to private data. */
201 struct rte_mempool *mp; /* Memory Pool for allocations. */
202 struct ibv_mr *mr; /* Memory Region (for mp). */
203 struct ibv_cq *cq; /* Completion Queue. */
204 struct ibv_qp *qp; /* Queue Pair. */
205 struct ibv_exp_qp_burst_family *if_qp; /* QP burst interface. */
206 struct ibv_exp_cq_family *if_cq; /* CQ interface. */
207 struct ibv_comp_channel *channel;
209 * Each VLAN ID requires a separate flow steering rule.
211 BITFIELD_DECLARE(mac_configured, uint32_t, MLX4_MAX_MAC_ADDRESSES);
212 struct ibv_flow *mac_flow[MLX4_MAX_MAC_ADDRESSES][MLX4_MAX_VLAN_IDS];
213 unsigned int port_id; /* Port ID for incoming packets. */
214 unsigned int elts_n; /* (*elts)[] length. */
215 unsigned int elts_head; /* Current index in (*elts)[]. */
217 struct rxq_elt_sp (*sp)[]; /* Scattered RX elements. */
218 struct rxq_elt (*no_sp)[]; /* RX elements. */
220 unsigned int sp:1; /* Use scattered RX elements. */
221 unsigned int csum:1; /* Enable checksum offloading. */
222 unsigned int csum_l2tun:1; /* Same for L2 tunnels. */
223 struct mlx4_rxq_stats stats; /* RX queue counters. */
224 unsigned int socket; /* CPU socket ID for allocations. */
225 struct ibv_exp_res_domain *rd; /* Resource Domain. */
228 uint16_t queues[RTE_MAX_QUEUES_PER_PORT];
234 struct rte_mbuf *buf;
237 struct mlx4_txq_stats {
238 unsigned int idx; /**< Mapping index. */
239 uint64_t opackets; /**< Total of successfully sent packets. */
240 uint64_t obytes; /**< Total of successfully sent bytes. */
241 uint64_t odropped; /**< Total of packets not sent when TX ring full. */
245 * Linear buffer type. It is used when transmitting buffers with too many
246 * segments that do not fit the hardware queue (see max_send_sge).
247 * Extra segments are copied (linearized) in such buffers, replacing the
248 * last SGE during TX.
249 * The size is arbitrary but large enough to hold a jumbo frame with
250 * 8 segments considering mbuf.buf_len is about 2048 bytes.
252 typedef uint8_t linear_t[16384];
254 /* TX queue descriptor. */
256 struct priv *priv; /* Back pointer to private data. */
258 const struct rte_mempool *mp; /* Cached Memory Pool. */
259 struct ibv_mr *mr; /* Memory Region (for mp). */
260 uint32_t lkey; /* mr->lkey */
261 } mp2mr[MLX4_PMD_TX_MP_CACHE]; /* MP to MR translation table. */
262 struct ibv_cq *cq; /* Completion Queue. */
263 struct ibv_qp *qp; /* Queue Pair. */
264 struct ibv_exp_qp_burst_family *if_qp; /* QP burst interface. */
265 struct ibv_exp_cq_family *if_cq; /* CQ interface. */
266 uint32_t max_inline; /* Max inline send size <= MLX4_PMD_MAX_INLINE. */
267 unsigned int elts_n; /* (*elts)[] length. */
268 struct txq_elt (*elts)[]; /* TX elements. */
269 unsigned int elts_head; /* Current index in (*elts)[]. */
270 unsigned int elts_tail; /* First element awaiting completion. */
271 unsigned int elts_comp; /* Number of completion requests. */
272 unsigned int elts_comp_cd; /* Countdown for next completion request. */
273 unsigned int elts_comp_cd_init; /* Initial value for countdown. */
274 struct mlx4_txq_stats stats; /* TX queue counters. */
275 linear_t (*elts_linear)[]; /* Linearized buffers. */
276 struct ibv_mr *mr_linear; /* Memory Region for linearized buffers. */
277 unsigned int socket; /* CPU socket ID for allocations. */
278 struct ibv_exp_res_domain *rd; /* Resource Domain. */
284 struct rte_eth_dev *dev; /* Ethernet device. */
285 struct ibv_context *ctx; /* Verbs context. */
286 struct ibv_device_attr device_attr; /* Device properties. */
287 struct ibv_pd *pd; /* Protection Domain. */
289 * MAC addresses array and configuration bit-field.
290 * An extra entry that cannot be modified by the DPDK is reserved
291 * for broadcast frames (destination MAC address ff:ff:ff:ff:ff:ff).
293 struct ether_addr mac[MLX4_MAX_MAC_ADDRESSES];
294 BITFIELD_DECLARE(mac_configured, uint32_t, MLX4_MAX_MAC_ADDRESSES);
297 unsigned int enabled:1; /* If enabled. */
298 unsigned int id:12; /* VLAN ID (0-4095). */
299 } vlan_filter[MLX4_MAX_VLAN_IDS]; /* VLAN filters table. */
300 /* Device properties. */
301 uint16_t mtu; /* Configured MTU. */
302 uint8_t port; /* Physical port number. */
303 unsigned int started:1; /* Device started, flows enabled. */
304 unsigned int hw_qpg:1; /* QP groups are supported. */
305 unsigned int hw_tss:1; /* TSS is supported. */
306 unsigned int hw_rss:1; /* RSS is supported. */
307 unsigned int hw_csum:1; /* Checksum offload is supported. */
308 unsigned int hw_csum_l2tun:1; /* Same for L2 tunnels. */
309 unsigned int rss:1; /* RSS is enabled. */
310 unsigned int vf:1; /* This is a VF device. */
311 unsigned int pending_alarm:1; /* An alarm is pending. */
312 unsigned int isolated:1; /* Toggle isolated mode. */
313 unsigned int inl_recv_size; /* Inline recv size */
314 unsigned int max_rss_tbl_sz; /* Maximum number of RSS queues. */
316 unsigned int rxqs_n; /* RX queues array size. */
317 unsigned int txqs_n; /* TX queues array size. */
318 struct rxq *(*rxqs)[]; /* RX queues. */
319 struct txq *(*txqs)[]; /* TX queues. */
320 struct rte_intr_handle intr_handle_dev; /* Device interrupt handler. */
321 struct rte_intr_handle intr_handle; /* Interrupt handler. */
322 struct rte_flow_drop *flow_drop_queue; /* Flow drop queue. */
323 LIST_HEAD(mlx4_flows, rte_flow) flows;
324 struct rte_intr_conf intr_conf; /* Active interrupt configuration. */
325 LIST_HEAD(mlx4_parents, rxq) parents;
326 rte_spinlock_t lock; /* Lock for control functions. */
329 void priv_lock(struct priv *priv);
330 void priv_unlock(struct priv *priv);
333 rxq_create_qp(struct rxq *rxq,
337 struct rxq *rxq_parent);
340 rxq_parent_cleanup(struct rxq *parent);
343 priv_parent_create(struct priv *priv,
345 uint16_t children_n);
347 #endif /* RTE_PMD_MLX4_H_ */