1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2012 6WIND S.A.
3 * Copyright 2012 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX4_H_
7 #define RTE_PMD_MLX4_H_
11 #include <sys/queue.h>
13 /* Verbs headers do not support -pedantic. */
15 #pragma GCC diagnostic ignored "-Wpedantic"
17 #include <infiniband/verbs.h>
19 #pragma GCC diagnostic error "-Wpedantic"
22 #include <rte_ethdev_driver.h>
23 #include <rte_ether.h>
24 #include <rte_interrupts.h>
25 #include <rte_mempool.h>
26 #include <rte_rwlock.h>
30 #ifndef IBV_RX_HASH_INNER
31 /** This is not necessarily defined by supported RDMA core versions. */
32 #define IBV_RX_HASH_INNER (1ull << 31)
33 #endif /* IBV_RX_HASH_INNER */
35 /** Maximum number of simultaneous MAC addresses. This value is arbitrary. */
36 #define MLX4_MAX_MAC_ADDRESSES 128
38 /** Request send completion once in every 64 sends, might be less. */
39 #define MLX4_PMD_TX_PER_COMP_REQ 64
41 /** Maximum size for inline data. */
42 #define MLX4_PMD_MAX_INLINE 0
44 /** Fixed RSS hash key size in bytes. Cannot be modified. */
45 #define MLX4_RSS_HASH_KEY_SIZE 40
47 /** Interrupt alarm timeout value in microseconds. */
48 #define MLX4_INTR_ALARM_TIMEOUT 100000
50 /* Maximum packet headers size (L2+L3+L4) for TSO. */
51 #define MLX4_MAX_TSO_HEADER 192
53 /** Port parameter. */
54 #define MLX4_PMD_PORT_KVARG "port"
57 PCI_VENDOR_ID_MELLANOX = 0x15b3,
61 PCI_DEVICE_ID_MELLANOX_CONNECTX3 = 0x1003,
62 PCI_DEVICE_ID_MELLANOX_CONNECTX3VF = 0x1004,
63 PCI_DEVICE_ID_MELLANOX_CONNECTX3PRO = 0x1007,
66 /** Driver name reported to lower layers and used in log output. */
67 #define MLX4_DRIVER_NAME "net_mlx4"
75 LIST_HEAD(mlx4_dev_list, priv);
76 LIST_HEAD(mlx4_mr_list, mlx4_mr);
78 /** Private data structure. */
80 LIST_ENTRY(priv) mem_event_cb; /* Called by memory event callback. */
81 struct rte_eth_dev *dev; /**< Ethernet device. */
82 struct ibv_context *ctx; /**< Verbs context. */
83 struct ibv_device_attr device_attr; /**< Device properties. */
84 struct ibv_pd *pd; /**< Protection Domain. */
85 /* Device properties. */
86 uint16_t mtu; /**< Configured MTU. */
87 uint8_t port; /**< Physical port number. */
88 uint32_t started:1; /**< Device started, flows enabled. */
89 uint32_t vf:1; /**< This is a VF device. */
90 uint32_t intr_alarm:1; /**< An interrupt alarm is scheduled. */
91 uint32_t isolated:1; /**< Toggle isolated mode. */
92 uint32_t rss_init:1; /**< Common RSS context is initialized. */
93 uint32_t hw_csum:1; /**< Checksum offload is supported. */
94 uint32_t hw_csum_l2tun:1; /**< Checksum support for L2 tunnels. */
95 uint32_t hw_fcs_strip:1; /**< FCS stripping toggling is supported. */
96 uint32_t tso:1; /**< Transmit segmentation offload is supported. */
97 uint32_t tso_max_payload_sz; /**< Max supported TSO payload size. */
98 uint32_t hw_rss_max_qps; /**< Max Rx Queues supported by RSS. */
99 uint64_t hw_rss_sup; /**< Supported RSS hash fields (Verbs format). */
100 struct rte_intr_handle intr_handle; /**< Port interrupt handle. */
101 struct mlx4_drop *drop; /**< Shared resources for drop flow rules. */
103 uint32_t dev_gen; /* Generation number to flush local caches. */
104 rte_rwlock_t rwlock; /* MR Lock. */
105 struct mlx4_mr_btree cache; /* Global MR cache table. */
106 struct mlx4_mr_list mr_list; /* Registered MR list. */
107 struct mlx4_mr_list mr_free_list; /* Freed MR list. */
109 LIST_HEAD(, mlx4_rss) rss; /**< Shared targets for Rx flow rules. */
110 LIST_HEAD(, rte_flow) flows; /**< Configured flow rule handles. */
111 struct ether_addr mac[MLX4_MAX_MAC_ADDRESSES];
112 /**< Configured MAC addresses. Unused entries are zeroed. */
117 int mlx4_get_ifname(const struct priv *priv, char (*ifname)[IF_NAMESIZE]);
118 int mlx4_get_mac(struct priv *priv, uint8_t (*mac)[ETHER_ADDR_LEN]);
119 int mlx4_mtu_get(struct priv *priv, uint16_t *mtu);
120 int mlx4_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
121 int mlx4_dev_set_link_down(struct rte_eth_dev *dev);
122 int mlx4_dev_set_link_up(struct rte_eth_dev *dev);
123 void mlx4_promiscuous_enable(struct rte_eth_dev *dev);
124 void mlx4_promiscuous_disable(struct rte_eth_dev *dev);
125 void mlx4_allmulticast_enable(struct rte_eth_dev *dev);
126 void mlx4_allmulticast_disable(struct rte_eth_dev *dev);
127 void mlx4_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
128 int mlx4_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
129 uint32_t index, uint32_t vmdq);
130 int mlx4_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr);
131 int mlx4_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
132 int mlx4_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
133 void mlx4_stats_reset(struct rte_eth_dev *dev);
134 void mlx4_dev_infos_get(struct rte_eth_dev *dev,
135 struct rte_eth_dev_info *info);
136 int mlx4_link_update(struct rte_eth_dev *dev, int wait_to_complete);
137 int mlx4_flow_ctrl_get(struct rte_eth_dev *dev,
138 struct rte_eth_fc_conf *fc_conf);
139 int mlx4_flow_ctrl_set(struct rte_eth_dev *dev,
140 struct rte_eth_fc_conf *fc_conf);
141 const uint32_t *mlx4_dev_supported_ptypes_get(struct rte_eth_dev *dev);
142 int mlx4_is_removed(struct rte_eth_dev *dev);
146 int mlx4_intr_uninstall(struct priv *priv);
147 int mlx4_intr_install(struct priv *priv);
148 int mlx4_rxq_intr_enable(struct priv *priv);
149 void mlx4_rxq_intr_disable(struct priv *priv);
150 int mlx4_rx_intr_disable(struct rte_eth_dev *dev, uint16_t idx);
151 int mlx4_rx_intr_enable(struct rte_eth_dev *dev, uint16_t idx);
153 #endif /* RTE_PMD_MLX4_H_ */