4 * Copyright 2012 6WIND S.A.
5 * Copyright 2012 Mellanox
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34 #ifndef RTE_PMD_MLX4_H_
35 #define RTE_PMD_MLX4_H_
39 #include <sys/queue.h>
41 /* Verbs headers do not support -pedantic. */
43 #pragma GCC diagnostic ignored "-Wpedantic"
45 #include <infiniband/verbs.h>
47 #pragma GCC diagnostic error "-Wpedantic"
50 #include <rte_ethdev.h>
51 #include <rte_ether.h>
52 #include <rte_interrupts.h>
53 #include <rte_mempool.h>
54 #include <rte_spinlock.h>
56 /** Maximum number of simultaneous MAC addresses. This value is arbitrary. */
57 #define MLX4_MAX_MAC_ADDRESSES 128
59 /** Request send completion once in every 64 sends, might be less. */
60 #define MLX4_PMD_TX_PER_COMP_REQ 64
62 /** Maximum size for inline data. */
63 #define MLX4_PMD_MAX_INLINE 0
65 /** Fixed RSS hash key size in bytes. Cannot be modified. */
66 #define MLX4_RSS_HASH_KEY_SIZE 40
69 * Maximum number of cached Memory Pools (MPs) per TX queue. Each RTE MP
70 * from which buffers are to be transmitted will have to be mapped by this
71 * driver to their own Memory Region (MR). This is a slow operation.
73 * This value is always 1 for RX queues.
75 #ifndef MLX4_PMD_TX_MP_CACHE
76 #define MLX4_PMD_TX_MP_CACHE 8
79 /** Interrupt alarm timeout value in microseconds. */
80 #define MLX4_INTR_ALARM_TIMEOUT 100000
82 /** Port parameter. */
83 #define MLX4_PMD_PORT_KVARG "port"
86 PCI_VENDOR_ID_MELLANOX = 0x15b3,
90 PCI_DEVICE_ID_MELLANOX_CONNECTX3 = 0x1003,
91 PCI_DEVICE_ID_MELLANOX_CONNECTX3VF = 0x1004,
92 PCI_DEVICE_ID_MELLANOX_CONNECTX3PRO = 0x1007,
95 /** Driver name reported to lower layers and used in log output. */
96 #define MLX4_DRIVER_NAME "net_mlx4"
104 /** Memory region descriptor. */
106 LIST_ENTRY(mlx4_mr) next; /**< Next entry in list. */
107 uintptr_t start; /**< Base address for memory region. */
108 uintptr_t end; /**< End address for memory region. */
109 uint32_t lkey; /**< L_Key extracted from @p mr. */
110 uint32_t refcnt; /**< Reference count for this object. */
111 struct priv *priv; /**< Back pointer to private data. */
112 struct ibv_mr *mr; /**< Memory region associated with @p mp. */
113 struct rte_mempool *mp; /**< Target memory pool (mempool). */
116 /** Private data structure. */
118 struct rte_eth_dev *dev; /**< Ethernet device. */
119 struct ibv_context *ctx; /**< Verbs context. */
120 struct ibv_device_attr device_attr; /**< Device properties. */
121 struct ibv_pd *pd; /**< Protection Domain. */
122 /* Device properties. */
123 uint16_t mtu; /**< Configured MTU. */
124 uint8_t port; /**< Physical port number. */
125 uint32_t started:1; /**< Device started, flows enabled. */
126 uint32_t vf:1; /**< This is a VF device. */
127 uint32_t intr_alarm:1; /**< An interrupt alarm is scheduled. */
128 uint32_t isolated:1; /**< Toggle isolated mode. */
129 uint32_t hw_csum:1; /* Checksum offload is supported. */
130 uint32_t hw_csum_l2tun:1; /* Checksum support for L2 tunnels. */
131 struct rte_intr_handle intr_handle; /**< Port interrupt handle. */
132 struct mlx4_drop *drop; /**< Shared resources for drop flow rules. */
133 LIST_HEAD(, mlx4_rss) rss; /**< Shared targets for Rx flow rules. */
134 LIST_HEAD(, rte_flow) flows; /**< Configured flow rule handles. */
135 LIST_HEAD(, mlx4_mr) mr; /**< Registered memory regions. */
136 rte_spinlock_t mr_lock; /**< Lock for @p mr access. */
137 struct ether_addr mac[MLX4_MAX_MAC_ADDRESSES];
138 /**< Configured MAC addresses. Unused entries are zeroed. */
143 int mlx4_get_ifname(const struct priv *priv, char (*ifname)[IF_NAMESIZE]);
144 int mlx4_get_mac(struct priv *priv, uint8_t (*mac)[ETHER_ADDR_LEN]);
145 int mlx4_mtu_get(struct priv *priv, uint16_t *mtu);
146 int mlx4_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
147 int mlx4_dev_set_link_down(struct rte_eth_dev *dev);
148 int mlx4_dev_set_link_up(struct rte_eth_dev *dev);
149 void mlx4_promiscuous_enable(struct rte_eth_dev *dev);
150 void mlx4_promiscuous_disable(struct rte_eth_dev *dev);
151 void mlx4_allmulticast_enable(struct rte_eth_dev *dev);
152 void mlx4_allmulticast_disable(struct rte_eth_dev *dev);
153 void mlx4_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
154 int mlx4_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
155 uint32_t index, uint32_t vmdq);
156 void mlx4_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr);
157 int mlx4_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
158 int mlx4_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
159 void mlx4_stats_reset(struct rte_eth_dev *dev);
160 void mlx4_dev_infos_get(struct rte_eth_dev *dev,
161 struct rte_eth_dev_info *info);
162 int mlx4_link_update(struct rte_eth_dev *dev, int wait_to_complete);
163 int mlx4_flow_ctrl_get(struct rte_eth_dev *dev,
164 struct rte_eth_fc_conf *fc_conf);
165 int mlx4_flow_ctrl_set(struct rte_eth_dev *dev,
166 struct rte_eth_fc_conf *fc_conf);
167 const uint32_t *mlx4_dev_supported_ptypes_get(struct rte_eth_dev *dev);
171 int mlx4_intr_uninstall(struct priv *priv);
172 int mlx4_intr_install(struct priv *priv);
173 int mlx4_rx_intr_disable(struct rte_eth_dev *dev, uint16_t idx);
174 int mlx4_rx_intr_enable(struct rte_eth_dev *dev, uint16_t idx);
178 struct mlx4_mr *mlx4_mr_get(struct priv *priv, struct rte_mempool *mp);
179 void mlx4_mr_put(struct mlx4_mr *mr);
180 uint32_t mlx4_txq_add_mr(struct txq *txq, struct rte_mempool *mp,
183 #endif /* RTE_PMD_MLX4_H_ */