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5 * Copyright 2017 Mellanox
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37 #include <rte_atomic.h>
38 #include <rte_branch_prediction.h>
39 #include <rte_byteorder.h>
41 /* Verbs headers do not support -pedantic. */
43 #pragma GCC diagnostic ignored "-Wpedantic"
45 #include <infiniband/mlx4dv.h>
46 #include <infiniband/verbs.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* ConnectX-3 Tx queue basic block. */
52 #define MLX4_TXBB_SHIFT 6
53 #define MLX4_TXBB_SIZE (1 << MLX4_TXBB_SHIFT)
55 /* Typical TSO descriptor with 16 gather entries is 352 bytes. */
56 #define MLX4_MAX_SGE 32
57 #define MLX4_MAX_WQE_SIZE \
58 (MLX4_MAX_SGE * sizeof(struct mlx4_wqe_data_seg) + \
59 sizeof(struct mlx4_wqe_ctrl_seg))
60 #define MLX4_SEG_SHIFT 4
62 /* Send queue stamping/invalidating information. */
63 #define MLX4_SQ_STAMP_STRIDE 64
64 #define MLX4_SQ_STAMP_DWORDS (MLX4_SQ_STAMP_STRIDE / 4)
65 #define MLX4_SQ_OWNER_BIT 31
66 #define MLX4_SQ_STAMP_VAL 0x7fffffff
68 /* Work queue element (WQE) flags. */
69 #define MLX4_WQE_CTRL_IIP_HDR_CSUM (1 << 28)
70 #define MLX4_WQE_CTRL_IL4_HDR_CSUM (1 << 27)
72 /* CQE checksum flags. */
74 MLX4_CQE_L2_TUNNEL_IPV4 = (int)(1u << 25),
75 MLX4_CQE_L2_TUNNEL_L4_CSUM = (int)(1u << 26),
76 MLX4_CQE_L2_TUNNEL = (int)(1u << 27),
77 MLX4_CQE_L2_VLAN_MASK = (int)(3u << 29),
78 MLX4_CQE_L2_TUNNEL_IPOK = (int)(1u << 31),
81 /* CQE status flags. */
82 #define MLX4_CQE_STATUS_IPV4 (1 << 22)
83 #define MLX4_CQE_STATUS_IPV4F (1 << 23)
84 #define MLX4_CQE_STATUS_IPV6 (1 << 24)
85 #define MLX4_CQE_STATUS_IPV4OPT (1 << 25)
86 #define MLX4_CQE_STATUS_TCP (1 << 26)
87 #define MLX4_CQE_STATUS_UDP (1 << 27)
88 #define MLX4_CQE_STATUS_PTYPE_MASK \
89 (MLX4_CQE_STATUS_IPV4 | \
90 MLX4_CQE_STATUS_IPV4F | \
91 MLX4_CQE_STATUS_IPV6 | \
92 MLX4_CQE_STATUS_IPV4OPT | \
93 MLX4_CQE_STATUS_TCP | \
96 /* Send queue information. */
98 volatile uint8_t *buf; /**< SQ buffer. */
99 volatile uint8_t *eob; /**< End of SQ buffer */
100 uint32_t size; /**< SQ size includes headroom. */
101 uint32_t remain_size; /**< Remaining WQE room in SQ (bytes). */
102 uint32_t owner_opcode;
103 /**< Default owner opcode with HW valid owner bit. */
104 uint32_t stamp; /**< Stamp value with an invalid HW owner bit. */
105 volatile uint32_t *db; /**< Pointer to the doorbell. */
106 uint32_t doorbell_qpn; /**< qp number to write to the doorbell. */
109 /* Completion queue events, numbers and masks. */
110 #define MLX4_CQ_DB_GEQ_N_MASK 0x3
111 #define MLX4_CQ_DOORBELL 0x20
112 #define MLX4_CQ_DB_CI_MASK 0xffffff
114 /* Completion queue information. */
116 volatile void *cq_uar; /**< CQ user access region. */
117 volatile void *cq_db_reg; /**< CQ doorbell register. */
118 volatile uint32_t *set_ci_db; /**< Pointer to the CQ doorbell. */
119 volatile uint32_t *arm_db; /**< Arming Rx events doorbell. */
120 volatile uint8_t *buf; /**< Pointer to the completion queue buffer. */
121 uint32_t cqe_cnt; /**< Number of entries in the queue. */
122 uint32_t cqe_64:1; /**< CQ entry size is 64 bytes. */
123 uint32_t cons_index; /**< Last queue entry that was handled. */
124 uint32_t cqn; /**< CQ number. */
125 int arm_sn; /**< Rx event counter. */
129 * Retrieve a CQE entry from a CQ.
131 * cqe = cq->buf + cons_index * cqe_size + cqe_offset
133 * Where cqe_size is 32 or 64 bytes and cqe_offset is 0 or 32 (depending on
137 * CQ to retrieve entry from.
142 * Pointer to CQE entry.
144 static inline volatile struct mlx4_cqe *
145 mlx4_get_cqe(struct mlx4_cq *cq, uint32_t index)
147 return (volatile struct mlx4_cqe *)(cq->buf +
148 ((index & (cq->cqe_cnt - 1)) <<
154 * Transpose a flag in a value.
159 * Flag to retrieve from input value.
161 * Flag to set in output value.
164 * Output value with transposed flag enabled if present on input.
166 static inline uint64_t
167 mlx4_transpose(uint64_t val, uint64_t from, uint64_t to)
170 (val & from) / (from / to) :
171 (val & from) * (to / from));
174 #endif /* MLX4_PRM_H_ */