4 * Copyright 2017 6WIND S.A.
5 * Copyright 2017 Mellanox
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36 * Data plane functions for mlx4 driver.
43 /* Verbs headers do not support -pedantic. */
45 #pragma GCC diagnostic ignored "-Wpedantic"
47 #include <infiniband/verbs.h>
49 #pragma GCC diagnostic error "-Wpedantic"
52 #include <rte_branch_prediction.h>
53 #include <rte_common.h>
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
61 #include "mlx4_rxtx.h"
62 #include "mlx4_utils.h"
64 #define WQE_ONE_DATA_SEG_SIZE \
65 (sizeof(struct mlx4_wqe_ctrl_seg) + sizeof(struct mlx4_wqe_data_seg))
68 * Pointer-value pair structure used in tx_post_send for saving the first
69 * DWORD (32 byte) of a TXBB.
72 volatile struct mlx4_wqe_data_seg *dseg;
76 /** A table to translate Rx completion flags to packet type. */
77 uint32_t mlx4_ptype_table[0x100] __rte_cache_aligned = {
79 * The index to the array should have:
80 * bit[7] - MLX4_CQE_L2_TUNNEL
81 * bit[6] - MLX4_CQE_L2_TUNNEL_IPV4
82 * bit[5] - MLX4_CQE_STATUS_UDP
83 * bit[4] - MLX4_CQE_STATUS_TCP
84 * bit[3] - MLX4_CQE_STATUS_IPV4OPT
85 * bit[2] - MLX4_CQE_STATUS_IPV6
86 * bit[1] - MLX4_CQE_STATUS_IPV4F
87 * bit[0] - MLX4_CQE_STATUS_IPV4
88 * giving a total of up to 256 entries.
90 [0x00] = RTE_PTYPE_L2_ETHER,
91 [0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
92 [0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
94 [0x03] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
96 [0x04] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
97 [0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT,
98 [0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
100 [0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
102 [0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
104 [0x14] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
106 [0x18] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
108 [0x19] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
110 [0x1a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
112 [0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
114 [0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
116 [0x24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
118 [0x28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
120 [0x29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
122 [0x2a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
124 /* Tunneled - L3 IPV6 */
125 [0x80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
126 [0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
127 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
128 [0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
129 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
130 RTE_PTYPE_INNER_L4_FRAG,
131 [0x83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
132 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
133 RTE_PTYPE_INNER_L4_FRAG,
134 [0x84] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
135 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
136 [0x88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
137 RTE_PTYPE_INNER_L3_IPV4_EXT,
138 [0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
139 RTE_PTYPE_INNER_L3_IPV4_EXT,
140 [0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
141 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG,
142 /* Tunneled - L3 IPV6, TCP */
143 [0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
144 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
145 RTE_PTYPE_INNER_L4_TCP,
146 [0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
147 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
148 RTE_PTYPE_INNER_L4_FRAG |
149 RTE_PTYPE_INNER_L4_TCP,
150 [0x93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
151 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
152 RTE_PTYPE_INNER_L4_FRAG |
153 RTE_PTYPE_INNER_L4_TCP,
154 [0x94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
155 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
156 RTE_PTYPE_INNER_L4_TCP,
157 [0x98] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
158 RTE_PTYPE_INNER_L3_IPV4_EXT |
159 RTE_PTYPE_INNER_L4_TCP,
160 [0x99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
161 RTE_PTYPE_INNER_L3_IPV4_EXT |
162 RTE_PTYPE_INNER_L4_TCP,
163 [0x9a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
164 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
165 RTE_PTYPE_INNER_L4_TCP,
166 /* Tunneled - L3 IPV6, UDP */
167 [0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
168 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
169 RTE_PTYPE_INNER_L4_UDP,
170 [0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
171 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
172 RTE_PTYPE_INNER_L4_FRAG |
173 RTE_PTYPE_INNER_L4_UDP,
174 [0xa3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
175 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
176 RTE_PTYPE_INNER_L4_FRAG |
177 RTE_PTYPE_INNER_L4_UDP,
178 [0xa4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
179 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
180 RTE_PTYPE_INNER_L4_UDP,
181 [0xa8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
182 RTE_PTYPE_INNER_L3_IPV4_EXT |
183 RTE_PTYPE_INNER_L4_UDP,
184 [0xa9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
185 RTE_PTYPE_INNER_L3_IPV4_EXT |
186 RTE_PTYPE_INNER_L4_UDP,
187 [0xaa] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
188 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
189 RTE_PTYPE_INNER_L4_UDP,
190 /* Tunneled - L3 IPV4 */
191 [0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
192 [0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
193 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
194 [0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
195 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
196 RTE_PTYPE_INNER_L4_FRAG,
197 [0xc3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
198 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
199 RTE_PTYPE_INNER_L4_FRAG,
200 [0xc4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
201 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
202 [0xc8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
203 RTE_PTYPE_INNER_L3_IPV4_EXT,
204 [0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
205 RTE_PTYPE_INNER_L3_IPV4_EXT,
206 [0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
207 RTE_PTYPE_INNER_L3_IPV4_EXT |
208 RTE_PTYPE_INNER_L4_FRAG,
209 /* Tunneled - L3 IPV4, TCP */
210 [0xd0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
211 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
212 RTE_PTYPE_INNER_L4_TCP,
213 [0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
214 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
215 RTE_PTYPE_INNER_L4_TCP,
216 [0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
217 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
218 RTE_PTYPE_INNER_L4_FRAG |
219 RTE_PTYPE_INNER_L4_TCP,
220 [0xd3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
221 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
222 RTE_PTYPE_INNER_L4_FRAG |
223 RTE_PTYPE_INNER_L4_TCP,
224 [0xd4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
225 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
226 RTE_PTYPE_INNER_L4_TCP,
227 [0xd8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
228 RTE_PTYPE_INNER_L3_IPV4_EXT |
229 RTE_PTYPE_INNER_L4_TCP,
230 [0xd9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
231 RTE_PTYPE_INNER_L3_IPV4_EXT |
232 RTE_PTYPE_INNER_L4_TCP,
233 [0xda] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
234 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
235 RTE_PTYPE_INNER_L4_TCP,
236 /* Tunneled - L3 IPV4, UDP */
237 [0xe0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
238 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
239 RTE_PTYPE_INNER_L4_UDP,
240 [0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
241 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
242 RTE_PTYPE_INNER_L4_UDP,
243 [0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
244 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
245 RTE_PTYPE_INNER_L4_FRAG |
246 RTE_PTYPE_INNER_L4_UDP,
247 [0xe3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
248 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
249 RTE_PTYPE_INNER_L4_FRAG |
250 RTE_PTYPE_INNER_L4_UDP,
251 [0xe4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
252 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
253 RTE_PTYPE_INNER_L4_UDP,
254 [0xe8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
255 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
256 [0xe9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
257 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
258 [0xea] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
259 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
260 RTE_PTYPE_INNER_L4_UDP,
264 * Stamp a WQE so it won't be reused by the HW.
266 * Routine is used when freeing WQE used by the chip or when failing
267 * building an WQ entry has failed leaving partial information on the queue.
270 * Pointer to the SQ structure.
272 * Index of the freed WQE.
274 * Number of blocks to stamp.
275 * If < 0 the routine will use the size written in the WQ entry.
277 * The value of the WQE owner bit to use in the stamp.
280 * The number of Tx basic blocs (TXBB) the WQE contained.
283 mlx4_txq_stamp_freed_wqe(struct mlx4_sq *sq, uint16_t index, uint8_t owner)
285 uint32_t stamp = rte_cpu_to_be_32(MLX4_SQ_STAMP_VAL |
286 (!!owner << MLX4_SQ_STAMP_SHIFT));
287 volatile uint8_t *wqe = mlx4_get_send_wqe(sq,
288 (index & sq->txbb_cnt_mask));
289 volatile uint32_t *ptr = (volatile uint32_t *)wqe;
294 /* Extract the size from the control segment of the WQE. */
295 num_txbbs = MLX4_SIZE_TO_TXBBS((((volatile struct mlx4_wqe_ctrl_seg *)
296 wqe)->fence_size & 0x3f) << 4);
297 txbbs_size = num_txbbs * MLX4_TXBB_SIZE;
298 /* Optimize the common case when there is no wrap-around. */
299 if (wqe + txbbs_size <= sq->eob) {
300 /* Stamp the freed descriptor. */
301 for (i = 0; i < txbbs_size; i += MLX4_SQ_STAMP_STRIDE) {
303 ptr += MLX4_SQ_STAMP_DWORDS;
306 /* Stamp the freed descriptor. */
307 for (i = 0; i < txbbs_size; i += MLX4_SQ_STAMP_STRIDE) {
309 ptr += MLX4_SQ_STAMP_DWORDS;
310 if ((volatile uint8_t *)ptr >= sq->eob) {
311 ptr = (volatile uint32_t *)sq->buf;
312 stamp ^= RTE_BE32(0x80000000);
320 * Manage Tx completions.
322 * When sending a burst, mlx4_tx_burst() posts several WRs.
323 * To improve performance, a completion event is only required once every
324 * MLX4_PMD_TX_PER_COMP_REQ sends. Doing so discards completion information
325 * for other WRs, but this information would not be used anyway.
328 * Pointer to Tx queue structure.
331 * 0 on success, -1 on failure.
334 mlx4_txq_complete(struct txq *txq, const unsigned int elts_n,
337 unsigned int elts_comp = txq->elts_comp;
338 unsigned int elts_tail = txq->elts_tail;
339 unsigned int sq_tail = sq->tail;
340 struct mlx4_cq *cq = &txq->mcq;
341 volatile struct mlx4_cqe *cqe;
342 uint32_t cons_index = cq->cons_index;
344 uint16_t nr_txbbs = 0;
348 * Traverse over all CQ entries reported and handle each WQ entry
352 cqe = (volatile struct mlx4_cqe *)mlx4_get_cqe(cq, cons_index);
353 if (unlikely(!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
354 !!(cons_index & cq->cqe_cnt)))
357 * Make sure we read the CQE after we read the ownership bit.
361 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
362 MLX4_CQE_OPCODE_ERROR)) {
363 volatile struct mlx4_err_cqe *cqe_err =
364 (volatile struct mlx4_err_cqe *)cqe;
365 ERROR("%p CQE error - vendor syndrome: 0x%x"
367 (void *)txq, cqe_err->vendor_err,
371 /* Get WQE index reported in the CQE. */
373 rte_be_to_cpu_16(cqe->wqe_index) & sq->txbb_cnt_mask;
375 /* Free next descriptor. */
378 mlx4_txq_stamp_freed_wqe(sq,
379 sq_tail & sq->txbb_cnt_mask,
380 !!(sq_tail & sq->txbb_cnt));
382 } while ((sq_tail & sq->txbb_cnt_mask) != new_index);
385 if (unlikely(pkts == 0))
388 cq->cons_index = cons_index;
389 *cq->set_ci_db = rte_cpu_to_be_32(cq->cons_index & MLX4_CQ_DB_CI_MASK);
390 sq->tail = sq_tail + nr_txbbs;
391 /* Update the list of packets posted for transmission. */
393 assert(elts_comp <= txq->elts_comp);
395 * Assume completion status is successful as nothing can be done about
399 if (elts_tail >= elts_n)
401 txq->elts_tail = elts_tail;
402 txq->elts_comp = elts_comp;
407 * Get memory pool (MP) from mbuf. If mbuf is indirect, the pool from which
408 * the cloned mbuf is allocated is returned instead.
414 * Memory pool where data is located for given mbuf.
416 static struct rte_mempool *
417 mlx4_txq_mb2mp(struct rte_mbuf *buf)
419 if (unlikely(RTE_MBUF_INDIRECT(buf)))
420 return rte_mbuf_from_indirect(buf)->pool;
425 mlx4_tx_burst_segs(struct rte_mbuf *buf, struct txq *txq,
426 volatile struct mlx4_wqe_ctrl_seg **pctrl)
430 struct pv *pv = (struct pv *)txq->bounce_buf;
431 struct mlx4_sq *sq = &txq->msq;
432 uint32_t head_idx = sq->head & sq->txbb_cnt_mask;
433 volatile struct mlx4_wqe_ctrl_seg *ctrl;
434 volatile struct mlx4_wqe_data_seg *dseg;
435 struct rte_mbuf *sbuf;
441 /* Calculate the needed work queue entry size for this packet. */
442 wqe_real_size = sizeof(volatile struct mlx4_wqe_ctrl_seg) +
443 buf->nb_segs * sizeof(volatile struct mlx4_wqe_data_seg);
444 nr_txbbs = MLX4_SIZE_TO_TXBBS(wqe_real_size);
446 * Check that there is room for this WQE in the send queue and that
447 * the WQE size is legal.
449 if (((sq->head - sq->tail) + nr_txbbs +
450 sq->headroom_txbbs) >= sq->txbb_cnt ||
451 nr_txbbs > MLX4_MAX_WQE_TXBBS) {
454 /* Get the control and data entries of the WQE. */
455 ctrl = (volatile struct mlx4_wqe_ctrl_seg *)
456 mlx4_get_send_wqe(sq, head_idx);
457 dseg = (volatile struct mlx4_wqe_data_seg *)
458 ((uintptr_t)ctrl + sizeof(struct mlx4_wqe_ctrl_seg));
460 /* Fill the data segments with buffer information. */
461 for (sbuf = buf; sbuf != NULL; sbuf = sbuf->next, dseg++) {
462 addr = rte_pktmbuf_mtod(sbuf, uintptr_t);
463 rte_prefetch0((volatile void *)addr);
464 /* Handle WQE wraparound. */
465 if (dseg >= (volatile struct mlx4_wqe_data_seg *)sq->eob)
466 dseg = (volatile struct mlx4_wqe_data_seg *)sq->buf;
467 dseg->addr = rte_cpu_to_be_64(addr);
468 /* Memory region key (big endian) for this memory pool. */
469 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
470 dseg->lkey = rte_cpu_to_be_32(lkey);
471 /* Calculate the needed work queue entry size for this packet */
472 if (unlikely(dseg->lkey == rte_cpu_to_be_32((uint32_t)-1))) {
473 /* MR does not exist. */
474 DEBUG("%p: unable to get MP <-> MR association",
477 * Restamp entry in case of failure.
478 * Make sure that size is written correctly
479 * Note that we give ownership to the SW, not the HW.
481 wqe_real_size = sizeof(struct mlx4_wqe_ctrl_seg) +
482 buf->nb_segs * sizeof(struct mlx4_wqe_data_seg);
483 ctrl->fence_size = (wqe_real_size >> 4) & 0x3f;
484 mlx4_txq_stamp_freed_wqe(sq, head_idx,
485 (sq->head & sq->txbb_cnt) ? 0 : 1);
488 if (likely(sbuf->data_len)) {
489 byte_count = rte_cpu_to_be_32(sbuf->data_len);
492 * Zero length segment is treated as inline segment
495 byte_count = RTE_BE32(0x80000000);
498 * If the data segment is not at the beginning of a
499 * Tx basic block (TXBB) then write the byte count,
500 * else postpone the writing to just before updating the
503 if ((uintptr_t)dseg & (uintptr_t)(MLX4_TXBB_SIZE - 1)) {
504 #if RTE_CACHE_LINE_SIZE < 64
506 * Need a barrier here before writing the byte_count
507 * fields to make sure that all the data is visible
508 * before the byte_count field is set.
509 * Otherwise, if the segment begins a new cacheline,
510 * the HCA prefetcher could grab the 64-byte chunk and
511 * get a valid (!= 0xffffffff) byte count but stale
512 * data, and end up sending the wrong data.
515 #endif /* RTE_CACHE_LINE_SIZE */
516 dseg->byte_count = byte_count;
519 * This data segment starts at the beginning of a new
520 * TXBB, so we need to postpone its byte_count writing
523 pv[pv_counter].dseg = dseg;
524 pv[pv_counter++].val = byte_count;
527 /* Write the first DWORD of each TXBB save earlier. */
529 /* Need a barrier here before writing the byte_count. */
531 for (--pv_counter; pv_counter >= 0; pv_counter--)
532 pv[pv_counter].dseg->byte_count = pv[pv_counter].val;
534 /* Fill the control parameters for this packet. */
535 ctrl->fence_size = (wqe_real_size >> 4) & 0x3f;
540 * DPDK callback for Tx.
543 * Generic pointer to Tx queue structure.
545 * Packets to transmit.
547 * Number of packets in array.
550 * Number of packets successfully transmitted (<= pkts_n).
553 mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
555 struct txq *txq = (struct txq *)dpdk_txq;
556 unsigned int elts_head = txq->elts_head;
557 const unsigned int elts_n = txq->elts_n;
558 unsigned int bytes_sent = 0;
561 struct mlx4_sq *sq = &txq->msq;
564 assert(txq->elts_comp_cd != 0);
565 if (likely(txq->elts_comp != 0))
566 mlx4_txq_complete(txq, elts_n, sq);
567 max = (elts_n - (elts_head - txq->elts_tail));
571 assert(max <= elts_n);
572 /* Always leave one free entry in the ring. */
576 for (i = 0; (i != max); ++i) {
577 struct rte_mbuf *buf = pkts[i];
578 unsigned int elts_head_next =
579 (((elts_head + 1) == elts_n) ? 0 : elts_head + 1);
580 struct txq_elt *elt_next = &(*txq->elts)[elts_head_next];
581 struct txq_elt *elt = &(*txq->elts)[elts_head];
582 uint32_t owner_opcode = MLX4_OPCODE_SEND;
583 volatile struct mlx4_wqe_ctrl_seg *ctrl;
584 volatile struct mlx4_wqe_data_seg *dseg;
589 uint32_t head_idx = sq->head & sq->txbb_cnt_mask;
593 /* Clean up old buffer. */
594 if (likely(elt->buf != NULL)) {
595 struct rte_mbuf *tmp = elt->buf;
599 memset(elt, 0x66, sizeof(*elt));
601 /* Faster than rte_pktmbuf_free(). */
603 struct rte_mbuf *next = tmp->next;
605 rte_pktmbuf_free_seg(tmp);
607 } while (tmp != NULL);
609 RTE_MBUF_PREFETCH_TO_FREE(elt_next->buf);
610 if (buf->nb_segs == 1) {
612 * Check that there is room for this WQE in the send
613 * queue and that the WQE size is legal
615 if (((sq->head - sq->tail) + 1 + sq->headroom_txbbs) >=
616 sq->txbb_cnt || 1 > MLX4_MAX_WQE_TXBBS) {
620 /* Get the control and data entries of the WQE. */
621 ctrl = (volatile struct mlx4_wqe_ctrl_seg *)
622 mlx4_get_send_wqe(sq, head_idx);
623 dseg = (volatile struct mlx4_wqe_data_seg *)
625 sizeof(struct mlx4_wqe_ctrl_seg));
626 addr = rte_pktmbuf_mtod(buf, uintptr_t);
627 rte_prefetch0((volatile void *)addr);
628 /* Handle WQE wraparound. */
630 (volatile struct mlx4_wqe_data_seg *)sq->eob)
631 dseg = (volatile struct mlx4_wqe_data_seg *)
633 dseg->addr = rte_cpu_to_be_64(addr);
634 /* Memory region key (big endian). */
635 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(buf));
636 dseg->lkey = rte_cpu_to_be_32(lkey);
637 if (unlikely(dseg->lkey ==
638 rte_cpu_to_be_32((uint32_t)-1))) {
639 /* MR does not exist. */
640 DEBUG("%p: unable to get MP <-> MR association",
643 * Restamp entry in case of failure.
644 * Make sure that size is written correctly
645 * Note that we give ownership to the SW,
649 (WQE_ONE_DATA_SEG_SIZE >> 4) & 0x3f;
650 mlx4_txq_stamp_freed_wqe(sq, head_idx,
651 (sq->head & sq->txbb_cnt) ? 0 : 1);
655 /* Never be TXBB aligned, no need compiler barrier. */
656 dseg->byte_count = rte_cpu_to_be_32(buf->data_len);
657 /* Fill the control parameters for this packet. */
658 ctrl->fence_size = (WQE_ONE_DATA_SEG_SIZE >> 4) & 0x3f;
661 nr_txbbs = mlx4_tx_burst_segs(buf, txq, &ctrl);
668 * For raw Ethernet, the SOLICIT flag is used to indicate
669 * that no ICRC should be calculated.
671 txq->elts_comp_cd -= nr_txbbs;
672 if (unlikely(txq->elts_comp_cd <= 0)) {
673 txq->elts_comp_cd = txq->elts_comp_cd_init;
674 srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT |
675 MLX4_WQE_CTRL_CQ_UPDATE);
677 srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT);
679 /* Enable HW checksum offload if requested */
682 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))) {
683 const uint64_t is_tunneled = (buf->ol_flags &
685 PKT_TX_TUNNEL_VXLAN));
687 if (is_tunneled && txq->csum_l2tun) {
688 owner_opcode |= MLX4_WQE_CTRL_IIP_HDR_CSUM |
689 MLX4_WQE_CTRL_IL4_HDR_CSUM;
690 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
692 RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM);
695 RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM |
696 MLX4_WQE_CTRL_TCP_UDP_CSUM);
701 * Copy destination MAC address to the WQE, this allows
702 * loopback in eSwitch, so that VFs and PF can
703 * communicate with each other.
705 srcrb.flags16[0] = *(rte_pktmbuf_mtod(buf, uint16_t *));
706 ctrl->imm = *(rte_pktmbuf_mtod_offset(buf, uint32_t *,
711 ctrl->srcrb_flags = srcrb.flags;
713 * Make sure descriptor is fully written before
714 * setting ownership bit (because HW can start
715 * executing as soon as we do).
718 ctrl->owner_opcode = rte_cpu_to_be_32(owner_opcode |
719 ((sq->head & sq->txbb_cnt) ?
720 MLX4_BIT_WQE_OWN : 0));
721 sq->head += nr_txbbs;
723 bytes_sent += buf->pkt_len;
724 elts_head = elts_head_next;
726 /* Take a shortcut if nothing must be sent. */
727 if (unlikely(i == 0))
729 /* Increment send statistics counters. */
730 txq->stats.opackets += i;
731 txq->stats.obytes += bytes_sent;
732 /* Make sure that descriptors are written before doorbell record. */
734 /* Ring QP doorbell. */
735 rte_write32(txq->msq.doorbell_qpn, txq->msq.db);
736 txq->elts_head = elts_head;
742 * Translate Rx completion flags to packet type.
748 * Packet type for struct rte_mbuf.
750 static inline uint32_t
751 rxq_cq_to_pkt_type(volatile struct mlx4_cqe *cqe,
752 uint32_t l2tun_offload)
755 uint32_t pinfo = rte_be_to_cpu_32(cqe->vlan_my_qpn);
756 uint32_t status = rte_be_to_cpu_32(cqe->status);
759 * The index to the array should have:
760 * bit[7] - MLX4_CQE_L2_TUNNEL
761 * bit[6] - MLX4_CQE_L2_TUNNEL_IPV4
763 if (l2tun_offload && (pinfo & MLX4_CQE_L2_TUNNEL))
764 idx |= ((pinfo & MLX4_CQE_L2_TUNNEL) >> 20) |
765 ((pinfo & MLX4_CQE_L2_TUNNEL_IPV4) >> 19);
767 * The index to the array should have:
768 * bit[5] - MLX4_CQE_STATUS_UDP
769 * bit[4] - MLX4_CQE_STATUS_TCP
770 * bit[3] - MLX4_CQE_STATUS_IPV4OPT
771 * bit[2] - MLX4_CQE_STATUS_IPV6
772 * bit[1] - MLX4_CQE_STATUS_IPV4F
773 * bit[0] - MLX4_CQE_STATUS_IPV4
774 * giving a total of up to 256 entries.
776 idx |= ((status & MLX4_CQE_STATUS_PTYPE_MASK) >> 22);
777 return mlx4_ptype_table[idx];
781 * Translate Rx completion flags to offload flags.
784 * Rx completion flags returned by mlx4_cqe_flags().
786 * Whether Rx checksums are enabled.
788 * Whether Rx L2 tunnel checksums are enabled.
791 * Offload flags (ol_flags) in mbuf format.
793 static inline uint32_t
794 rxq_cq_to_ol_flags(uint32_t flags, int csum, int csum_l2tun)
796 uint32_t ol_flags = 0;
800 mlx4_transpose(flags,
801 MLX4_CQE_STATUS_IP_HDR_CSUM_OK,
802 PKT_RX_IP_CKSUM_GOOD) |
803 mlx4_transpose(flags,
804 MLX4_CQE_STATUS_TCP_UDP_CSUM_OK,
805 PKT_RX_L4_CKSUM_GOOD);
806 if ((flags & MLX4_CQE_L2_TUNNEL) && csum_l2tun)
808 mlx4_transpose(flags,
809 MLX4_CQE_L2_TUNNEL_IPOK,
810 PKT_RX_IP_CKSUM_GOOD) |
811 mlx4_transpose(flags,
812 MLX4_CQE_L2_TUNNEL_L4_CSUM,
813 PKT_RX_L4_CKSUM_GOOD);
818 * Extract checksum information from CQE flags.
821 * Pointer to CQE structure.
823 * Whether Rx checksums are enabled.
825 * Whether Rx L2 tunnel checksums are enabled.
828 * CQE checksum information.
830 static inline uint32_t
831 mlx4_cqe_flags(volatile struct mlx4_cqe *cqe, int csum, int csum_l2tun)
836 * The relevant bits are in different locations on their
837 * CQE fields therefore we can join them in one 32bit
841 flags = (rte_be_to_cpu_32(cqe->status) &
842 MLX4_CQE_STATUS_IPV4_CSUM_OK);
844 flags |= (rte_be_to_cpu_32(cqe->vlan_my_qpn) &
845 (MLX4_CQE_L2_TUNNEL |
846 MLX4_CQE_L2_TUNNEL_IPOK |
847 MLX4_CQE_L2_TUNNEL_L4_CSUM |
848 MLX4_CQE_L2_TUNNEL_IPV4));
853 * Poll one CQE from CQ.
856 * Pointer to the receive queue structure.
861 * Number of bytes of the CQE, 0 in case there is no completion.
864 mlx4_cq_poll_one(struct rxq *rxq, volatile struct mlx4_cqe **out)
867 volatile struct mlx4_cqe *cqe = NULL;
868 struct mlx4_cq *cq = &rxq->mcq;
870 cqe = (volatile struct mlx4_cqe *)mlx4_get_cqe(cq, cq->cons_index);
871 if (!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
872 !!(cq->cons_index & cq->cqe_cnt))
875 * Make sure we read CQ entry contents after we've checked the
879 assert(!(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK));
880 assert((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) !=
881 MLX4_CQE_OPCODE_ERROR);
882 ret = rte_be_to_cpu_32(cqe->byte_cnt);
890 * DPDK callback for Rx with scattered packets support.
893 * Generic pointer to Rx queue structure.
895 * Array to store received packets.
897 * Maximum number of packets in array.
900 * Number of packets successfully received (<= pkts_n).
903 mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
905 struct rxq *rxq = dpdk_rxq;
906 const uint32_t wr_cnt = (1 << rxq->elts_n) - 1;
907 const uint16_t sges_n = rxq->sges_n;
908 struct rte_mbuf *pkt = NULL;
909 struct rte_mbuf *seg = NULL;
911 uint32_t rq_ci = rxq->rq_ci << sges_n;
915 volatile struct mlx4_cqe *cqe;
916 uint32_t idx = rq_ci & wr_cnt;
917 struct rte_mbuf *rep = (*rxq->elts)[idx];
918 volatile struct mlx4_wqe_data_seg *scat = &(*rxq->wqes)[idx];
920 /* Update the 'next' pointer of the previous segment. */
926 rep = rte_mbuf_raw_alloc(rxq->mp);
927 if (unlikely(rep == NULL)) {
928 ++rxq->stats.rx_nombuf;
931 * No buffers before we even started,
937 assert(pkt != (*rxq->elts)[idx]);
941 rte_mbuf_raw_free(pkt);
947 /* Looking for the new packet. */
948 len = mlx4_cq_poll_one(rxq, &cqe);
950 rte_mbuf_raw_free(rep);
953 if (unlikely(len < 0)) {
954 /* Rx error, packet is likely too large. */
955 rte_mbuf_raw_free(rep);
956 ++rxq->stats.idropped;
960 /* Update packet information. */
962 rxq_cq_to_pkt_type(cqe, rxq->l2tun_offload);
963 pkt->ol_flags = PKT_RX_RSS_HASH;
964 pkt->hash.rss = cqe->immed_rss_invalid;
966 if (rxq->csum | rxq->csum_l2tun) {
973 rxq_cq_to_ol_flags(flags,
979 rep->port = rxq->port_id;
980 rep->data_len = seg->data_len;
981 rep->data_off = seg->data_off;
982 (*rxq->elts)[idx] = rep;
984 * Fill NIC descriptor with the new buffer. The lkey and size
985 * of the buffers are already known, only the buffer address
988 scat->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
989 if (len > seg->data_len) {
990 len -= seg->data_len;
995 /* The last segment. */
997 /* Increment bytes counter. */
998 rxq->stats.ibytes += pkt->pkt_len;
1005 /* Align consumer index to the next stride. */
1010 if (unlikely(i == 0 && (rq_ci >> sges_n) == rxq->rq_ci))
1012 /* Update the consumer index. */
1013 rxq->rq_ci = rq_ci >> sges_n;
1015 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1016 *rxq->mcq.set_ci_db =
1017 rte_cpu_to_be_32(rxq->mcq.cons_index & MLX4_CQ_DB_CI_MASK);
1018 /* Increment packets counter. */
1019 rxq->stats.ipackets += i;
1024 * Dummy DPDK callback for Tx.
1026 * This function is used to temporarily replace the real callback during
1027 * unsafe control operations on the queue, or in case of error.
1030 * Generic pointer to Tx queue structure.
1032 * Packets to transmit.
1034 * Number of packets in array.
1037 * Number of packets successfully transmitted (<= pkts_n).
1040 mlx4_tx_burst_removed(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1049 * Dummy DPDK callback for Rx.
1051 * This function is used to temporarily replace the real callback during
1052 * unsafe control operations on the queue, or in case of error.
1055 * Generic pointer to Rx queue structure.
1057 * Array to store received packets.
1059 * Maximum number of packets in array.
1062 * Number of packets successfully received (<= pkts_n).
1065 mlx4_rx_burst_removed(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)