1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2017 6WIND S.A.
3 * Copyright 2017 Mellanox Technologies, Ltd
8 * Data plane functions for mlx4 driver.
15 /* Verbs headers do not support -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
24 #include <rte_branch_prediction.h>
25 #include <rte_common.h>
28 #include <rte_mempool.h>
29 #include <rte_prefetch.h>
33 #include "mlx4_rxtx.h"
34 #include "mlx4_utils.h"
37 * Pointer-value pair structure used in tx_post_send for saving the first
38 * DWORD (32 byte) of a TXBB.
41 volatile struct mlx4_wqe_data_seg *dseg;
45 /** A table to translate Rx completion flags to packet type. */
46 uint32_t mlx4_ptype_table[0x100] __rte_cache_aligned = {
48 * The index to the array should have:
49 * bit[7] - MLX4_CQE_L2_TUNNEL
50 * bit[6] - MLX4_CQE_L2_TUNNEL_IPV4
51 * bit[5] - MLX4_CQE_STATUS_UDP
52 * bit[4] - MLX4_CQE_STATUS_TCP
53 * bit[3] - MLX4_CQE_STATUS_IPV4OPT
54 * bit[2] - MLX4_CQE_STATUS_IPV6
55 * bit[1] - MLX4_CQE_STATUS_IPF
56 * bit[0] - MLX4_CQE_STATUS_IPV4
57 * giving a total of up to 256 entries.
60 [0x00] = RTE_PTYPE_L2_ETHER,
62 [0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
64 [0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
66 [0x03] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
68 [0x04] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
70 [0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
72 [0x08] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
74 [0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
76 [0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
78 [0x0b] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
81 [0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
83 [0x14] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
85 [0x16] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
87 [0x18] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
89 [0x19] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
92 [0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
94 [0x24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
96 [0x26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
98 [0x28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
100 [0x29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
102 /* Tunneled - L3 IPV6 */
103 [0x80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
104 [0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
105 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
106 RTE_PTYPE_INNER_L4_NONFRAG,
107 [0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
108 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
109 RTE_PTYPE_INNER_L4_FRAG,
110 [0x83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
111 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
112 RTE_PTYPE_INNER_L4_FRAG,
113 [0x84] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
114 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
115 RTE_PTYPE_INNER_L4_NONFRAG,
116 [0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
117 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
118 RTE_PTYPE_INNER_L4_FRAG,
119 [0x88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
120 RTE_PTYPE_INNER_L3_IPV4_EXT |
121 RTE_PTYPE_INNER_L4_NONFRAG,
122 [0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
123 RTE_PTYPE_INNER_L3_IPV4_EXT |
124 RTE_PTYPE_INNER_L4_NONFRAG,
125 [0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
126 RTE_PTYPE_INNER_L3_IPV4_EXT |
127 RTE_PTYPE_INNER_L4_FRAG,
128 [0x8b] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
129 RTE_PTYPE_INNER_L3_IPV4_EXT |
130 RTE_PTYPE_INNER_L4_FRAG,
131 /* Tunneled - L3 IPV6, TCP */
132 [0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
133 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
134 RTE_PTYPE_INNER_L4_TCP,
135 [0x94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
136 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
137 RTE_PTYPE_INNER_L4_TCP,
138 [0x96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
139 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
140 RTE_PTYPE_INNER_L4_FRAG,
141 [0x98] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
142 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_TCP,
143 [0x99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
144 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_TCP,
145 /* Tunneled - L3 IPV6, UDP */
146 [0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
147 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
148 RTE_PTYPE_INNER_L4_UDP,
149 [0xa4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
150 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
151 RTE_PTYPE_INNER_L4_UDP,
152 [0xa6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
153 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
154 RTE_PTYPE_INNER_L4_FRAG,
155 [0xa8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
156 RTE_PTYPE_INNER_L3_IPV4_EXT |
157 RTE_PTYPE_INNER_L4_UDP,
158 [0xa9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
159 RTE_PTYPE_INNER_L3_IPV4_EXT |
160 RTE_PTYPE_INNER_L4_UDP,
161 /* Tunneled - L3 IPV4 */
162 [0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
163 [0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
164 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
165 RTE_PTYPE_INNER_L4_NONFRAG,
166 [0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
167 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
168 RTE_PTYPE_INNER_L4_FRAG,
169 [0xc3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
170 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
171 RTE_PTYPE_INNER_L4_FRAG,
172 [0xc4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
173 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
174 RTE_PTYPE_INNER_L4_NONFRAG,
175 [0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
176 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
177 RTE_PTYPE_INNER_L4_FRAG,
178 [0xc8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
179 RTE_PTYPE_INNER_L3_IPV4_EXT |
180 RTE_PTYPE_INNER_L4_NONFRAG,
181 [0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
182 RTE_PTYPE_INNER_L3_IPV4_EXT |
183 RTE_PTYPE_INNER_L4_NONFRAG,
184 [0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
185 RTE_PTYPE_INNER_L3_IPV4_EXT |
186 RTE_PTYPE_INNER_L4_FRAG,
187 [0xcb] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
188 RTE_PTYPE_INNER_L3_IPV4_EXT |
189 RTE_PTYPE_INNER_L4_FRAG,
190 /* Tunneled - L3 IPV4, TCP */
191 [0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
192 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
193 RTE_PTYPE_INNER_L4_TCP,
194 [0xd4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
195 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
196 RTE_PTYPE_INNER_L4_TCP,
197 [0xd6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
198 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
199 RTE_PTYPE_INNER_L4_FRAG,
200 [0xd8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
201 RTE_PTYPE_INNER_L3_IPV4_EXT |
202 RTE_PTYPE_INNER_L4_TCP,
203 [0xd9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
204 RTE_PTYPE_INNER_L3_IPV4_EXT |
205 RTE_PTYPE_INNER_L4_TCP,
206 /* Tunneled - L3 IPV4, UDP */
207 [0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
208 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
209 RTE_PTYPE_INNER_L4_UDP,
210 [0xe4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
211 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
212 RTE_PTYPE_INNER_L4_UDP,
213 [0xe6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
214 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
215 RTE_PTYPE_INNER_L4_FRAG,
216 [0xe8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
217 RTE_PTYPE_INNER_L3_IPV4_EXT |
218 RTE_PTYPE_INNER_L4_UDP,
219 [0xe9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
220 RTE_PTYPE_INNER_L3_IPV4_EXT |
221 RTE_PTYPE_INNER_L4_UDP,
225 * Stamp TXBB burst so it won't be reused by the HW.
227 * Routine is used when freeing WQE used by the chip or when failing
228 * building an WQ entry has failed leaving partial information on the queue.
231 * Pointer to the SQ structure.
233 * Pointer to the first TXBB to stamp.
235 * Pointer to the followed end TXBB to stamp.
238 * Stamping burst size in byte units.
241 mlx4_txq_stamp_freed_wqe(struct mlx4_sq *sq, volatile uint32_t *start,
242 volatile uint32_t *end)
244 uint32_t stamp = sq->stamp;
245 int32_t size = (intptr_t)end - (intptr_t)start;
247 assert(start != end);
248 /* Hold SQ ring wrap around. */
250 size = (int32_t)sq->size + size;
253 start += MLX4_SQ_STAMP_DWORDS;
254 } while (start != (volatile uint32_t *)sq->eob);
255 start = (volatile uint32_t *)sq->buf;
256 /* Flip invalid stamping ownership. */
257 stamp ^= RTE_BE32(1u << MLX4_SQ_OWNER_BIT);
264 start += MLX4_SQ_STAMP_DWORDS;
265 } while (start != end);
266 return (uint32_t)size;
270 * Manage Tx completions.
272 * When sending a burst, mlx4_tx_burst() posts several WRs.
273 * To improve performance, a completion event is only required once every
274 * MLX4_PMD_TX_PER_COMP_REQ sends. Doing so discards completion information
275 * for other WRs, but this information would not be used anyway.
278 * Pointer to Tx queue structure.
280 * Tx elements number mask.
282 * Pointer to the SQ structure.
285 mlx4_txq_complete(struct txq *txq, const unsigned int elts_m,
288 unsigned int elts_tail = txq->elts_tail;
289 struct mlx4_cq *cq = &txq->mcq;
290 volatile struct mlx4_cqe *cqe;
292 uint32_t cons_index = cq->cons_index;
293 volatile uint32_t *first_txbb;
296 * Traverse over all CQ entries reported and handle each WQ entry
300 cqe = (volatile struct mlx4_cqe *)mlx4_get_cqe(cq, cons_index);
301 if (unlikely(!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
302 !!(cons_index & cq->cqe_cnt)))
306 * Make sure we read the CQE after we read the ownership bit.
309 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
310 MLX4_CQE_OPCODE_ERROR)) {
311 volatile struct mlx4_err_cqe *cqe_err =
312 (volatile struct mlx4_err_cqe *)cqe;
313 ERROR("%p CQE error - vendor syndrome: 0x%x"
315 (void *)txq, cqe_err->vendor_err,
322 completed = (cons_index - cq->cons_index) * txq->elts_comp_cd_init;
323 if (unlikely(!completed))
325 /* First stamping address is the end of the last one. */
326 first_txbb = (&(*txq->elts)[elts_tail & elts_m])->eocb;
327 elts_tail += completed;
328 /* The new tail element holds the end address. */
329 sq->remain_size += mlx4_txq_stamp_freed_wqe(sq, first_txbb,
330 (&(*txq->elts)[elts_tail & elts_m])->eocb);
331 /* Update CQ consumer index. */
332 cq->cons_index = cons_index;
333 *cq->set_ci_db = rte_cpu_to_be_32(cons_index & MLX4_CQ_DB_CI_MASK);
334 txq->elts_tail = elts_tail;
338 * Write Tx data segment to the SQ.
341 * Pointer to data segment in SQ.
343 * Memory region lkey.
347 * Big endian bytes count of the data to send.
350 mlx4_fill_tx_data_seg(volatile struct mlx4_wqe_data_seg *dseg,
351 uint32_t lkey, uintptr_t addr, rte_be32_t byte_count)
353 dseg->addr = rte_cpu_to_be_64(addr);
355 #if RTE_CACHE_LINE_SIZE < 64
357 * Need a barrier here before writing the byte_count
358 * fields to make sure that all the data is visible
359 * before the byte_count field is set.
360 * Otherwise, if the segment begins a new cacheline,
361 * the HCA prefetcher could grab the 64-byte chunk and
362 * get a valid (!= 0xffffffff) byte count but stale
363 * data, and end up sending the wrong data.
366 #endif /* RTE_CACHE_LINE_SIZE */
367 dseg->byte_count = byte_count;
371 * Write data segments of multi-segment packet.
374 * Pointer to the first packet mbuf.
376 * Pointer to Tx queue structure.
378 * Pointer to the WQE control segment.
381 * Pointer to the next WQE control segment on success, NULL otherwise.
383 static volatile struct mlx4_wqe_ctrl_seg *
384 mlx4_tx_burst_segs(struct rte_mbuf *buf, struct txq *txq,
385 volatile struct mlx4_wqe_ctrl_seg *ctrl)
387 struct pv *pv = (struct pv *)txq->bounce_buf;
388 struct mlx4_sq *sq = &txq->msq;
389 struct rte_mbuf *sbuf = buf;
392 int nb_segs = buf->nb_segs;
394 volatile struct mlx4_wqe_data_seg *dseg =
395 (volatile struct mlx4_wqe_data_seg *)(ctrl + 1);
397 ctrl->fence_size = 1 + nb_segs;
398 wqe_size = RTE_ALIGN((uint32_t)(ctrl->fence_size << MLX4_SEG_SHIFT),
400 /* Validate WQE size and WQE space in the send queue. */
401 if (sq->remain_size < wqe_size ||
402 wqe_size > MLX4_MAX_WQE_SIZE)
405 * Fill the data segments with buffer information.
406 * First WQE TXBB head segment is always control segment,
407 * so jump to tail TXBB data segments code for the first
408 * WQE data segments filling.
412 /* Memory region key (big endian) for this memory pool. */
413 lkey = mlx4_tx_mb2mr(txq, sbuf);
414 if (unlikely(lkey == (uint32_t)-1)) {
415 DEBUG("%p: unable to get MP <-> MR association",
419 /* Handle WQE wraparound. */
421 (volatile struct mlx4_wqe_data_seg *)sq->eob)
422 dseg = (volatile struct mlx4_wqe_data_seg *)
424 dseg->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(sbuf, uintptr_t));
427 * This data segment starts at the beginning of a new
428 * TXBB, so we need to postpone its byte_count writing
431 pv[pv_counter].dseg = dseg;
433 * Zero length segment is treated as inline segment
436 pv[pv_counter++].val = rte_cpu_to_be_32(sbuf->data_len ?
437 sbuf->data_len : 0x80000000);
442 /* Jump to default if there are more than two segments remaining. */
445 lkey = mlx4_tx_mb2mr(txq, sbuf);
446 if (unlikely(lkey == (uint32_t)-1)) {
447 DEBUG("%p: unable to get MP <-> MR association",
451 mlx4_fill_tx_data_seg(dseg, lkey,
452 rte_pktmbuf_mtod(sbuf, uintptr_t),
453 rte_cpu_to_be_32(sbuf->data_len ?
461 lkey = mlx4_tx_mb2mr(txq, sbuf);
462 if (unlikely(lkey == (uint32_t)-1)) {
463 DEBUG("%p: unable to get MP <-> MR association",
467 mlx4_fill_tx_data_seg(dseg, lkey,
468 rte_pktmbuf_mtod(sbuf, uintptr_t),
469 rte_cpu_to_be_32(sbuf->data_len ?
477 lkey = mlx4_tx_mb2mr(txq, sbuf);
478 if (unlikely(lkey == (uint32_t)-1)) {
479 DEBUG("%p: unable to get MP <-> MR association",
483 mlx4_fill_tx_data_seg(dseg, lkey,
484 rte_pktmbuf_mtod(sbuf, uintptr_t),
485 rte_cpu_to_be_32(sbuf->data_len ?
498 /* Write the first DWORD of each TXBB save earlier. */
500 /* Need a barrier here before writing the byte_count. */
502 for (--pv_counter; pv_counter >= 0; pv_counter--)
503 pv[pv_counter].dseg->byte_count = pv[pv_counter].val;
505 sq->remain_size -= wqe_size;
506 /* Align next WQE address to the next TXBB. */
507 return (volatile struct mlx4_wqe_ctrl_seg *)
508 ((volatile uint8_t *)ctrl + wqe_size);
512 * DPDK callback for Tx.
515 * Generic pointer to Tx queue structure.
517 * Packets to transmit.
519 * Number of packets in array.
522 * Number of packets successfully transmitted (<= pkts_n).
525 mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
527 struct txq *txq = (struct txq *)dpdk_txq;
528 unsigned int elts_head = txq->elts_head;
529 const unsigned int elts_n = txq->elts_n;
530 const unsigned int elts_m = elts_n - 1;
531 unsigned int bytes_sent = 0;
533 unsigned int max = elts_head - txq->elts_tail;
534 struct mlx4_sq *sq = &txq->msq;
535 volatile struct mlx4_wqe_ctrl_seg *ctrl;
538 assert(txq->elts_comp_cd != 0);
539 if (likely(max >= txq->elts_comp_cd_init))
540 mlx4_txq_complete(txq, elts_m, sq);
543 assert(max <= elts_n);
544 /* Always leave one free entry in the ring. */
548 elt = &(*txq->elts)[elts_head & elts_m];
549 /* First Tx burst element saves the next WQE control segment. */
551 for (i = 0; (i != max); ++i) {
552 struct rte_mbuf *buf = pkts[i];
553 struct txq_elt *elt_next = &(*txq->elts)[++elts_head & elts_m];
554 uint32_t owner_opcode = sq->owner_opcode;
555 volatile struct mlx4_wqe_data_seg *dseg =
556 (volatile struct mlx4_wqe_data_seg *)(ctrl + 1);
557 volatile struct mlx4_wqe_ctrl_seg *ctrl_next;
564 /* Clean up old buffer. */
565 if (likely(elt->buf != NULL)) {
566 struct rte_mbuf *tmp = elt->buf;
570 memset(&elt->buf, 0x66, sizeof(struct rte_mbuf *));
572 /* Faster than rte_pktmbuf_free(). */
574 struct rte_mbuf *next = tmp->next;
576 rte_pktmbuf_free_seg(tmp);
578 } while (tmp != NULL);
580 RTE_MBUF_PREFETCH_TO_FREE(elt_next->buf);
581 if (buf->nb_segs == 1) {
582 /* Validate WQE space in the send queue. */
583 if (sq->remain_size < MLX4_TXBB_SIZE) {
587 lkey = mlx4_tx_mb2mr(txq, buf);
588 if (unlikely(lkey == (uint32_t)-1)) {
589 /* MR does not exist. */
590 DEBUG("%p: unable to get MP <-> MR association",
595 mlx4_fill_tx_data_seg(dseg++, lkey,
596 rte_pktmbuf_mtod(buf, uintptr_t),
597 rte_cpu_to_be_32(buf->data_len));
598 /* Set WQE size in 16-byte units. */
599 ctrl->fence_size = 0x2;
600 sq->remain_size -= MLX4_TXBB_SIZE;
601 /* Align next WQE address to the next TXBB. */
602 ctrl_next = ctrl + 0x4;
604 ctrl_next = mlx4_tx_burst_segs(buf, txq, ctrl);
610 /* Hold SQ ring wrap around. */
611 if ((volatile uint8_t *)ctrl_next >= sq->eob) {
612 ctrl_next = (volatile struct mlx4_wqe_ctrl_seg *)
613 ((volatile uint8_t *)ctrl_next - sq->size);
614 /* Flip HW valid ownership. */
615 sq->owner_opcode ^= 1u << MLX4_SQ_OWNER_BIT;
618 * For raw Ethernet, the SOLICIT flag is used to indicate
619 * that no ICRC should be calculated.
621 if (--txq->elts_comp_cd == 0) {
622 /* Save the completion burst end address. */
623 elt_next->eocb = (volatile uint32_t *)ctrl_next;
624 txq->elts_comp_cd = txq->elts_comp_cd_init;
625 srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT |
626 MLX4_WQE_CTRL_CQ_UPDATE);
628 srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT);
630 /* Enable HW checksum offload if requested */
633 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))) {
634 const uint64_t is_tunneled = (buf->ol_flags &
636 PKT_TX_TUNNEL_VXLAN));
638 if (is_tunneled && txq->csum_l2tun) {
639 owner_opcode |= MLX4_WQE_CTRL_IIP_HDR_CSUM |
640 MLX4_WQE_CTRL_IL4_HDR_CSUM;
641 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
643 RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM);
646 RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM |
647 MLX4_WQE_CTRL_TCP_UDP_CSUM);
652 * Copy destination MAC address to the WQE, this allows
653 * loopback in eSwitch, so that VFs and PF can
654 * communicate with each other.
656 srcrb.flags16[0] = *(rte_pktmbuf_mtod(buf, uint16_t *));
657 ctrl->imm = *(rte_pktmbuf_mtod_offset(buf, uint32_t *,
662 ctrl->srcrb_flags = srcrb.flags;
664 * Make sure descriptor is fully written before
665 * setting ownership bit (because HW can start
666 * executing as soon as we do).
669 ctrl->owner_opcode = rte_cpu_to_be_32(owner_opcode);
671 bytes_sent += buf->pkt_len;
675 /* Take a shortcut if nothing must be sent. */
676 if (unlikely(i == 0))
678 /* Save WQE address of the next Tx burst element. */
680 /* Increment send statistics counters. */
681 txq->stats.opackets += i;
682 txq->stats.obytes += bytes_sent;
683 /* Make sure that descriptors are written before doorbell record. */
685 /* Ring QP doorbell. */
686 rte_write32(txq->msq.doorbell_qpn, txq->msq.db);
692 * Translate Rx completion flags to packet type.
698 * Packet type for struct rte_mbuf.
700 static inline uint32_t
701 rxq_cq_to_pkt_type(volatile struct mlx4_cqe *cqe,
702 uint32_t l2tun_offload)
705 uint32_t pinfo = rte_be_to_cpu_32(cqe->vlan_my_qpn);
706 uint32_t status = rte_be_to_cpu_32(cqe->status);
709 * The index to the array should have:
710 * bit[7] - MLX4_CQE_L2_TUNNEL
711 * bit[6] - MLX4_CQE_L2_TUNNEL_IPV4
713 if (l2tun_offload && (pinfo & MLX4_CQE_L2_TUNNEL))
714 idx |= ((pinfo & MLX4_CQE_L2_TUNNEL) >> 20) |
715 ((pinfo & MLX4_CQE_L2_TUNNEL_IPV4) >> 19);
717 * The index to the array should have:
718 * bit[5] - MLX4_CQE_STATUS_UDP
719 * bit[4] - MLX4_CQE_STATUS_TCP
720 * bit[3] - MLX4_CQE_STATUS_IPV4OPT
721 * bit[2] - MLX4_CQE_STATUS_IPV6
722 * bit[1] - MLX4_CQE_STATUS_IPF
723 * bit[0] - MLX4_CQE_STATUS_IPV4
724 * giving a total of up to 256 entries.
726 idx |= ((status & MLX4_CQE_STATUS_PTYPE_MASK) >> 22);
727 if (status & MLX4_CQE_STATUS_IPV6)
728 idx |= ((status & MLX4_CQE_STATUS_IPV6F) >> 11);
729 return mlx4_ptype_table[idx];
733 * Translate Rx completion flags to offload flags.
736 * Rx completion flags returned by mlx4_cqe_flags().
738 * Whether Rx checksums are enabled.
740 * Whether Rx L2 tunnel checksums are enabled.
743 * Offload flags (ol_flags) in mbuf format.
745 static inline uint32_t
746 rxq_cq_to_ol_flags(uint32_t flags, int csum, int csum_l2tun)
748 uint32_t ol_flags = 0;
752 mlx4_transpose(flags,
753 MLX4_CQE_STATUS_IP_HDR_CSUM_OK,
754 PKT_RX_IP_CKSUM_GOOD) |
755 mlx4_transpose(flags,
756 MLX4_CQE_STATUS_TCP_UDP_CSUM_OK,
757 PKT_RX_L4_CKSUM_GOOD);
758 if ((flags & MLX4_CQE_L2_TUNNEL) && csum_l2tun)
760 mlx4_transpose(flags,
761 MLX4_CQE_L2_TUNNEL_IPOK,
762 PKT_RX_IP_CKSUM_GOOD) |
763 mlx4_transpose(flags,
764 MLX4_CQE_L2_TUNNEL_L4_CSUM,
765 PKT_RX_L4_CKSUM_GOOD);
770 * Extract checksum information from CQE flags.
773 * Pointer to CQE structure.
775 * Whether Rx checksums are enabled.
777 * Whether Rx L2 tunnel checksums are enabled.
780 * CQE checksum information.
782 static inline uint32_t
783 mlx4_cqe_flags(volatile struct mlx4_cqe *cqe, int csum, int csum_l2tun)
788 * The relevant bits are in different locations on their
789 * CQE fields therefore we can join them in one 32bit
793 flags = (rte_be_to_cpu_32(cqe->status) &
794 MLX4_CQE_STATUS_IPV4_CSUM_OK);
796 flags |= (rte_be_to_cpu_32(cqe->vlan_my_qpn) &
797 (MLX4_CQE_L2_TUNNEL |
798 MLX4_CQE_L2_TUNNEL_IPOK |
799 MLX4_CQE_L2_TUNNEL_L4_CSUM |
800 MLX4_CQE_L2_TUNNEL_IPV4));
805 * Poll one CQE from CQ.
808 * Pointer to the receive queue structure.
813 * Number of bytes of the CQE, 0 in case there is no completion.
816 mlx4_cq_poll_one(struct rxq *rxq, volatile struct mlx4_cqe **out)
819 volatile struct mlx4_cqe *cqe = NULL;
820 struct mlx4_cq *cq = &rxq->mcq;
822 cqe = (volatile struct mlx4_cqe *)mlx4_get_cqe(cq, cq->cons_index);
823 if (!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
824 !!(cq->cons_index & cq->cqe_cnt))
827 * Make sure we read CQ entry contents after we've checked the
831 assert(!(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK));
832 assert((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) !=
833 MLX4_CQE_OPCODE_ERROR);
834 ret = rte_be_to_cpu_32(cqe->byte_cnt);
842 * DPDK callback for Rx with scattered packets support.
845 * Generic pointer to Rx queue structure.
847 * Array to store received packets.
849 * Maximum number of packets in array.
852 * Number of packets successfully received (<= pkts_n).
855 mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
857 struct rxq *rxq = dpdk_rxq;
858 const uint32_t wr_cnt = (1 << rxq->elts_n) - 1;
859 const uint16_t sges_n = rxq->sges_n;
860 struct rte_mbuf *pkt = NULL;
861 struct rte_mbuf *seg = NULL;
863 uint32_t rq_ci = rxq->rq_ci << sges_n;
867 volatile struct mlx4_cqe *cqe;
868 uint32_t idx = rq_ci & wr_cnt;
869 struct rte_mbuf *rep = (*rxq->elts)[idx];
870 volatile struct mlx4_wqe_data_seg *scat = &(*rxq->wqes)[idx];
872 /* Update the 'next' pointer of the previous segment. */
878 rep = rte_mbuf_raw_alloc(rxq->mp);
879 if (unlikely(rep == NULL)) {
880 ++rxq->stats.rx_nombuf;
883 * No buffers before we even started,
889 assert(pkt != (*rxq->elts)[idx]);
893 rte_mbuf_raw_free(pkt);
899 /* Looking for the new packet. */
900 len = mlx4_cq_poll_one(rxq, &cqe);
902 rte_mbuf_raw_free(rep);
905 if (unlikely(len < 0)) {
906 /* Rx error, packet is likely too large. */
907 rte_mbuf_raw_free(rep);
908 ++rxq->stats.idropped;
912 assert(len >= (rxq->crc_present << 2));
913 /* Update packet information. */
915 rxq_cq_to_pkt_type(cqe, rxq->l2tun_offload);
916 pkt->ol_flags = PKT_RX_RSS_HASH;
917 pkt->hash.rss = cqe->immed_rss_invalid;
918 if (rxq->crc_present)
919 len -= ETHER_CRC_LEN;
921 if (rxq->csum | rxq->csum_l2tun) {
928 rxq_cq_to_ol_flags(flags,
934 rep->port = rxq->port_id;
935 rep->data_len = seg->data_len;
936 rep->data_off = seg->data_off;
937 (*rxq->elts)[idx] = rep;
939 * Fill NIC descriptor with the new buffer. The lkey and size
940 * of the buffers are already known, only the buffer address
943 scat->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
944 /* If there's only one MR, no need to replace LKey in WQE. */
945 if (unlikely(mlx4_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
946 scat->lkey = mlx4_rx_mb2mr(rxq, rep);
947 if (len > seg->data_len) {
948 len -= seg->data_len;
953 /* The last segment. */
955 /* Increment bytes counter. */
956 rxq->stats.ibytes += pkt->pkt_len;
963 /* Align consumer index to the next stride. */
968 if (unlikely(i == 0 && (rq_ci >> sges_n) == rxq->rq_ci))
970 /* Update the consumer index. */
971 rxq->rq_ci = rq_ci >> sges_n;
973 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
974 *rxq->mcq.set_ci_db =
975 rte_cpu_to_be_32(rxq->mcq.cons_index & MLX4_CQ_DB_CI_MASK);
976 /* Increment packets counter. */
977 rxq->stats.ipackets += i;
982 * Dummy DPDK callback for Tx.
984 * This function is used to temporarily replace the real callback during
985 * unsafe control operations on the queue, or in case of error.
988 * Generic pointer to Tx queue structure.
990 * Packets to transmit.
992 * Number of packets in array.
995 * Number of packets successfully transmitted (<= pkts_n).
998 mlx4_tx_burst_removed(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1007 * Dummy DPDK callback for Rx.
1009 * This function is used to temporarily replace the real callback during
1010 * unsafe control operations on the queue, or in case of error.
1013 * Generic pointer to Rx queue structure.
1015 * Array to store received packets.
1017 * Maximum number of packets in array.
1020 * Number of packets successfully received (<= pkts_n).
1023 mlx4_rx_burst_removed(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)