4 * Copyright 2017 6WIND S.A.
5 * Copyright 2017 Mellanox
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of 6WIND S.A. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Data plane functions for mlx4 driver.
44 /* Verbs headers do not support -pedantic. */
46 #pragma GCC diagnostic ignored "-Wpedantic"
48 #include <infiniband/verbs.h>
50 #pragma GCC diagnostic error "-Wpedantic"
53 #include <rte_branch_prediction.h>
54 #include <rte_common.h>
57 #include <rte_mempool.h>
58 #include <rte_prefetch.h>
62 #include "mlx4_rxtx.h"
63 #include "mlx4_utils.h"
66 * Pointer-value pair structure used in tx_post_send for saving the first
67 * DWORD (32 byte) of a TXBB.
70 struct mlx4_wqe_data_seg *dseg;
75 * Stamp a WQE so it won't be reused by the HW.
77 * Routine is used when freeing WQE used by the chip or when failing
78 * building an WQ entry has failed leaving partial information on the queue.
81 * Pointer to the SQ structure.
83 * Index of the freed WQE.
85 * Number of blocks to stamp.
86 * If < 0 the routine will use the size written in the WQ entry.
88 * The value of the WQE owner bit to use in the stamp.
91 * The number of Tx basic blocs (TXBB) the WQE contained.
94 mlx4_txq_stamp_freed_wqe(struct mlx4_sq *sq, uint16_t index, uint8_t owner)
96 uint32_t stamp = rte_cpu_to_be_32(MLX4_SQ_STAMP_VAL |
97 (!!owner << MLX4_SQ_STAMP_SHIFT));
98 uint8_t *wqe = mlx4_get_send_wqe(sq, (index & sq->txbb_cnt_mask));
99 uint32_t *ptr = (uint32_t *)wqe;
104 /* Extract the size from the control segment of the WQE. */
105 num_txbbs = MLX4_SIZE_TO_TXBBS((((struct mlx4_wqe_ctrl_seg *)
106 wqe)->fence_size & 0x3f) << 4);
107 txbbs_size = num_txbbs * MLX4_TXBB_SIZE;
108 /* Optimize the common case when there is no wrap-around. */
109 if (wqe + txbbs_size <= sq->eob) {
110 /* Stamp the freed descriptor. */
111 for (i = 0; i < txbbs_size; i += MLX4_SQ_STAMP_STRIDE) {
113 ptr += MLX4_SQ_STAMP_DWORDS;
116 /* Stamp the freed descriptor. */
117 for (i = 0; i < txbbs_size; i += MLX4_SQ_STAMP_STRIDE) {
119 ptr += MLX4_SQ_STAMP_DWORDS;
120 if ((uint8_t *)ptr >= sq->eob) {
121 ptr = (uint32_t *)sq->buf;
122 stamp ^= RTE_BE32(0x80000000);
130 * Manage Tx completions.
132 * When sending a burst, mlx4_tx_burst() posts several WRs.
133 * To improve performance, a completion event is only required once every
134 * MLX4_PMD_TX_PER_COMP_REQ sends. Doing so discards completion information
135 * for other WRs, but this information would not be used anyway.
138 * Pointer to Tx queue structure.
141 * 0 on success, -1 on failure.
144 mlx4_txq_complete(struct txq *txq)
146 unsigned int elts_comp = txq->elts_comp;
147 unsigned int elts_tail = txq->elts_tail;
148 const unsigned int elts_n = txq->elts_n;
149 struct mlx4_cq *cq = &txq->mcq;
150 struct mlx4_sq *sq = &txq->msq;
151 struct mlx4_cqe *cqe;
152 uint32_t cons_index = cq->cons_index;
154 uint16_t nr_txbbs = 0;
157 if (unlikely(elts_comp == 0))
160 * Traverse over all CQ entries reported and handle each WQ entry
164 cqe = (struct mlx4_cqe *)mlx4_get_cqe(cq, cons_index);
165 if (unlikely(!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
166 !!(cons_index & cq->cqe_cnt)))
169 * Make sure we read the CQE after we read the ownership bit.
173 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
174 MLX4_CQE_OPCODE_ERROR)) {
175 struct mlx4_err_cqe *cqe_err =
176 (struct mlx4_err_cqe *)cqe;
177 ERROR("%p CQE error - vendor syndrome: 0x%x"
179 (void *)txq, cqe_err->vendor_err,
183 /* Get WQE index reported in the CQE. */
185 rte_be_to_cpu_16(cqe->wqe_index) & sq->txbb_cnt_mask;
187 /* Free next descriptor. */
189 mlx4_txq_stamp_freed_wqe(sq,
190 (sq->tail + nr_txbbs) & sq->txbb_cnt_mask,
191 !!((sq->tail + nr_txbbs) & sq->txbb_cnt));
193 } while (((sq->tail + nr_txbbs) & sq->txbb_cnt_mask) !=
197 if (unlikely(pkts == 0))
201 * To prevent CQ overflow we first update CQ consumer and only then
204 cq->cons_index = cons_index;
205 *cq->set_ci_db = rte_cpu_to_be_32(cq->cons_index & MLX4_CQ_DB_CI_MASK);
207 sq->tail = sq->tail + nr_txbbs;
208 /* Update the list of packets posted for transmission. */
210 assert(elts_comp <= txq->elts_comp);
212 * Assume completion status is successful as nothing can be done about
216 if (elts_tail >= elts_n)
218 txq->elts_tail = elts_tail;
219 txq->elts_comp = elts_comp;
224 * Get memory pool (MP) from mbuf. If mbuf is indirect, the pool from which
225 * the cloned mbuf is allocated is returned instead.
231 * Memory pool where data is located for given mbuf.
233 static struct rte_mempool *
234 mlx4_txq_mb2mp(struct rte_mbuf *buf)
236 if (unlikely(RTE_MBUF_INDIRECT(buf)))
237 return rte_mbuf_from_indirect(buf)->pool;
242 * Get memory region (MR) <-> memory pool (MP) association from txq->mp2mr[].
243 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
244 * remove an entry first.
247 * Pointer to Tx queue structure.
249 * Memory pool for which a memory region lkey must be returned.
252 * mr->lkey on success, (uint32_t)-1 on failure.
255 mlx4_txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
260 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
261 if (unlikely(txq->mp2mr[i].mp == NULL)) {
262 /* Unknown MP, add a new MR for it. */
265 if (txq->mp2mr[i].mp == mp) {
266 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
267 assert(txq->mp2mr[i].mr->lkey == txq->mp2mr[i].lkey);
268 return txq->mp2mr[i].lkey;
271 /* Add a new entry, register MR first. */
272 DEBUG("%p: discovered new memory pool \"%s\" (%p)",
273 (void *)txq, mp->name, (void *)mp);
274 mr = mlx4_mp2mr(txq->priv->pd, mp);
275 if (unlikely(mr == NULL)) {
276 DEBUG("%p: unable to configure MR, ibv_reg_mr() failed.",
280 if (unlikely(i == RTE_DIM(txq->mp2mr))) {
281 /* Table is full, remove oldest entry. */
282 DEBUG("%p: MR <-> MP table full, dropping oldest entry.",
285 claim_zero(ibv_dereg_mr(txq->mp2mr[0].mr));
286 memmove(&txq->mp2mr[0], &txq->mp2mr[1],
287 (sizeof(txq->mp2mr) - sizeof(txq->mp2mr[0])));
289 /* Store the new entry. */
290 txq->mp2mr[i].mp = mp;
291 txq->mp2mr[i].mr = mr;
292 txq->mp2mr[i].lkey = mr->lkey;
293 DEBUG("%p: new MR lkey for MP \"%s\" (%p): 0x%08" PRIu32,
294 (void *)txq, mp->name, (void *)mp, txq->mp2mr[i].lkey);
295 return txq->mp2mr[i].lkey;
299 * Posts a single work request to a send queue.
304 * Packet to transmit.
307 * 0 on success, negative errno value otherwise.
310 mlx4_post_send(struct txq *txq, struct rte_mbuf *pkt)
312 struct mlx4_wqe_ctrl_seg *ctrl;
313 struct mlx4_wqe_data_seg *dseg;
314 struct mlx4_sq *sq = &txq->msq;
315 struct rte_mbuf *buf;
320 uint32_t head_idx = sq->head & sq->txbb_cnt_mask;
323 uint32_t owner_opcode = MLX4_OPCODE_SEND;
327 struct pv *pv = (struct pv *)txq->bounce_buf;
330 /* Calculate the needed work queue entry size for this packet. */
331 wqe_real_size = sizeof(struct mlx4_wqe_ctrl_seg) +
332 pkt->nb_segs * sizeof(struct mlx4_wqe_data_seg);
333 nr_txbbs = MLX4_SIZE_TO_TXBBS(wqe_real_size);
335 * Check that there is room for this WQE in the send queue and that
336 * the WQE size is legal.
338 if (((sq->head - sq->tail) + nr_txbbs +
339 sq->headroom_txbbs) >= sq->txbb_cnt ||
340 nr_txbbs > MLX4_MAX_WQE_TXBBS) {
343 /* Get the control and data entries of the WQE. */
344 ctrl = (struct mlx4_wqe_ctrl_seg *)mlx4_get_send_wqe(sq, head_idx);
345 dseg = (struct mlx4_wqe_data_seg *)((uintptr_t)ctrl +
346 sizeof(struct mlx4_wqe_ctrl_seg));
347 /* Fill the data segments with buffer information. */
348 for (buf = pkt; buf != NULL; buf = buf->next, dseg++) {
349 addr = rte_pktmbuf_mtod(buf, uintptr_t);
350 rte_prefetch0((volatile void *)addr);
351 /* Handle WQE wraparound. */
352 if (unlikely(dseg >= (struct mlx4_wqe_data_seg *)sq->eob))
353 dseg = (struct mlx4_wqe_data_seg *)sq->buf;
354 dseg->addr = rte_cpu_to_be_64(addr);
355 /* Memory region key for this memory pool. */
356 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(buf));
358 if (unlikely(lkey == (uint32_t)-1)) {
359 /* MR does not exist. */
360 DEBUG("%p: unable to get MP <-> MR association",
363 * Restamp entry in case of failure.
364 * Make sure that size is written correctly
365 * Note that we give ownership to the SW, not the HW.
367 ctrl->fence_size = (wqe_real_size >> 4) & 0x3f;
368 mlx4_txq_stamp_freed_wqe(sq, head_idx,
369 (sq->head & sq->txbb_cnt) ? 0 : 1);
373 dseg->lkey = rte_cpu_to_be_32(lkey);
374 if (likely(buf->data_len)) {
375 byte_count = rte_cpu_to_be_32(buf->data_len);
378 * Zero length segment is treated as inline segment
381 byte_count = RTE_BE32(0x80000000);
384 * If the data segment is not at the beginning of a
385 * Tx basic block (TXBB) then write the byte count,
386 * else postpone the writing to just before updating the
389 if ((uintptr_t)dseg & (uintptr_t)(MLX4_TXBB_SIZE - 1)) {
391 * Need a barrier here before writing the byte_count
392 * fields to make sure that all the data is visible
393 * before the byte_count field is set.
394 * Otherwise, if the segment begins a new cacheline,
395 * the HCA prefetcher could grab the 64-byte chunk and
396 * get a valid (!= 0xffffffff) byte count but stale
397 * data, and end up sending the wrong data.
400 dseg->byte_count = byte_count;
403 * This data segment starts at the beginning of a new
404 * TXBB, so we need to postpone its byte_count writing
407 pv[pv_counter].dseg = dseg;
408 pv[pv_counter++].val = byte_count;
411 /* Write the first DWORD of each TXBB save earlier. */
413 /* Need a barrier here before writing the byte_count. */
415 for (--pv_counter; pv_counter >= 0; pv_counter--)
416 pv[pv_counter].dseg->byte_count = pv[pv_counter].val;
418 /* Fill the control parameters for this packet. */
419 ctrl->fence_size = (wqe_real_size >> 4) & 0x3f;
421 * For raw Ethernet, the SOLICIT flag is used to indicate that no ICRC
422 * should be calculated.
424 txq->elts_comp_cd -= nr_txbbs;
425 if (unlikely(txq->elts_comp_cd <= 0)) {
426 txq->elts_comp_cd = txq->elts_comp_cd_init;
427 srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT |
428 MLX4_WQE_CTRL_CQ_UPDATE);
430 srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT);
432 /* Enable HW checksum offload if requested */
435 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))) {
436 const uint64_t is_tunneled = (pkt->ol_flags &
438 PKT_TX_TUNNEL_VXLAN));
440 if (is_tunneled && txq->csum_l2tun) {
441 owner_opcode |= MLX4_WQE_CTRL_IIP_HDR_CSUM |
442 MLX4_WQE_CTRL_IL4_HDR_CSUM;
443 if (pkt->ol_flags & PKT_TX_OUTER_IP_CKSUM)
445 RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM);
447 srcrb.flags |= RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM |
448 MLX4_WQE_CTRL_TCP_UDP_CSUM);
453 * Copy destination MAC address to the WQE, this allows
454 * loopback in eSwitch, so that VFs and PF can communicate
457 srcrb.flags16[0] = *(rte_pktmbuf_mtod(pkt, uint16_t *));
458 ctrl->imm = *(rte_pktmbuf_mtod_offset(pkt, uint32_t *,
463 ctrl->srcrb_flags = srcrb.flags;
465 * Make sure descriptor is fully written before
466 * setting ownership bit (because HW can start
467 * executing as soon as we do).
470 ctrl->owner_opcode = rte_cpu_to_be_32(owner_opcode |
471 ((sq->head & sq->txbb_cnt) ?
472 MLX4_BIT_WQE_OWN : 0));
473 sq->head += nr_txbbs;
478 * DPDK callback for Tx.
481 * Generic pointer to Tx queue structure.
483 * Packets to transmit.
485 * Number of packets in array.
488 * Number of packets successfully transmitted (<= pkts_n).
491 mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
493 struct txq *txq = (struct txq *)dpdk_txq;
494 unsigned int elts_head = txq->elts_head;
495 const unsigned int elts_n = txq->elts_n;
496 unsigned int elts_comp = 0;
497 unsigned int bytes_sent = 0;
502 assert(txq->elts_comp_cd != 0);
503 mlx4_txq_complete(txq);
504 max = (elts_n - (elts_head - txq->elts_tail));
508 assert(max <= elts_n);
509 /* Always leave one free entry in the ring. */
515 for (i = 0; (i != max); ++i) {
516 struct rte_mbuf *buf = pkts[i];
517 unsigned int elts_head_next =
518 (((elts_head + 1) == elts_n) ? 0 : elts_head + 1);
519 struct txq_elt *elt_next = &(*txq->elts)[elts_head_next];
520 struct txq_elt *elt = &(*txq->elts)[elts_head];
522 /* Clean up old buffer. */
523 if (likely(elt->buf != NULL)) {
524 struct rte_mbuf *tmp = elt->buf;
528 memset(elt, 0x66, sizeof(*elt));
530 /* Faster than rte_pktmbuf_free(). */
532 struct rte_mbuf *next = tmp->next;
534 rte_pktmbuf_free_seg(tmp);
536 } while (tmp != NULL);
538 RTE_MBUF_PREFETCH_TO_FREE(elt_next->buf);
539 /* Post the packet for sending. */
540 err = mlx4_post_send(txq, buf);
546 bytes_sent += buf->pkt_len;
548 elts_head = elts_head_next;
551 /* Take a shortcut if nothing must be sent. */
552 if (unlikely(i == 0))
554 /* Increment send statistics counters. */
555 txq->stats.opackets += i;
556 txq->stats.obytes += bytes_sent;
557 /* Make sure that descriptors are written before doorbell record. */
559 /* Ring QP doorbell. */
560 rte_write32(txq->msq.doorbell_qpn, txq->msq.db);
561 txq->elts_head = elts_head;
562 txq->elts_comp += elts_comp;
567 * Translate Rx completion flags to packet type.
570 * Rx completion flags returned by mlx4_cqe_flags().
573 * Packet type in mbuf format.
575 static inline uint32_t
576 rxq_cq_to_pkt_type(uint32_t flags)
580 if (flags & MLX4_CQE_L2_TUNNEL)
582 mlx4_transpose(flags,
583 MLX4_CQE_L2_TUNNEL_IPV4,
584 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN) |
585 mlx4_transpose(flags,
586 MLX4_CQE_STATUS_IPV4_PKT,
587 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN);
589 pkt_type = mlx4_transpose(flags,
590 MLX4_CQE_STATUS_IPV4_PKT,
591 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
596 * Translate Rx completion flags to offload flags.
599 * Rx completion flags returned by mlx4_cqe_flags().
601 * Whether Rx checksums are enabled.
603 * Whether Rx L2 tunnel checksums are enabled.
606 * Offload flags (ol_flags) in mbuf format.
608 static inline uint32_t
609 rxq_cq_to_ol_flags(uint32_t flags, int csum, int csum_l2tun)
611 uint32_t ol_flags = 0;
615 mlx4_transpose(flags,
616 MLX4_CQE_STATUS_IP_HDR_CSUM_OK,
617 PKT_RX_IP_CKSUM_GOOD) |
618 mlx4_transpose(flags,
619 MLX4_CQE_STATUS_TCP_UDP_CSUM_OK,
620 PKT_RX_L4_CKSUM_GOOD);
621 if ((flags & MLX4_CQE_L2_TUNNEL) && csum_l2tun)
623 mlx4_transpose(flags,
624 MLX4_CQE_L2_TUNNEL_IPOK,
625 PKT_RX_IP_CKSUM_GOOD) |
626 mlx4_transpose(flags,
627 MLX4_CQE_L2_TUNNEL_L4_CSUM,
628 PKT_RX_L4_CKSUM_GOOD);
633 * Extract checksum information from CQE flags.
636 * Pointer to CQE structure.
638 * Whether Rx checksums are enabled.
640 * Whether Rx L2 tunnel checksums are enabled.
643 * CQE checksum information.
645 static inline uint32_t
646 mlx4_cqe_flags(struct mlx4_cqe *cqe, int csum, int csum_l2tun)
651 * The relevant bits are in different locations on their
652 * CQE fields therefore we can join them in one 32bit
656 flags = (rte_be_to_cpu_32(cqe->status) &
657 MLX4_CQE_STATUS_IPV4_CSUM_OK);
659 flags |= (rte_be_to_cpu_32(cqe->vlan_my_qpn) &
660 (MLX4_CQE_L2_TUNNEL |
661 MLX4_CQE_L2_TUNNEL_IPOK |
662 MLX4_CQE_L2_TUNNEL_L4_CSUM |
663 MLX4_CQE_L2_TUNNEL_IPV4));
668 * Poll one CQE from CQ.
671 * Pointer to the receive queue structure.
676 * Number of bytes of the CQE, 0 in case there is no completion.
679 mlx4_cq_poll_one(struct rxq *rxq, struct mlx4_cqe **out)
682 struct mlx4_cqe *cqe = NULL;
683 struct mlx4_cq *cq = &rxq->mcq;
685 cqe = (struct mlx4_cqe *)mlx4_get_cqe(cq, cq->cons_index);
686 if (!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
687 !!(cq->cons_index & cq->cqe_cnt))
690 * Make sure we read CQ entry contents after we've checked the
694 assert(!(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK));
695 assert((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) !=
696 MLX4_CQE_OPCODE_ERROR);
697 ret = rte_be_to_cpu_32(cqe->byte_cnt);
705 * DPDK callback for Rx with scattered packets support.
708 * Generic pointer to Rx queue structure.
710 * Array to store received packets.
712 * Maximum number of packets in array.
715 * Number of packets successfully received (<= pkts_n).
718 mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
720 struct rxq *rxq = dpdk_rxq;
721 const uint32_t wr_cnt = (1 << rxq->elts_n) - 1;
722 const uint16_t sges_n = rxq->sges_n;
723 struct rte_mbuf *pkt = NULL;
724 struct rte_mbuf *seg = NULL;
726 uint32_t rq_ci = rxq->rq_ci << sges_n;
730 struct mlx4_cqe *cqe;
731 uint32_t idx = rq_ci & wr_cnt;
732 struct rte_mbuf *rep = (*rxq->elts)[idx];
733 volatile struct mlx4_wqe_data_seg *scat = &(*rxq->wqes)[idx];
735 /* Update the 'next' pointer of the previous segment. */
741 rep = rte_mbuf_raw_alloc(rxq->mp);
742 if (unlikely(rep == NULL)) {
743 ++rxq->stats.rx_nombuf;
746 * No buffers before we even started,
752 assert(pkt != (*rxq->elts)[idx]);
756 rte_mbuf_raw_free(pkt);
762 /* Looking for the new packet. */
763 len = mlx4_cq_poll_one(rxq, &cqe);
765 rte_mbuf_raw_free(rep);
768 if (unlikely(len < 0)) {
769 /* Rx error, packet is likely too large. */
770 rte_mbuf_raw_free(rep);
771 ++rxq->stats.idropped;
775 if (rxq->csum | rxq->csum_l2tun) {
782 rxq_cq_to_ol_flags(flags,
785 pkt->packet_type = rxq_cq_to_pkt_type(flags);
787 pkt->packet_type = 0;
793 rep->port = rxq->port_id;
794 rep->data_len = seg->data_len;
795 rep->data_off = seg->data_off;
796 (*rxq->elts)[idx] = rep;
798 * Fill NIC descriptor with the new buffer. The lkey and size
799 * of the buffers are already known, only the buffer address
802 scat->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
803 if (len > seg->data_len) {
804 len -= seg->data_len;
809 /* The last segment. */
811 /* Increment bytes counter. */
812 rxq->stats.ibytes += pkt->pkt_len;
819 /* Align consumer index to the next stride. */
824 if (unlikely(i == 0 && (rq_ci >> sges_n) == rxq->rq_ci))
826 /* Update the consumer index. */
827 rxq->rq_ci = rq_ci >> sges_n;
829 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
830 *rxq->mcq.set_ci_db =
831 rte_cpu_to_be_32(rxq->mcq.cons_index & MLX4_CQ_DB_CI_MASK);
832 /* Increment packets counter. */
833 rxq->stats.ipackets += i;
838 * Dummy DPDK callback for Tx.
840 * This function is used to temporarily replace the real callback during
841 * unsafe control operations on the queue, or in case of error.
844 * Generic pointer to Tx queue structure.
846 * Packets to transmit.
848 * Number of packets in array.
851 * Number of packets successfully transmitted (<= pkts_n).
854 mlx4_tx_burst_removed(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
863 * Dummy DPDK callback for Rx.
865 * This function is used to temporarily replace the real callback during
866 * unsafe control operations on the queue, or in case of error.
869 * Generic pointer to Rx queue structure.
871 * Array to store received packets.
873 * Maximum number of packets in array.
876 * Number of packets successfully received (<= pkts_n).
879 mlx4_rx_burst_removed(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)