drivers/net/mlx4/mlx4_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2017 6WIND S.A.
   5  *   Copyright 2017 Mellanox
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /**
  35  * @file
  36  * Data plane functions for mlx4 driver.
  37  */
  38
  39 #include <assert.h>
  40 #include <stdint.h>
  41 #include <string.h>
  42
  43 /* Verbs headers do not support -pedantic. */
  44 #ifdef PEDANTIC
  45 #pragma GCC diagnostic ignored "-Wpedantic"
  46 #endif
  47 #include <infiniband/verbs.h>
  48 #ifdef PEDANTIC
  49 #pragma GCC diagnostic error "-Wpedantic"
  50 #endif
  51
  52 #include <rte_branch_prediction.h>
  53 #include <rte_common.h>
  54 #include <rte_io.h>
  55 #include <rte_mbuf.h>
  56 #include <rte_mempool.h>
  57 #include <rte_prefetch.h>
  58
  59 #include "mlx4.h"
  60 #include "mlx4_prm.h"
  61 #include "mlx4_rxtx.h"
  62 #include "mlx4_utils.h"
  63
  64 #define WQE_ONE_DATA_SEG_SIZE \
  65         (sizeof(struct mlx4_wqe_ctrl_seg) + sizeof(struct mlx4_wqe_data_seg))
  66
  67 /**
  68  * Pointer-value pair structure used in tx_post_send for saving the first
  69  * DWORD (32 byte) of a TXBB.
  70  */
  71 struct pv {
  72         volatile struct mlx4_wqe_data_seg *dseg;
  73         uint32_t val;
  74 };
  75
  76 /** A table to translate Rx completion flags to packet type. */
  77 uint32_t mlx4_ptype_table[0x100] __rte_cache_aligned = {
  78         /*
  79          * The index to the array should have:
  80          *  bit[7] - MLX4_CQE_L2_TUNNEL
  81          *  bit[6] - MLX4_CQE_L2_TUNNEL_IPV4
  82          *  bit[5] - MLX4_CQE_STATUS_UDP
  83          *  bit[4] - MLX4_CQE_STATUS_TCP
  84          *  bit[3] - MLX4_CQE_STATUS_IPV4OPT
  85          *  bit[2] - MLX4_CQE_STATUS_IPV6
  86          *  bit[1] - MLX4_CQE_STATUS_IPV4F
  87          *  bit[0] - MLX4_CQE_STATUS_IPV4
  88          * giving a total of up to 256 entries.
  89          */
  90         [0x00] = RTE_PTYPE_L2_ETHER,
  91         [0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
  92         [0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  93                      RTE_PTYPE_L4_FRAG,
  94         [0x03] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  95                      RTE_PTYPE_L4_FRAG,
  96         [0x04] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
  97         [0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT,
  98         [0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
  99                      RTE_PTYPE_L4_FRAG,
 100         [0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 101                      RTE_PTYPE_L4_TCP,
 102         [0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 103                      RTE_PTYPE_L4_TCP,
 104         [0x14] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 105                      RTE_PTYPE_L4_TCP,
 106         [0x18] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 107                      RTE_PTYPE_L4_TCP,
 108         [0x19] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 109                      RTE_PTYPE_L4_TCP,
 110         [0x1a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 111                      RTE_PTYPE_L4_TCP,
 112         [0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 113                      RTE_PTYPE_L4_UDP,
 114         [0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 115                      RTE_PTYPE_L4_UDP,
 116         [0x24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 117                      RTE_PTYPE_L4_UDP,
 118         [0x28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 119                      RTE_PTYPE_L4_UDP,
 120         [0x29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 121                      RTE_PTYPE_L4_UDP,
 122         [0x2a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT |
 123                      RTE_PTYPE_L4_UDP,
 124         /* Tunneled - L3 IPV6 */
 125         [0x80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 126         [0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 127                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
 128         [0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 129                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 130                      RTE_PTYPE_INNER_L4_FRAG,
 131         [0x83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 132                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 133                      RTE_PTYPE_INNER_L4_FRAG,
 134         [0x84] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 135                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
 136         [0x88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 137                      RTE_PTYPE_INNER_L3_IPV4_EXT,
 138         [0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 139                      RTE_PTYPE_INNER_L3_IPV4_EXT,
 140         [0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 141                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG,
 142         /* Tunneled - L3 IPV6, TCP */
 143         [0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 144                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 145                      RTE_PTYPE_INNER_L4_TCP,
 146         [0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 147                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 148                      RTE_PTYPE_INNER_L4_FRAG |
 149                      RTE_PTYPE_INNER_L4_TCP,
 150         [0x93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 151                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 152                      RTE_PTYPE_INNER_L4_FRAG |
 153                      RTE_PTYPE_INNER_L4_TCP,
 154         [0x94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 155                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 156                      RTE_PTYPE_INNER_L4_TCP,
 157         [0x98] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 158                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 159                      RTE_PTYPE_INNER_L4_TCP,
 160         [0x99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 161                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 162                      RTE_PTYPE_INNER_L4_TCP,
 163         [0x9a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 164                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
 165                      RTE_PTYPE_INNER_L4_TCP,
 166         /* Tunneled - L3 IPV6, UDP */
 167         [0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 168                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 169                      RTE_PTYPE_INNER_L4_UDP,
 170         [0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 171                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 172                      RTE_PTYPE_INNER_L4_FRAG |
 173                      RTE_PTYPE_INNER_L4_UDP,
 174         [0xa3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 175                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 176                      RTE_PTYPE_INNER_L4_FRAG |
 177                      RTE_PTYPE_INNER_L4_UDP,
 178         [0xa4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 179                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 180                      RTE_PTYPE_INNER_L4_UDP,
 181         [0xa8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 182                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 183                      RTE_PTYPE_INNER_L4_UDP,
 184         [0xa9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 185                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 186                      RTE_PTYPE_INNER_L4_UDP,
 187         [0xaa] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 188                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
 189                      RTE_PTYPE_INNER_L4_UDP,
 190         /* Tunneled - L3 IPV4 */
 191         [0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 192         [0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 193                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
 194         [0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 195                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 196                      RTE_PTYPE_INNER_L4_FRAG,
 197         [0xc3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 198                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 199                      RTE_PTYPE_INNER_L4_FRAG,
 200         [0xc4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 201                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
 202         [0xc8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 203                      RTE_PTYPE_INNER_L3_IPV4_EXT,
 204         [0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 205                      RTE_PTYPE_INNER_L3_IPV4_EXT,
 206         [0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 207                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 208                      RTE_PTYPE_INNER_L4_FRAG,
 209         /* Tunneled - L3 IPV4, TCP */
 210         [0xd0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 211                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 212                      RTE_PTYPE_INNER_L4_TCP,
 213         [0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 214                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 215                      RTE_PTYPE_INNER_L4_TCP,
 216         [0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 217                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 218                      RTE_PTYPE_INNER_L4_FRAG |
 219                      RTE_PTYPE_INNER_L4_TCP,
 220         [0xd3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 221                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 222                      RTE_PTYPE_INNER_L4_FRAG |
 223                      RTE_PTYPE_INNER_L4_TCP,
 224         [0xd4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 225                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 226                      RTE_PTYPE_INNER_L4_TCP,
 227         [0xd8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 228                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 229                      RTE_PTYPE_INNER_L4_TCP,
 230         [0xd9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 231                      RTE_PTYPE_INNER_L3_IPV4_EXT |
 232                      RTE_PTYPE_INNER_L4_TCP,
 233         [0xda] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 234                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
 235                      RTE_PTYPE_INNER_L4_TCP,
 236         /* Tunneled - L3 IPV4, UDP */
 237         [0xe0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 238                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 239                      RTE_PTYPE_INNER_L4_UDP,
 240         [0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 241                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 242                      RTE_PTYPE_INNER_L4_UDP,
 243         [0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 244                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 245                      RTE_PTYPE_INNER_L4_FRAG |
 246                      RTE_PTYPE_INNER_L4_UDP,
 247         [0xe3] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 248                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 249                      RTE_PTYPE_INNER_L4_FRAG |
 250                      RTE_PTYPE_INNER_L4_UDP,
 251         [0xe4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 252                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 253                      RTE_PTYPE_INNER_L4_UDP,
 254         [0xe8] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 255                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
 256         [0xe9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 257                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
 258         [0xea] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 259                      RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_FRAG |
 260                      RTE_PTYPE_INNER_L4_UDP,
 261 };
 262
 263 /**
 264  * Stamp a WQE so it won't be reused by the HW.
 265  *
 266  * Routine is used when freeing WQE used by the chip or when failing
 267  * building an WQ entry has failed leaving partial information on the queue.
 268  *
 269  * @param sq
 270  *   Pointer to the SQ structure.
 271  * @param index
 272  *   Index of the freed WQE.
 273  * @param num_txbbs
 274  *   Number of blocks to stamp.
 275  *   If < 0 the routine will use the size written in the WQ entry.
 276  * @param owner
 277  *   The value of the WQE owner bit to use in the stamp.
 278  *
 279  * @return
 280  *   The number of Tx basic blocs (TXBB) the WQE contained.
 281  */
 282 static int
 283 mlx4_txq_stamp_freed_wqe(struct mlx4_sq *sq, uint16_t index, uint8_t owner)
 284 {
 285         uint32_t stamp = rte_cpu_to_be_32(MLX4_SQ_STAMP_VAL |
 286                                           (!!owner << MLX4_SQ_STAMP_SHIFT));
 287         volatile uint8_t *wqe = mlx4_get_send_wqe(sq,
 288                                                 (index & sq->txbb_cnt_mask));
 289         volatile uint32_t *ptr = (volatile uint32_t *)wqe;
 290         int i;
 291         int txbbs_size;
 292         int num_txbbs;
 293
 294         /* Extract the size from the control segment of the WQE. */
 295         num_txbbs = MLX4_SIZE_TO_TXBBS((((volatile struct mlx4_wqe_ctrl_seg *)
 296                                          wqe)->fence_size & 0x3f) << 4);
 297         txbbs_size = num_txbbs * MLX4_TXBB_SIZE;
 298         /* Optimize the common case when there is no wrap-around. */
 299         if (wqe + txbbs_size <= sq->eob) {
 300                 /* Stamp the freed descriptor. */
 301                 for (i = 0; i < txbbs_size; i += MLX4_SQ_STAMP_STRIDE) {
 302                         *ptr = stamp;
 303                         ptr += MLX4_SQ_STAMP_DWORDS;
 304                 }
 305         } else {
 306                 /* Stamp the freed descriptor. */
 307                 for (i = 0; i < txbbs_size; i += MLX4_SQ_STAMP_STRIDE) {
 308                         *ptr = stamp;
 309                         ptr += MLX4_SQ_STAMP_DWORDS;
 310                         if ((volatile uint8_t *)ptr >= sq->eob) {
 311                                 ptr = (volatile uint32_t *)sq->buf;
 312                                 stamp ^= RTE_BE32(0x80000000);
 313                         }
 314                 }
 315         }
 316         return num_txbbs;
 317 }
 318
 319 /**
 320  * Manage Tx completions.
 321  *
 322  * When sending a burst, mlx4_tx_burst() posts several WRs.
 323  * To improve performance, a completion event is only required once every
 324  * MLX4_PMD_TX_PER_COMP_REQ sends. Doing so discards completion information
 325  * for other WRs, but this information would not be used anyway.
 326  *
 327  * @param txq
 328  *   Pointer to Tx queue structure.
 329  *
 330  * @return
 331  *   0 on success, -1 on failure.
 332  */
 333 static int
 334 mlx4_txq_complete(struct txq *txq, const unsigned int elts_n,
 335                                   struct mlx4_sq *sq)
 336 {
 337         unsigned int elts_comp = txq->elts_comp;
 338         unsigned int elts_tail = txq->elts_tail;
 339         unsigned int sq_tail = sq->tail;
 340         struct mlx4_cq *cq = &txq->mcq;
 341         volatile struct mlx4_cqe *cqe;
 342         uint32_t cons_index = cq->cons_index;
 343         uint16_t new_index;
 344         uint16_t nr_txbbs = 0;
 345         int pkts = 0;
 346
 347         /*
 348          * Traverse over all CQ entries reported and handle each WQ entry
 349          * reported by them.
 350          */
 351         do {
 352                 cqe = (volatile struct mlx4_cqe *)mlx4_get_cqe(cq, cons_index);
 353                 if (unlikely(!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
 354                     !!(cons_index & cq->cqe_cnt)))
 355                         break;
 356                 /*
 357                  * Make sure we read the CQE after we read the ownership bit.
 358                  */
 359                 rte_io_rmb();
 360 #ifndef NDEBUG
 361                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 362                              MLX4_CQE_OPCODE_ERROR)) {
 363                         volatile struct mlx4_err_cqe *cqe_err =
 364                                 (volatile struct mlx4_err_cqe *)cqe;
 365                         ERROR("%p CQE error - vendor syndrome: 0x%x"
 366                               " syndrome: 0x%x\n",
 367                               (void *)txq, cqe_err->vendor_err,
 368                               cqe_err->syndrome);
 369                 }
 370 #endif /* NDEBUG */
 371                 /* Get WQE index reported in the CQE. */
 372                 new_index =
 373                         rte_be_to_cpu_16(cqe->wqe_index) & sq->txbb_cnt_mask;
 374                 do {
 375                         /* Free next descriptor. */
 376                         sq_tail += nr_txbbs;
 377                         nr_txbbs =
 378                                 mlx4_txq_stamp_freed_wqe(sq,
 379                                      sq_tail & sq->txbb_cnt_mask,
 380                                      !!(sq_tail & sq->txbb_cnt));
 381                         pkts++;
 382                 } while ((sq_tail & sq->txbb_cnt_mask) != new_index);
 383                 cons_index++;
 384         } while (1);
 385         if (unlikely(pkts == 0))
 386                 return 0;
 387         /* Update CQ. */
 388         cq->cons_index = cons_index;
 389         *cq->set_ci_db = rte_cpu_to_be_32(cq->cons_index & MLX4_CQ_DB_CI_MASK);
 390         sq->tail = sq_tail + nr_txbbs;
 391         /* Update the list of packets posted for transmission. */
 392         elts_comp -= pkts;
 393         assert(elts_comp <= txq->elts_comp);
 394         /*
 395          * Assume completion status is successful as nothing can be done about
 396          * it anyway.
 397          */
 398         elts_tail += pkts;
 399         if (elts_tail >= elts_n)
 400                 elts_tail -= elts_n;
 401         txq->elts_tail = elts_tail;
 402         txq->elts_comp = elts_comp;
 403         return 0;
 404 }
 405
 406 /**
 407  * Get memory pool (MP) from mbuf. If mbuf is indirect, the pool from which
 408  * the cloned mbuf is allocated is returned instead.
 409  *
 410  * @param buf
 411  *   Pointer to mbuf.
 412  *
 413  * @return
 414  *   Memory pool where data is located for given mbuf.
 415  */
 416 static struct rte_mempool *
 417 mlx4_txq_mb2mp(struct rte_mbuf *buf)
 418 {
 419         if (unlikely(RTE_MBUF_INDIRECT(buf)))
 420                 return rte_mbuf_from_indirect(buf)->pool;
 421         return buf->pool;
 422 }
 423
 424 static int
 425 mlx4_tx_burst_segs(struct rte_mbuf *buf, struct txq *txq,
 426                    volatile struct mlx4_wqe_ctrl_seg **pctrl)
 427 {
 428         int wqe_real_size;
 429         int nr_txbbs;
 430         struct pv *pv = (struct pv *)txq->bounce_buf;
 431         struct mlx4_sq *sq = &txq->msq;
 432         uint32_t head_idx = sq->head & sq->txbb_cnt_mask;
 433         volatile struct mlx4_wqe_ctrl_seg *ctrl;
 434         volatile struct mlx4_wqe_data_seg *dseg;
 435         struct rte_mbuf *sbuf;
 436         uint32_t lkey;
 437         uintptr_t addr;
 438         uint32_t byte_count;
 439         int pv_counter = 0;
 440
 441         /* Calculate the needed work queue entry size for this packet. */
 442         wqe_real_size = sizeof(volatile struct mlx4_wqe_ctrl_seg) +
 443                 buf->nb_segs * sizeof(volatile struct mlx4_wqe_data_seg);
 444         nr_txbbs = MLX4_SIZE_TO_TXBBS(wqe_real_size);
 445         /*
 446          * Check that there is room for this WQE in the send queue and that
 447          * the WQE size is legal.
 448          */
 449         if (((sq->head - sq->tail) + nr_txbbs +
 450                                 sq->headroom_txbbs) >= sq->txbb_cnt ||
 451                         nr_txbbs > MLX4_MAX_WQE_TXBBS) {
 452                 return -1;
 453         }
 454         /* Get the control and data entries of the WQE. */
 455         ctrl = (volatile struct mlx4_wqe_ctrl_seg *)
 456                         mlx4_get_send_wqe(sq, head_idx);
 457         dseg = (volatile struct mlx4_wqe_data_seg *)
 458                         ((uintptr_t)ctrl + sizeof(struct mlx4_wqe_ctrl_seg));
 459         *pctrl = ctrl;
 460         /* Fill the data segments with buffer information. */
 461         for (sbuf = buf; sbuf != NULL; sbuf = sbuf->next, dseg++) {
 462                 addr = rte_pktmbuf_mtod(sbuf, uintptr_t);
 463                 rte_prefetch0((volatile void *)addr);
 464                 /* Memory region key (big endian) for this memory pool. */
 465                 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
 466                 dseg->lkey = rte_cpu_to_be_32(lkey);
 467                 /* Calculate the needed work queue entry size for this packet */
 468                 if (unlikely(lkey == rte_cpu_to_be_32((uint32_t)-1))) {
 469                         /* MR does not exist. */
 470                         DEBUG("%p: unable to get MP <-> MR association",
 471                               (void *)txq);
 472                         return -1;
 473                 }
 474                 if (likely(sbuf->data_len)) {
 475                         byte_count = rte_cpu_to_be_32(sbuf->data_len);
 476                 } else {
 477                         /*
 478                          * Zero length segment is treated as inline segment
 479                          * with zero data.
 480                          */
 481                         byte_count = RTE_BE32(0x80000000);
 482                 }
 483                 /*
 484                  * If the data segment is not at the beginning of a
 485                  * Tx basic block (TXBB) then write the byte count,
 486                  * else postpone the writing to just before updating the
 487                  * control segment.
 488                  */
 489                 if ((uintptr_t)dseg & (uintptr_t)(MLX4_TXBB_SIZE - 1)) {
 490                         dseg->addr = rte_cpu_to_be_64(addr);
 491                         dseg->lkey = rte_cpu_to_be_32(lkey);
 492 #if RTE_CACHE_LINE_SIZE < 64
 493                         /*
 494                          * Need a barrier here before writing the byte_count
 495                          * fields to make sure that all the data is visible
 496                          * before the byte_count field is set.
 497                          * Otherwise, if the segment begins a new cacheline,
 498                          * the HCA prefetcher could grab the 64-byte chunk and
 499                          * get a valid (!= 0xffffffff) byte count but stale
 500                          * data, and end up sending the wrong data.
 501                          */
 502                         rte_io_wmb();
 503 #endif /* RTE_CACHE_LINE_SIZE */
 504                         dseg->byte_count = byte_count;
 505                 } else {
 506                         /*
 507                          * This data segment starts at the beginning of a new
 508                          * TXBB, so we need to postpone its byte_count writing
 509                          * for later.
 510                          */
 511                         /* Handle WQE wraparound. */
 512                         if (dseg >=
 513                             (volatile struct mlx4_wqe_data_seg *)sq->eob)
 514                                 dseg = (volatile struct mlx4_wqe_data_seg *)
 515                                         sq->buf;
 516                         dseg->addr = rte_cpu_to_be_64(addr);
 517                         dseg->lkey = rte_cpu_to_be_32(lkey);
 518                         pv[pv_counter].dseg = dseg;
 519                         pv[pv_counter++].val = byte_count;
 520                 }
 521         }
 522         /* Write the first DWORD of each TXBB save earlier. */
 523         if (pv_counter) {
 524                 /* Need a barrier here before writing the byte_count. */
 525                 rte_io_wmb();
 526                 for (--pv_counter; pv_counter  >= 0; pv_counter--)
 527                         pv[pv_counter].dseg->byte_count = pv[pv_counter].val;
 528         }
 529         /* Fill the control parameters for this packet. */
 530         ctrl->fence_size = (wqe_real_size >> 4) & 0x3f;
 531         return nr_txbbs;
 532 }
 533
 534 /**
 535  * DPDK callback for Tx.
 536  *
 537  * @param dpdk_txq
 538  *   Generic pointer to Tx queue structure.
 539  * @param[in] pkts
 540  *   Packets to transmit.
 541  * @param pkts_n
 542  *   Number of packets in array.
 543  *
 544  * @return
 545  *   Number of packets successfully transmitted (<= pkts_n).
 546  */
 547 uint16_t
 548 mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 549 {
 550         struct txq *txq = (struct txq *)dpdk_txq;
 551         unsigned int elts_head = txq->elts_head;
 552         const unsigned int elts_n = txq->elts_n;
 553         unsigned int bytes_sent = 0;
 554         unsigned int i;
 555         unsigned int max;
 556         struct mlx4_sq *sq = &txq->msq;
 557         int nr_txbbs;
 558
 559         assert(txq->elts_comp_cd != 0);
 560         if (likely(txq->elts_comp != 0))
 561                 mlx4_txq_complete(txq, elts_n, sq);
 562         max = (elts_n - (elts_head - txq->elts_tail));
 563         if (max > elts_n)
 564                 max -= elts_n;
 565         assert(max >= 1);
 566         assert(max <= elts_n);
 567         /* Always leave one free entry in the ring. */
 568         --max;
 569         if (max > pkts_n)
 570                 max = pkts_n;
 571         for (i = 0; (i != max); ++i) {
 572                 struct rte_mbuf *buf = pkts[i];
 573                 unsigned int elts_head_next =
 574                         (((elts_head + 1) == elts_n) ? 0 : elts_head + 1);
 575                 struct txq_elt *elt_next = &(*txq->elts)[elts_head_next];
 576                 struct txq_elt *elt = &(*txq->elts)[elts_head];
 577                 uint32_t owner_opcode = MLX4_OPCODE_SEND;
 578                 volatile struct mlx4_wqe_ctrl_seg *ctrl;
 579                 volatile struct mlx4_wqe_data_seg *dseg;
 580                 union {
 581                         uint32_t flags;
 582                         uint16_t flags16[2];
 583                 } srcrb;
 584                 uint32_t head_idx = sq->head & sq->txbb_cnt_mask;
 585                 uint32_t lkey;
 586                 uintptr_t addr;
 587
 588                 /* Clean up old buffer. */
 589                 if (likely(elt->buf != NULL)) {
 590                         struct rte_mbuf *tmp = elt->buf;
 591
 592 #ifndef NDEBUG
 593                         /* Poisoning. */
 594                         memset(elt, 0x66, sizeof(*elt));
 595 #endif
 596                         /* Faster than rte_pktmbuf_free(). */
 597                         do {
 598                                 struct rte_mbuf *next = tmp->next;
 599
 600                                 rte_pktmbuf_free_seg(tmp);
 601                                 tmp = next;
 602                         } while (tmp != NULL);
 603                 }
 604                 RTE_MBUF_PREFETCH_TO_FREE(elt_next->buf);
 605                 if (buf->nb_segs == 1) {
 606                         /*
 607                          * Check that there is room for this WQE in the send
 608                          * queue and that the WQE size is legal
 609                          */
 610                         if (((sq->head - sq->tail) + 1 + sq->headroom_txbbs) >=
 611                              sq->txbb_cnt || 1 > MLX4_MAX_WQE_TXBBS) {
 612                                 elt->buf = NULL;
 613                                 break;
 614                         }
 615                         /* Get the control and data entries of the WQE. */
 616                         ctrl = (volatile struct mlx4_wqe_ctrl_seg *)
 617                                         mlx4_get_send_wqe(sq, head_idx);
 618                         dseg = (volatile struct mlx4_wqe_data_seg *)
 619                                         ((uintptr_t)ctrl +
 620                                         sizeof(struct mlx4_wqe_ctrl_seg));
 621                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 622                         rte_prefetch0((volatile void *)addr);
 623                         dseg->addr = rte_cpu_to_be_64(addr);
 624                         /* Memory region key (big endian). */
 625                         lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(buf));
 626                         dseg->lkey = rte_cpu_to_be_32(lkey);
 627                         if (unlikely(dseg->lkey ==
 628                                 rte_cpu_to_be_32((uint32_t)-1))) {
 629                                 /* MR does not exist. */
 630                                 DEBUG("%p: unable to get MP <-> MR association",
 631                                       (void *)txq);
 632                                 elt->buf = NULL;
 633                                 break;
 634                         }
 635                         /* Never be TXBB aligned, no need compiler barrier. */
 636                         dseg->byte_count = rte_cpu_to_be_32(buf->data_len);
 637                         /* Fill the control parameters for this packet. */
 638                         ctrl->fence_size = (WQE_ONE_DATA_SEG_SIZE >> 4) & 0x3f;
 639                         nr_txbbs = 1;
 640                 } else {
 641                         nr_txbbs = mlx4_tx_burst_segs(buf, txq, &ctrl);
 642                         if (nr_txbbs < 0) {
 643                                 elt->buf = NULL;
 644                                 break;
 645                         }
 646                 }
 647                 /*
 648                  * For raw Ethernet, the SOLICIT flag is used to indicate
 649                  * that no ICRC should be calculated.
 650                  */
 651                 txq->elts_comp_cd -= nr_txbbs;
 652                 if (unlikely(txq->elts_comp_cd <= 0)) {
 653                         txq->elts_comp_cd = txq->elts_comp_cd_init;
 654                         srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT |
 655                                                MLX4_WQE_CTRL_CQ_UPDATE);
 656                 } else {
 657                         srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT);
 658                 }
 659                 /* Enable HW checksum offload if requested */
 660                 if (txq->csum &&
 661                     (buf->ol_flags &
 662                      (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))) {
 663                         const uint64_t is_tunneled = (buf->ol_flags &
 664                                                       (PKT_TX_TUNNEL_GRE |
 665                                                        PKT_TX_TUNNEL_VXLAN));
 666
 667                         if (is_tunneled && txq->csum_l2tun) {
 668                                 owner_opcode |= MLX4_WQE_CTRL_IIP_HDR_CSUM |
 669                                                 MLX4_WQE_CTRL_IL4_HDR_CSUM;
 670                                 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
 671                                         srcrb.flags |=
 672                                             RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM);
 673                         } else {
 674                                 srcrb.flags |=
 675                                         RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM |
 676                                                 MLX4_WQE_CTRL_TCP_UDP_CSUM);
 677                         }
 678                 }
 679                 if (txq->lb) {
 680                         /*
 681                          * Copy destination MAC address to the WQE, this allows
 682                          * loopback in eSwitch, so that VFs and PF can
 683                          * communicate with each other.
 684                          */
 685                         srcrb.flags16[0] = *(rte_pktmbuf_mtod(buf, uint16_t *));
 686                         ctrl->imm = *(rte_pktmbuf_mtod_offset(buf, uint32_t *,
 687                                               sizeof(uint16_t)));
 688                 } else {
 689                         ctrl->imm = 0;
 690                 }
 691                 ctrl->srcrb_flags = srcrb.flags;
 692                 /*
 693                  * Make sure descriptor is fully written before
 694                  * setting ownership bit (because HW can start
 695                  * executing as soon as we do).
 696                  */
 697                 rte_io_wmb();
 698                 ctrl->owner_opcode = rte_cpu_to_be_32(owner_opcode |
 699                                               ((sq->head & sq->txbb_cnt) ?
 700                                                        MLX4_BIT_WQE_OWN : 0));
 701                 sq->head += nr_txbbs;
 702                 elt->buf = buf;
 703                 bytes_sent += buf->pkt_len;
 704                 elts_head = elts_head_next;
 705         }
 706         /* Take a shortcut if nothing must be sent. */
 707         if (unlikely(i == 0))
 708                 return 0;
 709         /* Increment send statistics counters. */
 710         txq->stats.opackets += i;
 711         txq->stats.obytes += bytes_sent;
 712         /* Make sure that descriptors are written before doorbell record. */
 713         rte_wmb();
 714         /* Ring QP doorbell. */
 715         rte_write32(txq->msq.doorbell_qpn, txq->msq.db);
 716         txq->elts_head = elts_head;
 717         txq->elts_comp += i;
 718         return i;
 719 }
 720
 721 /**
 722  * Translate Rx completion flags to packet type.
 723  *
 724  * @param[in] cqe
 725  *   Pointer to CQE.
 726  *
 727  * @return
 728  *   Packet type for struct rte_mbuf.
 729  */
 730 static inline uint32_t
 731 rxq_cq_to_pkt_type(volatile struct mlx4_cqe *cqe,
 732                    uint32_t l2tun_offload)
 733 {
 734         uint8_t idx = 0;
 735         uint32_t pinfo = rte_be_to_cpu_32(cqe->vlan_my_qpn);
 736         uint32_t status = rte_be_to_cpu_32(cqe->status);
 737
 738         /*
 739          * The index to the array should have:
 740          *  bit[7] - MLX4_CQE_L2_TUNNEL
 741          *  bit[6] - MLX4_CQE_L2_TUNNEL_IPV4
 742          */
 743         if (l2tun_offload && (pinfo & MLX4_CQE_L2_TUNNEL))
 744                 idx |= ((pinfo & MLX4_CQE_L2_TUNNEL) >> 20) |
 745                        ((pinfo & MLX4_CQE_L2_TUNNEL_IPV4) >> 19);
 746         /*
 747          * The index to the array should have:
 748          *  bit[5] - MLX4_CQE_STATUS_UDP
 749          *  bit[4] - MLX4_CQE_STATUS_TCP
 750          *  bit[3] - MLX4_CQE_STATUS_IPV4OPT
 751          *  bit[2] - MLX4_CQE_STATUS_IPV6
 752          *  bit[1] - MLX4_CQE_STATUS_IPV4F
 753          *  bit[0] - MLX4_CQE_STATUS_IPV4
 754          * giving a total of up to 256 entries.
 755          */
 756         idx |= ((status & MLX4_CQE_STATUS_PTYPE_MASK) >> 22);
 757         return mlx4_ptype_table[idx];
 758 }
 759
 760 /**
 761  * Translate Rx completion flags to offload flags.
 762  *
 763  * @param flags
 764  *   Rx completion flags returned by mlx4_cqe_flags().
 765  * @param csum
 766  *   Whether Rx checksums are enabled.
 767  * @param csum_l2tun
 768  *   Whether Rx L2 tunnel checksums are enabled.
 769  *
 770  * @return
 771  *   Offload flags (ol_flags) in mbuf format.
 772  */
 773 static inline uint32_t
 774 rxq_cq_to_ol_flags(uint32_t flags, int csum, int csum_l2tun)
 775 {
 776         uint32_t ol_flags = 0;
 777
 778         if (csum)
 779                 ol_flags |=
 780                         mlx4_transpose(flags,
 781                                        MLX4_CQE_STATUS_IP_HDR_CSUM_OK,
 782                                        PKT_RX_IP_CKSUM_GOOD) |
 783                         mlx4_transpose(flags,
 784                                        MLX4_CQE_STATUS_TCP_UDP_CSUM_OK,
 785                                        PKT_RX_L4_CKSUM_GOOD);
 786         if ((flags & MLX4_CQE_L2_TUNNEL) && csum_l2tun)
 787                 ol_flags |=
 788                         mlx4_transpose(flags,
 789                                        MLX4_CQE_L2_TUNNEL_IPOK,
 790                                        PKT_RX_IP_CKSUM_GOOD) |
 791                         mlx4_transpose(flags,
 792                                        MLX4_CQE_L2_TUNNEL_L4_CSUM,
 793                                        PKT_RX_L4_CKSUM_GOOD);
 794         return ol_flags;
 795 }
 796
 797 /**
 798  * Extract checksum information from CQE flags.
 799  *
 800  * @param cqe
 801  *   Pointer to CQE structure.
 802  * @param csum
 803  *   Whether Rx checksums are enabled.
 804  * @param csum_l2tun
 805  *   Whether Rx L2 tunnel checksums are enabled.
 806  *
 807  * @return
 808  *   CQE checksum information.
 809  */
 810 static inline uint32_t
 811 mlx4_cqe_flags(volatile struct mlx4_cqe *cqe, int csum, int csum_l2tun)
 812 {
 813         uint32_t flags = 0;
 814
 815         /*
 816          * The relevant bits are in different locations on their
 817          * CQE fields therefore we can join them in one 32bit
 818          * variable.
 819          */
 820         if (csum)
 821                 flags = (rte_be_to_cpu_32(cqe->status) &
 822                          MLX4_CQE_STATUS_IPV4_CSUM_OK);
 823         if (csum_l2tun)
 824                 flags |= (rte_be_to_cpu_32(cqe->vlan_my_qpn) &
 825                           (MLX4_CQE_L2_TUNNEL |
 826                            MLX4_CQE_L2_TUNNEL_IPOK |
 827                            MLX4_CQE_L2_TUNNEL_L4_CSUM |
 828                            MLX4_CQE_L2_TUNNEL_IPV4));
 829         return flags;
 830 }
 831
 832 /**
 833  * Poll one CQE from CQ.
 834  *
 835  * @param rxq
 836  *   Pointer to the receive queue structure.
 837  * @param[out] out
 838  *   Just polled CQE.
 839  *
 840  * @return
 841  *   Number of bytes of the CQE, 0 in case there is no completion.
 842  */
 843 static unsigned int
 844 mlx4_cq_poll_one(struct rxq *rxq, volatile struct mlx4_cqe **out)
 845 {
 846         int ret = 0;
 847         volatile struct mlx4_cqe *cqe = NULL;
 848         struct mlx4_cq *cq = &rxq->mcq;
 849
 850         cqe = (volatile struct mlx4_cqe *)mlx4_get_cqe(cq, cq->cons_index);
 851         if (!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
 852             !!(cq->cons_index & cq->cqe_cnt))
 853                 goto out;
 854         /*
 855          * Make sure we read CQ entry contents after we've checked the
 856          * ownership bit.
 857          */
 858         rte_rmb();
 859         assert(!(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK));
 860         assert((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) !=
 861                MLX4_CQE_OPCODE_ERROR);
 862         ret = rte_be_to_cpu_32(cqe->byte_cnt);
 863         ++cq->cons_index;
 864 out:
 865         *out = cqe;
 866         return ret;
 867 }
 868
 869 /**
 870  * DPDK callback for Rx with scattered packets support.
 871  *
 872  * @param dpdk_rxq
 873  *   Generic pointer to Rx queue structure.
 874  * @param[out] pkts
 875  *   Array to store received packets.
 876  * @param pkts_n
 877  *   Maximum number of packets in array.
 878  *
 879  * @return
 880  *   Number of packets successfully received (<= pkts_n).
 881  */
 882 uint16_t
 883 mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
 884 {
 885         struct rxq *rxq = dpdk_rxq;
 886         const uint32_t wr_cnt = (1 << rxq->elts_n) - 1;
 887         const uint16_t sges_n = rxq->sges_n;
 888         struct rte_mbuf *pkt = NULL;
 889         struct rte_mbuf *seg = NULL;
 890         unsigned int i = 0;
 891         uint32_t rq_ci = rxq->rq_ci << sges_n;
 892         int len = 0;
 893
 894         while (pkts_n) {
 895                 volatile struct mlx4_cqe *cqe;
 896                 uint32_t idx = rq_ci & wr_cnt;
 897                 struct rte_mbuf *rep = (*rxq->elts)[idx];
 898                 volatile struct mlx4_wqe_data_seg *scat = &(*rxq->wqes)[idx];
 899
 900                 /* Update the 'next' pointer of the previous segment. */
 901                 if (pkt)
 902                         seg->next = rep;
 903                 seg = rep;
 904                 rte_prefetch0(seg);
 905                 rte_prefetch0(scat);
 906                 rep = rte_mbuf_raw_alloc(rxq->mp);
 907                 if (unlikely(rep == NULL)) {
 908                         ++rxq->stats.rx_nombuf;
 909                         if (!pkt) {
 910                                 /*
 911                                  * No buffers before we even started,
 912                                  * bail out silently.
 913                                  */
 914                                 break;
 915                         }
 916                         while (pkt != seg) {
 917                                 assert(pkt != (*rxq->elts)[idx]);
 918                                 rep = pkt->next;
 919                                 pkt->next = NULL;
 920                                 pkt->nb_segs = 1;
 921                                 rte_mbuf_raw_free(pkt);
 922                                 pkt = rep;
 923                         }
 924                         break;
 925                 }
 926                 if (!pkt) {
 927                         /* Looking for the new packet. */
 928                         len = mlx4_cq_poll_one(rxq, &cqe);
 929                         if (!len) {
 930                                 rte_mbuf_raw_free(rep);
 931                                 break;
 932                         }
 933                         if (unlikely(len < 0)) {
 934                                 /* Rx error, packet is likely too large. */
 935                                 rte_mbuf_raw_free(rep);
 936                                 ++rxq->stats.idropped;
 937                                 goto skip;
 938                         }
 939                         pkt = seg;
 940                         /* Update packet information. */
 941                         pkt->packet_type =
 942                                 rxq_cq_to_pkt_type(cqe, rxq->l2tun_offload);
 943                         pkt->ol_flags = PKT_RX_RSS_HASH;
 944                         pkt->hash.rss = cqe->immed_rss_invalid;
 945                         pkt->pkt_len = len;
 946                         if (rxq->csum | rxq->csum_l2tun) {
 947                                 uint32_t flags =
 948                                         mlx4_cqe_flags(cqe,
 949                                                        rxq->csum,
 950                                                        rxq->csum_l2tun);
 951
 952                                 pkt->ol_flags =
 953                                         rxq_cq_to_ol_flags(flags,
 954                                                            rxq->csum,
 955                                                            rxq->csum_l2tun);
 956                         }
 957                 }
 958                 rep->nb_segs = 1;
 959                 rep->port = rxq->port_id;
 960                 rep->data_len = seg->data_len;
 961                 rep->data_off = seg->data_off;
 962                 (*rxq->elts)[idx] = rep;
 963                 /*
 964                  * Fill NIC descriptor with the new buffer. The lkey and size
 965                  * of the buffers are already known, only the buffer address
 966                  * changes.
 967                  */
 968                 scat->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
 969                 if (len > seg->data_len) {
 970                         len -= seg->data_len;
 971                         ++pkt->nb_segs;
 972                         ++rq_ci;
 973                         continue;
 974                 }
 975                 /* The last segment. */
 976                 seg->data_len = len;
 977                 /* Increment bytes counter. */
 978                 rxq->stats.ibytes += pkt->pkt_len;
 979                 /* Return packet. */
 980                 *(pkts++) = pkt;
 981                 pkt = NULL;
 982                 --pkts_n;
 983                 ++i;
 984 skip:
 985                 /* Align consumer index to the next stride. */
 986                 rq_ci >>= sges_n;
 987                 ++rq_ci;
 988                 rq_ci <<= sges_n;
 989         }
 990         if (unlikely(i == 0 && (rq_ci >> sges_n) == rxq->rq_ci))
 991                 return 0;
 992         /* Update the consumer index. */
 993         rxq->rq_ci = rq_ci >> sges_n;
 994         rte_wmb();
 995         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
 996         *rxq->mcq.set_ci_db =
 997                 rte_cpu_to_be_32(rxq->mcq.cons_index & MLX4_CQ_DB_CI_MASK);
 998         /* Increment packets counter. */
 999         rxq->stats.ipackets += i;
1000         return i;
1001 }
1002
1003 /**
1004  * Dummy DPDK callback for Tx.
1005  *
1006  * This function is used to temporarily replace the real callback during
1007  * unsafe control operations on the queue, or in case of error.
1008  *
1009  * @param dpdk_txq
1010  *   Generic pointer to Tx queue structure.
1011  * @param[in] pkts
1012  *   Packets to transmit.
1013  * @param pkts_n
1014  *   Number of packets in array.
1015  *
1016  * @return
1017  *   Number of packets successfully transmitted (<= pkts_n).
1018  */
1019 uint16_t
1020 mlx4_tx_burst_removed(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1021 {
1022         (void)dpdk_txq;
1023         (void)pkts;
1024         (void)pkts_n;
1025         return 0;
1026 }
1027
1028 /**
1029  * Dummy DPDK callback for Rx.
1030  *
1031  * This function is used to temporarily replace the real callback during
1032  * unsafe control operations on the queue, or in case of error.
1033  *
1034  * @param dpdk_rxq
1035  *   Generic pointer to Rx queue structure.
1036  * @param[out] pkts
1037  *   Array to store received packets.
1038  * @param pkts_n
1039  *   Maximum number of packets in array.
1040  *
1041  * @return
1042  *   Number of packets successfully received (<= pkts_n).
1043  */
1044 uint16_t
1045 mlx4_rx_burst_removed(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1046 {
1047         (void)dpdk_rxq;
1048         (void)pkts;
1049         (void)pkts_n;
1050         return 0;
1051 }