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5 * Copyright 2017 Mellanox
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36 * Data plane functions for mlx4 driver.
43 /* Verbs headers do not support -pedantic. */
45 #pragma GCC diagnostic ignored "-Wpedantic"
47 #include <infiniband/verbs.h>
49 #pragma GCC diagnostic error "-Wpedantic"
52 #include <rte_branch_prediction.h>
53 #include <rte_common.h>
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
61 #include "mlx4_rxtx.h"
62 #include "mlx4_utils.h"
65 * Pointer-value pair structure used in tx_post_send for saving the first
66 * DWORD (32 byte) of a TXBB.
69 struct mlx4_wqe_data_seg *dseg;
74 * Stamp a WQE so it won't be reused by the HW.
76 * Routine is used when freeing WQE used by the chip or when failing
77 * building an WQ entry has failed leaving partial information on the queue.
80 * Pointer to the SQ structure.
82 * Index of the freed WQE.
84 * Number of blocks to stamp.
85 * If < 0 the routine will use the size written in the WQ entry.
87 * The value of the WQE owner bit to use in the stamp.
90 * The number of Tx basic blocs (TXBB) the WQE contained.
93 mlx4_txq_stamp_freed_wqe(struct mlx4_sq *sq, uint16_t index, uint8_t owner)
95 uint32_t stamp = rte_cpu_to_be_32(MLX4_SQ_STAMP_VAL |
96 (!!owner << MLX4_SQ_STAMP_SHIFT));
97 uint8_t *wqe = mlx4_get_send_wqe(sq, (index & sq->txbb_cnt_mask));
98 uint32_t *ptr = (uint32_t *)wqe;
103 /* Extract the size from the control segment of the WQE. */
104 num_txbbs = MLX4_SIZE_TO_TXBBS((((struct mlx4_wqe_ctrl_seg *)
105 wqe)->fence_size & 0x3f) << 4);
106 txbbs_size = num_txbbs * MLX4_TXBB_SIZE;
107 /* Optimize the common case when there is no wrap-around. */
108 if (wqe + txbbs_size <= sq->eob) {
109 /* Stamp the freed descriptor. */
110 for (i = 0; i < txbbs_size; i += MLX4_SQ_STAMP_STRIDE) {
112 ptr += MLX4_SQ_STAMP_DWORDS;
115 /* Stamp the freed descriptor. */
116 for (i = 0; i < txbbs_size; i += MLX4_SQ_STAMP_STRIDE) {
118 ptr += MLX4_SQ_STAMP_DWORDS;
119 if ((uint8_t *)ptr >= sq->eob) {
120 ptr = (uint32_t *)sq->buf;
121 stamp ^= RTE_BE32(0x80000000);
129 * Manage Tx completions.
131 * When sending a burst, mlx4_tx_burst() posts several WRs.
132 * To improve performance, a completion event is only required once every
133 * MLX4_PMD_TX_PER_COMP_REQ sends. Doing so discards completion information
134 * for other WRs, but this information would not be used anyway.
137 * Pointer to Tx queue structure.
140 * 0 on success, -1 on failure.
143 mlx4_txq_complete(struct txq *txq)
145 unsigned int elts_comp = txq->elts_comp;
146 unsigned int elts_tail = txq->elts_tail;
147 const unsigned int elts_n = txq->elts_n;
148 struct mlx4_cq *cq = &txq->mcq;
149 struct mlx4_sq *sq = &txq->msq;
150 struct mlx4_cqe *cqe;
151 uint32_t cons_index = cq->cons_index;
153 uint16_t nr_txbbs = 0;
156 if (unlikely(elts_comp == 0))
159 * Traverse over all CQ entries reported and handle each WQ entry
163 cqe = (struct mlx4_cqe *)mlx4_get_cqe(cq, cons_index);
164 if (unlikely(!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
165 !!(cons_index & cq->cqe_cnt)))
168 * Make sure we read the CQE after we read the ownership bit.
172 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
173 MLX4_CQE_OPCODE_ERROR)) {
174 struct mlx4_err_cqe *cqe_err =
175 (struct mlx4_err_cqe *)cqe;
176 ERROR("%p CQE error - vendor syndrome: 0x%x"
178 (void *)txq, cqe_err->vendor_err,
182 /* Get WQE index reported in the CQE. */
184 rte_be_to_cpu_16(cqe->wqe_index) & sq->txbb_cnt_mask;
186 /* Free next descriptor. */
188 mlx4_txq_stamp_freed_wqe(sq,
189 (sq->tail + nr_txbbs) & sq->txbb_cnt_mask,
190 !!((sq->tail + nr_txbbs) & sq->txbb_cnt));
192 } while (((sq->tail + nr_txbbs) & sq->txbb_cnt_mask) !=
196 if (unlikely(pkts == 0))
200 * To prevent CQ overflow we first update CQ consumer and only then
203 cq->cons_index = cons_index;
204 *cq->set_ci_db = rte_cpu_to_be_32(cq->cons_index & MLX4_CQ_DB_CI_MASK);
206 sq->tail = sq->tail + nr_txbbs;
207 /* Update the list of packets posted for transmission. */
209 assert(elts_comp <= txq->elts_comp);
211 * Assume completion status is successful as nothing can be done about
215 if (elts_tail >= elts_n)
217 txq->elts_tail = elts_tail;
218 txq->elts_comp = elts_comp;
223 * Get memory pool (MP) from mbuf. If mbuf is indirect, the pool from which
224 * the cloned mbuf is allocated is returned instead.
230 * Memory pool where data is located for given mbuf.
232 static struct rte_mempool *
233 mlx4_txq_mb2mp(struct rte_mbuf *buf)
235 if (unlikely(RTE_MBUF_INDIRECT(buf)))
236 return rte_mbuf_from_indirect(buf)->pool;
241 * DPDK callback for Tx.
244 * Generic pointer to Tx queue structure.
246 * Packets to transmit.
248 * Number of packets in array.
251 * Number of packets successfully transmitted (<= pkts_n).
254 mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
256 struct txq *txq = (struct txq *)dpdk_txq;
257 unsigned int elts_head = txq->elts_head;
258 const unsigned int elts_n = txq->elts_n;
259 unsigned int elts_comp = 0;
260 unsigned int bytes_sent = 0;
263 struct mlx4_sq *sq = &txq->msq;
264 struct pv *pv = (struct pv *)txq->bounce_buf;
266 assert(txq->elts_comp_cd != 0);
267 mlx4_txq_complete(txq);
268 max = (elts_n - (elts_head - txq->elts_tail));
272 assert(max <= elts_n);
273 /* Always leave one free entry in the ring. */
279 for (i = 0; (i != max); ++i) {
280 struct rte_mbuf *buf = pkts[i];
281 unsigned int elts_head_next =
282 (((elts_head + 1) == elts_n) ? 0 : elts_head + 1);
283 struct txq_elt *elt_next = &(*txq->elts)[elts_head_next];
284 struct txq_elt *elt = &(*txq->elts)[elts_head];
285 uint32_t owner_opcode = MLX4_OPCODE_SEND;
286 struct mlx4_wqe_ctrl_seg *ctrl;
287 struct mlx4_wqe_data_seg *dseg;
288 struct rte_mbuf *sbuf;
293 uint32_t head_idx = sq->head & sq->txbb_cnt_mask;
301 /* Clean up old buffer. */
302 if (likely(elt->buf != NULL)) {
303 struct rte_mbuf *tmp = elt->buf;
307 memset(elt, 0x66, sizeof(*elt));
309 /* Faster than rte_pktmbuf_free(). */
311 struct rte_mbuf *next = tmp->next;
313 rte_pktmbuf_free_seg(tmp);
315 } while (tmp != NULL);
317 RTE_MBUF_PREFETCH_TO_FREE(elt_next->buf);
319 * Calculate the needed work queue entry size
322 wqe_real_size = sizeof(struct mlx4_wqe_ctrl_seg) +
323 buf->nb_segs * sizeof(struct mlx4_wqe_data_seg);
324 nr_txbbs = MLX4_SIZE_TO_TXBBS(wqe_real_size);
326 * Check that there is room for this WQE in the send
327 * queue and that the WQE size is legal.
329 if (((sq->head - sq->tail) + nr_txbbs +
330 sq->headroom_txbbs) >= sq->txbb_cnt ||
331 nr_txbbs > MLX4_MAX_WQE_TXBBS) {
335 /* Get the control and data entries of the WQE. */
336 ctrl = (struct mlx4_wqe_ctrl_seg *)
337 mlx4_get_send_wqe(sq, head_idx);
338 dseg = (struct mlx4_wqe_data_seg *)((uintptr_t)ctrl +
339 sizeof(struct mlx4_wqe_ctrl_seg));
340 /* Fill the data segments with buffer information. */
341 for (sbuf = buf; sbuf != NULL; sbuf = sbuf->next, dseg++) {
342 addr = rte_pktmbuf_mtod(sbuf, uintptr_t);
343 rte_prefetch0((volatile void *)addr);
344 /* Handle WQE wraparound. */
345 if (dseg >= (struct mlx4_wqe_data_seg *)sq->eob)
346 dseg = (struct mlx4_wqe_data_seg *)sq->buf;
347 dseg->addr = rte_cpu_to_be_64(addr);
348 /* Memory region key (big endian). */
349 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
350 dseg->lkey = rte_cpu_to_be_32(lkey);
352 if (unlikely(dseg->lkey ==
353 rte_cpu_to_be_32((uint32_t)-1))) {
354 /* MR does not exist. */
355 DEBUG("%p: unable to get MP <-> MR association",
358 * Restamp entry in case of failure.
359 * Make sure that size is written correctly
360 * Note that we give ownership to the SW,
363 ctrl->fence_size = (wqe_real_size >> 4) & 0x3f;
364 mlx4_txq_stamp_freed_wqe(sq, head_idx,
365 (sq->head & sq->txbb_cnt) ? 0 : 1);
370 if (likely(sbuf->data_len)) {
371 byte_count = rte_cpu_to_be_32(sbuf->data_len);
374 * Zero length segment is treated as inline
375 * segment with zero data.
377 byte_count = RTE_BE32(0x80000000);
380 * If the data segment is not at the beginning
381 * of a Tx basic block (TXBB) then write the
382 * byte count, else postpone the writing to
383 * just before updating the control segment.
385 if ((uintptr_t)dseg & (uintptr_t)(MLX4_TXBB_SIZE - 1)) {
387 * Need a barrier here before writing the
388 * byte_count fields to make sure that all the
389 * data is visible before the byte_count field
390 * is set. otherwise, if the segment begins a
391 * new cacheline, the HCA prefetcher could grab
392 * the 64-byte chunk and get a valid
393 * (!= 0xffffffff) byte count but stale data,
394 * and end up sending the wrong data.
397 dseg->byte_count = byte_count;
400 * This data segment starts at the beginning of
401 * a new TXBB, so we need to postpone its
402 * byte_count writing for later.
404 pv[pv_counter].dseg = dseg;
405 pv[pv_counter++].val = byte_count;
408 /* Write the first DWORD of each TXBB save earlier. */
410 /* Need a barrier before writing the byte_count. */
412 for (--pv_counter; pv_counter >= 0; pv_counter--)
413 pv[pv_counter].dseg->byte_count =
416 /* Fill the control parameters for this packet. */
417 ctrl->fence_size = (wqe_real_size >> 4) & 0x3f;
419 * For raw Ethernet, the SOLICIT flag is used to indicate
420 * that no ICRC should be calculated.
422 txq->elts_comp_cd -= nr_txbbs;
423 if (unlikely(txq->elts_comp_cd <= 0)) {
424 txq->elts_comp_cd = txq->elts_comp_cd_init;
425 srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT |
426 MLX4_WQE_CTRL_CQ_UPDATE);
428 srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT);
430 /* Enable HW checksum offload if requested */
433 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))) {
434 const uint64_t is_tunneled = (buf->ol_flags &
436 PKT_TX_TUNNEL_VXLAN));
438 if (is_tunneled && txq->csum_l2tun) {
439 owner_opcode |= MLX4_WQE_CTRL_IIP_HDR_CSUM |
440 MLX4_WQE_CTRL_IL4_HDR_CSUM;
441 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
443 RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM);
446 RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM |
447 MLX4_WQE_CTRL_TCP_UDP_CSUM);
452 * Copy destination MAC address to the WQE, this allows
453 * loopback in eSwitch, so that VFs and PF can
454 * communicate with each other.
456 srcrb.flags16[0] = *(rte_pktmbuf_mtod(buf, uint16_t *));
457 ctrl->imm = *(rte_pktmbuf_mtod_offset(buf, uint32_t *,
462 ctrl->srcrb_flags = srcrb.flags;
464 * Make sure descriptor is fully written before
465 * setting ownership bit (because HW can start
466 * executing as soon as we do).
469 ctrl->owner_opcode = rte_cpu_to_be_32(owner_opcode |
470 ((sq->head & sq->txbb_cnt) ?
471 MLX4_BIT_WQE_OWN : 0));
472 sq->head += nr_txbbs;
474 bytes_sent += buf->pkt_len;
476 elts_head = elts_head_next;
478 /* Take a shortcut if nothing must be sent. */
479 if (unlikely(i == 0))
481 /* Increment send statistics counters. */
482 txq->stats.opackets += i;
483 txq->stats.obytes += bytes_sent;
484 /* Make sure that descriptors are written before doorbell record. */
486 /* Ring QP doorbell. */
487 rte_write32(txq->msq.doorbell_qpn, txq->msq.db);
488 txq->elts_head = elts_head;
489 txq->elts_comp += elts_comp;
494 * Translate Rx completion flags to packet type.
497 * Rx completion flags returned by mlx4_cqe_flags().
500 * Packet type in mbuf format.
502 static inline uint32_t
503 rxq_cq_to_pkt_type(uint32_t flags)
507 if (flags & MLX4_CQE_L2_TUNNEL)
509 mlx4_transpose(flags,
510 MLX4_CQE_L2_TUNNEL_IPV4,
511 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN) |
512 mlx4_transpose(flags,
513 MLX4_CQE_STATUS_IPV4_PKT,
514 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN);
516 pkt_type = mlx4_transpose(flags,
517 MLX4_CQE_STATUS_IPV4_PKT,
518 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
523 * Translate Rx completion flags to offload flags.
526 * Rx completion flags returned by mlx4_cqe_flags().
528 * Whether Rx checksums are enabled.
530 * Whether Rx L2 tunnel checksums are enabled.
533 * Offload flags (ol_flags) in mbuf format.
535 static inline uint32_t
536 rxq_cq_to_ol_flags(uint32_t flags, int csum, int csum_l2tun)
538 uint32_t ol_flags = 0;
542 mlx4_transpose(flags,
543 MLX4_CQE_STATUS_IP_HDR_CSUM_OK,
544 PKT_RX_IP_CKSUM_GOOD) |
545 mlx4_transpose(flags,
546 MLX4_CQE_STATUS_TCP_UDP_CSUM_OK,
547 PKT_RX_L4_CKSUM_GOOD);
548 if ((flags & MLX4_CQE_L2_TUNNEL) && csum_l2tun)
550 mlx4_transpose(flags,
551 MLX4_CQE_L2_TUNNEL_IPOK,
552 PKT_RX_IP_CKSUM_GOOD) |
553 mlx4_transpose(flags,
554 MLX4_CQE_L2_TUNNEL_L4_CSUM,
555 PKT_RX_L4_CKSUM_GOOD);
560 * Extract checksum information from CQE flags.
563 * Pointer to CQE structure.
565 * Whether Rx checksums are enabled.
567 * Whether Rx L2 tunnel checksums are enabled.
570 * CQE checksum information.
572 static inline uint32_t
573 mlx4_cqe_flags(struct mlx4_cqe *cqe, int csum, int csum_l2tun)
578 * The relevant bits are in different locations on their
579 * CQE fields therefore we can join them in one 32bit
583 flags = (rte_be_to_cpu_32(cqe->status) &
584 MLX4_CQE_STATUS_IPV4_CSUM_OK);
586 flags |= (rte_be_to_cpu_32(cqe->vlan_my_qpn) &
587 (MLX4_CQE_L2_TUNNEL |
588 MLX4_CQE_L2_TUNNEL_IPOK |
589 MLX4_CQE_L2_TUNNEL_L4_CSUM |
590 MLX4_CQE_L2_TUNNEL_IPV4));
595 * Poll one CQE from CQ.
598 * Pointer to the receive queue structure.
603 * Number of bytes of the CQE, 0 in case there is no completion.
606 mlx4_cq_poll_one(struct rxq *rxq, struct mlx4_cqe **out)
609 struct mlx4_cqe *cqe = NULL;
610 struct mlx4_cq *cq = &rxq->mcq;
612 cqe = (struct mlx4_cqe *)mlx4_get_cqe(cq, cq->cons_index);
613 if (!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
614 !!(cq->cons_index & cq->cqe_cnt))
617 * Make sure we read CQ entry contents after we've checked the
621 assert(!(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK));
622 assert((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) !=
623 MLX4_CQE_OPCODE_ERROR);
624 ret = rte_be_to_cpu_32(cqe->byte_cnt);
632 * DPDK callback for Rx with scattered packets support.
635 * Generic pointer to Rx queue structure.
637 * Array to store received packets.
639 * Maximum number of packets in array.
642 * Number of packets successfully received (<= pkts_n).
645 mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
647 struct rxq *rxq = dpdk_rxq;
648 const uint32_t wr_cnt = (1 << rxq->elts_n) - 1;
649 const uint16_t sges_n = rxq->sges_n;
650 struct rte_mbuf *pkt = NULL;
651 struct rte_mbuf *seg = NULL;
653 uint32_t rq_ci = rxq->rq_ci << sges_n;
657 struct mlx4_cqe *cqe;
658 uint32_t idx = rq_ci & wr_cnt;
659 struct rte_mbuf *rep = (*rxq->elts)[idx];
660 volatile struct mlx4_wqe_data_seg *scat = &(*rxq->wqes)[idx];
662 /* Update the 'next' pointer of the previous segment. */
668 rep = rte_mbuf_raw_alloc(rxq->mp);
669 if (unlikely(rep == NULL)) {
670 ++rxq->stats.rx_nombuf;
673 * No buffers before we even started,
679 assert(pkt != (*rxq->elts)[idx]);
683 rte_mbuf_raw_free(pkt);
689 /* Looking for the new packet. */
690 len = mlx4_cq_poll_one(rxq, &cqe);
692 rte_mbuf_raw_free(rep);
695 if (unlikely(len < 0)) {
696 /* Rx error, packet is likely too large. */
697 rte_mbuf_raw_free(rep);
698 ++rxq->stats.idropped;
702 if (rxq->csum | rxq->csum_l2tun) {
709 rxq_cq_to_ol_flags(flags,
712 pkt->packet_type = rxq_cq_to_pkt_type(flags);
714 pkt->packet_type = 0;
720 rep->port = rxq->port_id;
721 rep->data_len = seg->data_len;
722 rep->data_off = seg->data_off;
723 (*rxq->elts)[idx] = rep;
725 * Fill NIC descriptor with the new buffer. The lkey and size
726 * of the buffers are already known, only the buffer address
729 scat->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
730 if (len > seg->data_len) {
731 len -= seg->data_len;
736 /* The last segment. */
738 /* Increment bytes counter. */
739 rxq->stats.ibytes += pkt->pkt_len;
746 /* Align consumer index to the next stride. */
751 if (unlikely(i == 0 && (rq_ci >> sges_n) == rxq->rq_ci))
753 /* Update the consumer index. */
754 rxq->rq_ci = rq_ci >> sges_n;
756 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
757 *rxq->mcq.set_ci_db =
758 rte_cpu_to_be_32(rxq->mcq.cons_index & MLX4_CQ_DB_CI_MASK);
759 /* Increment packets counter. */
760 rxq->stats.ipackets += i;
765 * Dummy DPDK callback for Tx.
767 * This function is used to temporarily replace the real callback during
768 * unsafe control operations on the queue, or in case of error.
771 * Generic pointer to Tx queue structure.
773 * Packets to transmit.
775 * Number of packets in array.
778 * Number of packets successfully transmitted (<= pkts_n).
781 mlx4_tx_burst_removed(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
790 * Dummy DPDK callback for Rx.
792 * This function is used to temporarily replace the real callback during
793 * unsafe control operations on the queue, or in case of error.
796 * Generic pointer to Rx queue structure.
798 * Array to store received packets.
800 * Maximum number of packets in array.
803 * Number of packets successfully received (<= pkts_n).
806 mlx4_rx_burst_removed(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)