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5 * Copyright 2017 Mellanox
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36 * Data plane functions for mlx4 driver.
43 /* Verbs headers do not support -pedantic. */
45 #pragma GCC diagnostic ignored "-Wpedantic"
47 #include <infiniband/verbs.h>
49 #pragma GCC diagnostic error "-Wpedantic"
52 #include <rte_branch_prediction.h>
53 #include <rte_common.h>
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
61 #include "mlx4_rxtx.h"
62 #include "mlx4_utils.h"
65 * Pointer-value pair structure used in tx_post_send for saving the first
66 * DWORD (32 byte) of a TXBB.
69 struct mlx4_wqe_data_seg *dseg;
74 * Stamp a WQE so it won't be reused by the HW.
76 * Routine is used when freeing WQE used by the chip or when failing
77 * building an WQ entry has failed leaving partial information on the queue.
80 * Pointer to the SQ structure.
82 * Index of the freed WQE.
84 * Number of blocks to stamp.
85 * If < 0 the routine will use the size written in the WQ entry.
87 * The value of the WQE owner bit to use in the stamp.
90 * The number of Tx basic blocs (TXBB) the WQE contained.
93 mlx4_txq_stamp_freed_wqe(struct mlx4_sq *sq, uint16_t index, uint8_t owner)
95 uint32_t stamp = rte_cpu_to_be_32(MLX4_SQ_STAMP_VAL |
96 (!!owner << MLX4_SQ_STAMP_SHIFT));
97 uint8_t *wqe = mlx4_get_send_wqe(sq, (index & sq->txbb_cnt_mask));
98 uint32_t *ptr = (uint32_t *)wqe;
103 /* Extract the size from the control segment of the WQE. */
104 num_txbbs = MLX4_SIZE_TO_TXBBS((((struct mlx4_wqe_ctrl_seg *)
105 wqe)->fence_size & 0x3f) << 4);
106 txbbs_size = num_txbbs * MLX4_TXBB_SIZE;
107 /* Optimize the common case when there is no wrap-around. */
108 if (wqe + txbbs_size <= sq->eob) {
109 /* Stamp the freed descriptor. */
110 for (i = 0; i < txbbs_size; i += MLX4_SQ_STAMP_STRIDE) {
112 ptr += MLX4_SQ_STAMP_DWORDS;
115 /* Stamp the freed descriptor. */
116 for (i = 0; i < txbbs_size; i += MLX4_SQ_STAMP_STRIDE) {
118 ptr += MLX4_SQ_STAMP_DWORDS;
119 if ((uint8_t *)ptr >= sq->eob) {
120 ptr = (uint32_t *)sq->buf;
121 stamp ^= RTE_BE32(0x80000000);
129 * Manage Tx completions.
131 * When sending a burst, mlx4_tx_burst() posts several WRs.
132 * To improve performance, a completion event is only required once every
133 * MLX4_PMD_TX_PER_COMP_REQ sends. Doing so discards completion information
134 * for other WRs, but this information would not be used anyway.
137 * Pointer to Tx queue structure.
140 * 0 on success, -1 on failure.
143 mlx4_txq_complete(struct txq *txq)
145 unsigned int elts_comp = txq->elts_comp;
146 unsigned int elts_tail = txq->elts_tail;
147 const unsigned int elts_n = txq->elts_n;
148 struct mlx4_cq *cq = &txq->mcq;
149 struct mlx4_sq *sq = &txq->msq;
150 struct mlx4_cqe *cqe;
151 uint32_t cons_index = cq->cons_index;
153 uint16_t nr_txbbs = 0;
156 if (unlikely(elts_comp == 0))
159 * Traverse over all CQ entries reported and handle each WQ entry
163 cqe = (struct mlx4_cqe *)mlx4_get_cqe(cq, cons_index);
164 if (unlikely(!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
165 !!(cons_index & cq->cqe_cnt)))
168 * Make sure we read the CQE after we read the ownership bit.
172 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
173 MLX4_CQE_OPCODE_ERROR)) {
174 struct mlx4_err_cqe *cqe_err =
175 (struct mlx4_err_cqe *)cqe;
176 ERROR("%p CQE error - vendor syndrome: 0x%x"
178 (void *)txq, cqe_err->vendor_err,
182 /* Get WQE index reported in the CQE. */
184 rte_be_to_cpu_16(cqe->wqe_index) & sq->txbb_cnt_mask;
186 /* Free next descriptor. */
188 mlx4_txq_stamp_freed_wqe(sq,
189 (sq->tail + nr_txbbs) & sq->txbb_cnt_mask,
190 !!((sq->tail + nr_txbbs) & sq->txbb_cnt));
192 } while (((sq->tail + nr_txbbs) & sq->txbb_cnt_mask) !=
196 if (unlikely(pkts == 0))
200 * To prevent CQ overflow we first update CQ consumer and only then
203 cq->cons_index = cons_index;
204 *cq->set_ci_db = rte_cpu_to_be_32(cq->cons_index & MLX4_CQ_DB_CI_MASK);
206 sq->tail = sq->tail + nr_txbbs;
207 /* Update the list of packets posted for transmission. */
209 assert(elts_comp <= txq->elts_comp);
211 * Assume completion status is successful as nothing can be done about
215 if (elts_tail >= elts_n)
217 txq->elts_tail = elts_tail;
218 txq->elts_comp = elts_comp;
223 * Get memory pool (MP) from mbuf. If mbuf is indirect, the pool from which
224 * the cloned mbuf is allocated is returned instead.
230 * Memory pool where data is located for given mbuf.
232 static struct rte_mempool *
233 mlx4_txq_mb2mp(struct rte_mbuf *buf)
235 if (unlikely(RTE_MBUF_INDIRECT(buf)))
236 return rte_mbuf_from_indirect(buf)->pool;
241 * DPDK callback for Tx.
244 * Generic pointer to Tx queue structure.
246 * Packets to transmit.
248 * Number of packets in array.
251 * Number of packets successfully transmitted (<= pkts_n).
254 mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
256 struct txq *txq = (struct txq *)dpdk_txq;
257 unsigned int elts_head = txq->elts_head;
258 const unsigned int elts_n = txq->elts_n;
259 unsigned int bytes_sent = 0;
262 struct mlx4_sq *sq = &txq->msq;
263 struct pv *pv = (struct pv *)txq->bounce_buf;
265 assert(txq->elts_comp_cd != 0);
266 mlx4_txq_complete(txq);
267 max = (elts_n - (elts_head - txq->elts_tail));
271 assert(max <= elts_n);
272 /* Always leave one free entry in the ring. */
276 for (i = 0; (i != max); ++i) {
277 struct rte_mbuf *buf = pkts[i];
278 unsigned int elts_head_next =
279 (((elts_head + 1) == elts_n) ? 0 : elts_head + 1);
280 struct txq_elt *elt_next = &(*txq->elts)[elts_head_next];
281 struct txq_elt *elt = &(*txq->elts)[elts_head];
282 uint32_t owner_opcode = MLX4_OPCODE_SEND;
283 struct mlx4_wqe_ctrl_seg *ctrl;
284 struct mlx4_wqe_data_seg *dseg;
285 struct rte_mbuf *sbuf;
290 uint32_t head_idx = sq->head & sq->txbb_cnt_mask;
298 /* Clean up old buffer. */
299 if (likely(elt->buf != NULL)) {
300 struct rte_mbuf *tmp = elt->buf;
304 memset(elt, 0x66, sizeof(*elt));
306 /* Faster than rte_pktmbuf_free(). */
308 struct rte_mbuf *next = tmp->next;
310 rte_pktmbuf_free_seg(tmp);
312 } while (tmp != NULL);
314 RTE_MBUF_PREFETCH_TO_FREE(elt_next->buf);
316 * Calculate the needed work queue entry size
319 wqe_real_size = sizeof(struct mlx4_wqe_ctrl_seg) +
320 buf->nb_segs * sizeof(struct mlx4_wqe_data_seg);
321 nr_txbbs = MLX4_SIZE_TO_TXBBS(wqe_real_size);
323 * Check that there is room for this WQE in the send
324 * queue and that the WQE size is legal.
326 if (((sq->head - sq->tail) + nr_txbbs +
327 sq->headroom_txbbs) >= sq->txbb_cnt ||
328 nr_txbbs > MLX4_MAX_WQE_TXBBS) {
332 /* Get the control and data entries of the WQE. */
333 ctrl = (struct mlx4_wqe_ctrl_seg *)
334 mlx4_get_send_wqe(sq, head_idx);
335 dseg = (struct mlx4_wqe_data_seg *)((uintptr_t)ctrl +
336 sizeof(struct mlx4_wqe_ctrl_seg));
337 /* Fill the data segments with buffer information. */
338 for (sbuf = buf; sbuf != NULL; sbuf = sbuf->next, dseg++) {
339 addr = rte_pktmbuf_mtod(sbuf, uintptr_t);
340 rte_prefetch0((volatile void *)addr);
341 /* Handle WQE wraparound. */
342 if (dseg >= (struct mlx4_wqe_data_seg *)sq->eob)
343 dseg = (struct mlx4_wqe_data_seg *)sq->buf;
344 dseg->addr = rte_cpu_to_be_64(addr);
345 /* Memory region key (big endian). */
346 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
347 dseg->lkey = rte_cpu_to_be_32(lkey);
349 if (unlikely(dseg->lkey ==
350 rte_cpu_to_be_32((uint32_t)-1))) {
351 /* MR does not exist. */
352 DEBUG("%p: unable to get MP <-> MR association",
355 * Restamp entry in case of failure.
356 * Make sure that size is written correctly
357 * Note that we give ownership to the SW,
360 ctrl->fence_size = (wqe_real_size >> 4) & 0x3f;
361 mlx4_txq_stamp_freed_wqe(sq, head_idx,
362 (sq->head & sq->txbb_cnt) ? 0 : 1);
367 if (likely(sbuf->data_len)) {
368 byte_count = rte_cpu_to_be_32(sbuf->data_len);
371 * Zero length segment is treated as inline
372 * segment with zero data.
374 byte_count = RTE_BE32(0x80000000);
377 * If the data segment is not at the beginning
378 * of a Tx basic block (TXBB) then write the
379 * byte count, else postpone the writing to
380 * just before updating the control segment.
382 if ((uintptr_t)dseg & (uintptr_t)(MLX4_TXBB_SIZE - 1)) {
384 * Need a barrier here before writing the
385 * byte_count fields to make sure that all the
386 * data is visible before the byte_count field
387 * is set. otherwise, if the segment begins a
388 * new cacheline, the HCA prefetcher could grab
389 * the 64-byte chunk and get a valid
390 * (!= 0xffffffff) byte count but stale data,
391 * and end up sending the wrong data.
394 dseg->byte_count = byte_count;
397 * This data segment starts at the beginning of
398 * a new TXBB, so we need to postpone its
399 * byte_count writing for later.
401 pv[pv_counter].dseg = dseg;
402 pv[pv_counter++].val = byte_count;
405 /* Write the first DWORD of each TXBB save earlier. */
407 /* Need a barrier before writing the byte_count. */
409 for (--pv_counter; pv_counter >= 0; pv_counter--)
410 pv[pv_counter].dseg->byte_count =
413 /* Fill the control parameters for this packet. */
414 ctrl->fence_size = (wqe_real_size >> 4) & 0x3f;
416 * For raw Ethernet, the SOLICIT flag is used to indicate
417 * that no ICRC should be calculated.
419 txq->elts_comp_cd -= nr_txbbs;
420 if (unlikely(txq->elts_comp_cd <= 0)) {
421 txq->elts_comp_cd = txq->elts_comp_cd_init;
422 srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT |
423 MLX4_WQE_CTRL_CQ_UPDATE);
425 srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT);
427 /* Enable HW checksum offload if requested */
430 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))) {
431 const uint64_t is_tunneled = (buf->ol_flags &
433 PKT_TX_TUNNEL_VXLAN));
435 if (is_tunneled && txq->csum_l2tun) {
436 owner_opcode |= MLX4_WQE_CTRL_IIP_HDR_CSUM |
437 MLX4_WQE_CTRL_IL4_HDR_CSUM;
438 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
440 RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM);
443 RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM |
444 MLX4_WQE_CTRL_TCP_UDP_CSUM);
449 * Copy destination MAC address to the WQE, this allows
450 * loopback in eSwitch, so that VFs and PF can
451 * communicate with each other.
453 srcrb.flags16[0] = *(rte_pktmbuf_mtod(buf, uint16_t *));
454 ctrl->imm = *(rte_pktmbuf_mtod_offset(buf, uint32_t *,
459 ctrl->srcrb_flags = srcrb.flags;
461 * Make sure descriptor is fully written before
462 * setting ownership bit (because HW can start
463 * executing as soon as we do).
466 ctrl->owner_opcode = rte_cpu_to_be_32(owner_opcode |
467 ((sq->head & sq->txbb_cnt) ?
468 MLX4_BIT_WQE_OWN : 0));
469 sq->head += nr_txbbs;
471 bytes_sent += buf->pkt_len;
472 elts_head = elts_head_next;
474 /* Take a shortcut if nothing must be sent. */
475 if (unlikely(i == 0))
477 /* Increment send statistics counters. */
478 txq->stats.opackets += i;
479 txq->stats.obytes += bytes_sent;
480 /* Make sure that descriptors are written before doorbell record. */
482 /* Ring QP doorbell. */
483 rte_write32(txq->msq.doorbell_qpn, txq->msq.db);
484 txq->elts_head = elts_head;
490 * Translate Rx completion flags to packet type.
493 * Rx completion flags returned by mlx4_cqe_flags().
496 * Packet type in mbuf format.
498 static inline uint32_t
499 rxq_cq_to_pkt_type(uint32_t flags)
503 if (flags & MLX4_CQE_L2_TUNNEL)
505 mlx4_transpose(flags,
506 MLX4_CQE_L2_TUNNEL_IPV4,
507 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN) |
508 mlx4_transpose(flags,
509 MLX4_CQE_STATUS_IPV4_PKT,
510 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN);
512 pkt_type = mlx4_transpose(flags,
513 MLX4_CQE_STATUS_IPV4_PKT,
514 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
519 * Translate Rx completion flags to offload flags.
522 * Rx completion flags returned by mlx4_cqe_flags().
524 * Whether Rx checksums are enabled.
526 * Whether Rx L2 tunnel checksums are enabled.
529 * Offload flags (ol_flags) in mbuf format.
531 static inline uint32_t
532 rxq_cq_to_ol_flags(uint32_t flags, int csum, int csum_l2tun)
534 uint32_t ol_flags = 0;
538 mlx4_transpose(flags,
539 MLX4_CQE_STATUS_IP_HDR_CSUM_OK,
540 PKT_RX_IP_CKSUM_GOOD) |
541 mlx4_transpose(flags,
542 MLX4_CQE_STATUS_TCP_UDP_CSUM_OK,
543 PKT_RX_L4_CKSUM_GOOD);
544 if ((flags & MLX4_CQE_L2_TUNNEL) && csum_l2tun)
546 mlx4_transpose(flags,
547 MLX4_CQE_L2_TUNNEL_IPOK,
548 PKT_RX_IP_CKSUM_GOOD) |
549 mlx4_transpose(flags,
550 MLX4_CQE_L2_TUNNEL_L4_CSUM,
551 PKT_RX_L4_CKSUM_GOOD);
556 * Extract checksum information from CQE flags.
559 * Pointer to CQE structure.
561 * Whether Rx checksums are enabled.
563 * Whether Rx L2 tunnel checksums are enabled.
566 * CQE checksum information.
568 static inline uint32_t
569 mlx4_cqe_flags(struct mlx4_cqe *cqe, int csum, int csum_l2tun)
574 * The relevant bits are in different locations on their
575 * CQE fields therefore we can join them in one 32bit
579 flags = (rte_be_to_cpu_32(cqe->status) &
580 MLX4_CQE_STATUS_IPV4_CSUM_OK);
582 flags |= (rte_be_to_cpu_32(cqe->vlan_my_qpn) &
583 (MLX4_CQE_L2_TUNNEL |
584 MLX4_CQE_L2_TUNNEL_IPOK |
585 MLX4_CQE_L2_TUNNEL_L4_CSUM |
586 MLX4_CQE_L2_TUNNEL_IPV4));
591 * Poll one CQE from CQ.
594 * Pointer to the receive queue structure.
599 * Number of bytes of the CQE, 0 in case there is no completion.
602 mlx4_cq_poll_one(struct rxq *rxq, struct mlx4_cqe **out)
605 struct mlx4_cqe *cqe = NULL;
606 struct mlx4_cq *cq = &rxq->mcq;
608 cqe = (struct mlx4_cqe *)mlx4_get_cqe(cq, cq->cons_index);
609 if (!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
610 !!(cq->cons_index & cq->cqe_cnt))
613 * Make sure we read CQ entry contents after we've checked the
617 assert(!(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK));
618 assert((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) !=
619 MLX4_CQE_OPCODE_ERROR);
620 ret = rte_be_to_cpu_32(cqe->byte_cnt);
628 * DPDK callback for Rx with scattered packets support.
631 * Generic pointer to Rx queue structure.
633 * Array to store received packets.
635 * Maximum number of packets in array.
638 * Number of packets successfully received (<= pkts_n).
641 mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
643 struct rxq *rxq = dpdk_rxq;
644 const uint32_t wr_cnt = (1 << rxq->elts_n) - 1;
645 const uint16_t sges_n = rxq->sges_n;
646 struct rte_mbuf *pkt = NULL;
647 struct rte_mbuf *seg = NULL;
649 uint32_t rq_ci = rxq->rq_ci << sges_n;
653 struct mlx4_cqe *cqe;
654 uint32_t idx = rq_ci & wr_cnt;
655 struct rte_mbuf *rep = (*rxq->elts)[idx];
656 volatile struct mlx4_wqe_data_seg *scat = &(*rxq->wqes)[idx];
658 /* Update the 'next' pointer of the previous segment. */
664 rep = rte_mbuf_raw_alloc(rxq->mp);
665 if (unlikely(rep == NULL)) {
666 ++rxq->stats.rx_nombuf;
669 * No buffers before we even started,
675 assert(pkt != (*rxq->elts)[idx]);
679 rte_mbuf_raw_free(pkt);
685 /* Looking for the new packet. */
686 len = mlx4_cq_poll_one(rxq, &cqe);
688 rte_mbuf_raw_free(rep);
691 if (unlikely(len < 0)) {
692 /* Rx error, packet is likely too large. */
693 rte_mbuf_raw_free(rep);
694 ++rxq->stats.idropped;
698 if (rxq->csum | rxq->csum_l2tun) {
705 rxq_cq_to_ol_flags(flags,
708 pkt->packet_type = rxq_cq_to_pkt_type(flags);
710 pkt->packet_type = 0;
716 rep->port = rxq->port_id;
717 rep->data_len = seg->data_len;
718 rep->data_off = seg->data_off;
719 (*rxq->elts)[idx] = rep;
721 * Fill NIC descriptor with the new buffer. The lkey and size
722 * of the buffers are already known, only the buffer address
725 scat->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
726 if (len > seg->data_len) {
727 len -= seg->data_len;
732 /* The last segment. */
734 /* Increment bytes counter. */
735 rxq->stats.ibytes += pkt->pkt_len;
742 /* Align consumer index to the next stride. */
747 if (unlikely(i == 0 && (rq_ci >> sges_n) == rxq->rq_ci))
749 /* Update the consumer index. */
750 rxq->rq_ci = rq_ci >> sges_n;
752 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
753 *rxq->mcq.set_ci_db =
754 rte_cpu_to_be_32(rxq->mcq.cons_index & MLX4_CQ_DB_CI_MASK);
755 /* Increment packets counter. */
756 rxq->stats.ipackets += i;
761 * Dummy DPDK callback for Tx.
763 * This function is used to temporarily replace the real callback during
764 * unsafe control operations on the queue, or in case of error.
767 * Generic pointer to Tx queue structure.
769 * Packets to transmit.
771 * Number of packets in array.
774 * Number of packets successfully transmitted (<= pkts_n).
777 mlx4_tx_burst_removed(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
786 * Dummy DPDK callback for Rx.
788 * This function is used to temporarily replace the real callback during
789 * unsafe control operations on the queue, or in case of error.
792 * Generic pointer to Rx queue structure.
794 * Array to store received packets.
796 * Maximum number of packets in array.
799 * Number of packets successfully received (<= pkts_n).
802 mlx4_rx_burst_removed(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)