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5 * Copyright 2017 Mellanox
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36 * Data plane functions for mlx4 driver.
43 /* Verbs headers do not support -pedantic. */
45 #pragma GCC diagnostic ignored "-Wpedantic"
47 #include <infiniband/verbs.h>
49 #pragma GCC diagnostic error "-Wpedantic"
52 #include <rte_branch_prediction.h>
53 #include <rte_common.h>
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
61 #include "mlx4_rxtx.h"
62 #include "mlx4_utils.h"
64 #define WQE_ONE_DATA_SEG_SIZE \
65 (sizeof(struct mlx4_wqe_ctrl_seg) + sizeof(struct mlx4_wqe_data_seg))
68 * Pointer-value pair structure used in tx_post_send for saving the first
69 * DWORD (32 byte) of a TXBB.
72 struct mlx4_wqe_data_seg *dseg;
77 * Stamp a WQE so it won't be reused by the HW.
79 * Routine is used when freeing WQE used by the chip or when failing
80 * building an WQ entry has failed leaving partial information on the queue.
83 * Pointer to the SQ structure.
85 * Index of the freed WQE.
87 * Number of blocks to stamp.
88 * If < 0 the routine will use the size written in the WQ entry.
90 * The value of the WQE owner bit to use in the stamp.
93 * The number of Tx basic blocs (TXBB) the WQE contained.
96 mlx4_txq_stamp_freed_wqe(struct mlx4_sq *sq, uint16_t index, uint8_t owner)
98 uint32_t stamp = rte_cpu_to_be_32(MLX4_SQ_STAMP_VAL |
99 (!!owner << MLX4_SQ_STAMP_SHIFT));
100 uint8_t *wqe = mlx4_get_send_wqe(sq, (index & sq->txbb_cnt_mask));
101 uint32_t *ptr = (uint32_t *)wqe;
106 /* Extract the size from the control segment of the WQE. */
107 num_txbbs = MLX4_SIZE_TO_TXBBS((((struct mlx4_wqe_ctrl_seg *)
108 wqe)->fence_size & 0x3f) << 4);
109 txbbs_size = num_txbbs * MLX4_TXBB_SIZE;
110 /* Optimize the common case when there is no wrap-around. */
111 if (wqe + txbbs_size <= sq->eob) {
112 /* Stamp the freed descriptor. */
113 for (i = 0; i < txbbs_size; i += MLX4_SQ_STAMP_STRIDE) {
115 ptr += MLX4_SQ_STAMP_DWORDS;
118 /* Stamp the freed descriptor. */
119 for (i = 0; i < txbbs_size; i += MLX4_SQ_STAMP_STRIDE) {
121 ptr += MLX4_SQ_STAMP_DWORDS;
122 if ((uint8_t *)ptr >= sq->eob) {
123 ptr = (uint32_t *)sq->buf;
124 stamp ^= RTE_BE32(0x80000000);
132 * Manage Tx completions.
134 * When sending a burst, mlx4_tx_burst() posts several WRs.
135 * To improve performance, a completion event is only required once every
136 * MLX4_PMD_TX_PER_COMP_REQ sends. Doing so discards completion information
137 * for other WRs, but this information would not be used anyway.
140 * Pointer to Tx queue structure.
143 * 0 on success, -1 on failure.
146 mlx4_txq_complete(struct txq *txq, const unsigned int elts_n,
149 unsigned int elts_comp = txq->elts_comp;
150 unsigned int elts_tail = txq->elts_tail;
151 struct mlx4_cq *cq = &txq->mcq;
152 struct mlx4_cqe *cqe;
153 uint32_t cons_index = cq->cons_index;
155 uint16_t nr_txbbs = 0;
159 * Traverse over all CQ entries reported and handle each WQ entry
163 cqe = (struct mlx4_cqe *)mlx4_get_cqe(cq, cons_index);
164 if (unlikely(!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
165 !!(cons_index & cq->cqe_cnt)))
168 * Make sure we read the CQE after we read the ownership bit.
172 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
173 MLX4_CQE_OPCODE_ERROR)) {
174 struct mlx4_err_cqe *cqe_err =
175 (struct mlx4_err_cqe *)cqe;
176 ERROR("%p CQE error - vendor syndrome: 0x%x"
178 (void *)txq, cqe_err->vendor_err,
182 /* Get WQE index reported in the CQE. */
184 rte_be_to_cpu_16(cqe->wqe_index) & sq->txbb_cnt_mask;
186 /* Free next descriptor. */
188 mlx4_txq_stamp_freed_wqe(sq,
189 (sq->tail + nr_txbbs) & sq->txbb_cnt_mask,
190 !!((sq->tail + nr_txbbs) & sq->txbb_cnt));
192 } while (((sq->tail + nr_txbbs) & sq->txbb_cnt_mask) !=
196 if (unlikely(pkts == 0))
200 * To prevent CQ overflow we first update CQ consumer and only then
203 cq->cons_index = cons_index;
204 *cq->set_ci_db = rte_cpu_to_be_32(cq->cons_index & MLX4_CQ_DB_CI_MASK);
206 sq->tail = sq->tail + nr_txbbs;
207 /* Update the list of packets posted for transmission. */
209 assert(elts_comp <= txq->elts_comp);
211 * Assume completion status is successful as nothing can be done about
215 if (elts_tail >= elts_n)
217 txq->elts_tail = elts_tail;
218 txq->elts_comp = elts_comp;
223 * Get memory pool (MP) from mbuf. If mbuf is indirect, the pool from which
224 * the cloned mbuf is allocated is returned instead.
230 * Memory pool where data is located for given mbuf.
232 static struct rte_mempool *
233 mlx4_txq_mb2mp(struct rte_mbuf *buf)
235 if (unlikely(RTE_MBUF_INDIRECT(buf)))
236 return rte_mbuf_from_indirect(buf)->pool;
241 mlx4_tx_burst_segs(struct rte_mbuf *buf, struct txq *txq,
242 struct mlx4_wqe_ctrl_seg **pctrl)
246 struct pv *pv = (struct pv *)txq->bounce_buf;
247 struct mlx4_sq *sq = &txq->msq;
248 uint32_t head_idx = sq->head & sq->txbb_cnt_mask;
249 struct mlx4_wqe_ctrl_seg *ctrl;
250 struct mlx4_wqe_data_seg *dseg;
251 struct rte_mbuf *sbuf;
257 /* Calculate the needed work queue entry size for this packet. */
258 wqe_real_size = sizeof(struct mlx4_wqe_ctrl_seg) +
259 buf->nb_segs * sizeof(struct mlx4_wqe_data_seg);
260 nr_txbbs = MLX4_SIZE_TO_TXBBS(wqe_real_size);
262 * Check that there is room for this WQE in the send queue and that
263 * the WQE size is legal.
265 if (((sq->head - sq->tail) + nr_txbbs +
266 sq->headroom_txbbs) >= sq->txbb_cnt ||
267 nr_txbbs > MLX4_MAX_WQE_TXBBS) {
270 /* Get the control and data entries of the WQE. */
271 ctrl = (struct mlx4_wqe_ctrl_seg *)mlx4_get_send_wqe(sq, head_idx);
272 dseg = (struct mlx4_wqe_data_seg *)((uintptr_t)ctrl +
273 sizeof(struct mlx4_wqe_ctrl_seg));
275 /* Fill the data segments with buffer information. */
276 for (sbuf = buf; sbuf != NULL; sbuf = sbuf->next, dseg++) {
277 addr = rte_pktmbuf_mtod(sbuf, uintptr_t);
278 rte_prefetch0((volatile void *)addr);
279 /* Handle WQE wraparound. */
280 if (dseg >= (struct mlx4_wqe_data_seg *)sq->eob)
281 dseg = (struct mlx4_wqe_data_seg *)sq->buf;
282 dseg->addr = rte_cpu_to_be_64(addr);
283 /* Memory region key (big endian) for this memory pool. */
284 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(sbuf));
285 dseg->lkey = rte_cpu_to_be_32(lkey);
287 /* Calculate the needed work queue entry size for this packet */
288 if (unlikely(dseg->lkey == rte_cpu_to_be_32((uint32_t)-1))) {
289 /* MR does not exist. */
290 DEBUG("%p: unable to get MP <-> MR association",
293 * Restamp entry in case of failure.
294 * Make sure that size is written correctly
295 * Note that we give ownership to the SW, not the HW.
297 wqe_real_size = sizeof(struct mlx4_wqe_ctrl_seg) +
298 buf->nb_segs * sizeof(struct mlx4_wqe_data_seg);
299 ctrl->fence_size = (wqe_real_size >> 4) & 0x3f;
300 mlx4_txq_stamp_freed_wqe(sq, head_idx,
301 (sq->head & sq->txbb_cnt) ? 0 : 1);
305 if (likely(sbuf->data_len)) {
306 byte_count = rte_cpu_to_be_32(sbuf->data_len);
309 * Zero length segment is treated as inline segment
312 byte_count = RTE_BE32(0x80000000);
315 * If the data segment is not at the beginning of a
316 * Tx basic block (TXBB) then write the byte count,
317 * else postpone the writing to just before updating the
320 if ((uintptr_t)dseg & (uintptr_t)(MLX4_TXBB_SIZE - 1)) {
322 * Need a barrier here before writing the byte_count
323 * fields to make sure that all the data is visible
324 * before the byte_count field is set.
325 * Otherwise, if the segment begins a new cacheline,
326 * the HCA prefetcher could grab the 64-byte chunk and
327 * get a valid (!= 0xffffffff) byte count but stale
328 * data, and end up sending the wrong data.
331 dseg->byte_count = byte_count;
334 * This data segment starts at the beginning of a new
335 * TXBB, so we need to postpone its byte_count writing
338 pv[pv_counter].dseg = dseg;
339 pv[pv_counter++].val = byte_count;
342 /* Write the first DWORD of each TXBB save earlier. */
344 /* Need a barrier here before writing the byte_count. */
346 for (--pv_counter; pv_counter >= 0; pv_counter--)
347 pv[pv_counter].dseg->byte_count = pv[pv_counter].val;
349 /* Fill the control parameters for this packet. */
350 ctrl->fence_size = (wqe_real_size >> 4) & 0x3f;
355 * DPDK callback for Tx.
358 * Generic pointer to Tx queue structure.
360 * Packets to transmit.
362 * Number of packets in array.
365 * Number of packets successfully transmitted (<= pkts_n).
368 mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
370 struct txq *txq = (struct txq *)dpdk_txq;
371 unsigned int elts_head = txq->elts_head;
372 const unsigned int elts_n = txq->elts_n;
373 unsigned int bytes_sent = 0;
376 struct mlx4_sq *sq = &txq->msq;
379 assert(txq->elts_comp_cd != 0);
380 if (likely(txq->elts_comp != 0))
381 mlx4_txq_complete(txq, elts_n, sq);
382 max = (elts_n - (elts_head - txq->elts_tail));
386 assert(max <= elts_n);
387 /* Always leave one free entry in the ring. */
391 for (i = 0; (i != max); ++i) {
392 struct rte_mbuf *buf = pkts[i];
393 unsigned int elts_head_next =
394 (((elts_head + 1) == elts_n) ? 0 : elts_head + 1);
395 struct txq_elt *elt_next = &(*txq->elts)[elts_head_next];
396 struct txq_elt *elt = &(*txq->elts)[elts_head];
397 uint32_t owner_opcode = MLX4_OPCODE_SEND;
398 struct mlx4_wqe_ctrl_seg *ctrl;
399 struct mlx4_wqe_data_seg *dseg;
404 uint32_t head_idx = sq->head & sq->txbb_cnt_mask;
408 /* Clean up old buffer. */
409 if (likely(elt->buf != NULL)) {
410 struct rte_mbuf *tmp = elt->buf;
414 memset(elt, 0x66, sizeof(*elt));
416 /* Faster than rte_pktmbuf_free(). */
418 struct rte_mbuf *next = tmp->next;
420 rte_pktmbuf_free_seg(tmp);
422 } while (tmp != NULL);
424 RTE_MBUF_PREFETCH_TO_FREE(elt_next->buf);
425 if (buf->nb_segs == 1) {
427 * Check that there is room for this WQE in the send
428 * queue and that the WQE size is legal
430 if (((sq->head - sq->tail) + 1 + sq->headroom_txbbs) >=
431 sq->txbb_cnt || 1 > MLX4_MAX_WQE_TXBBS) {
435 /* Get the control and data entries of the WQE. */
436 ctrl = (struct mlx4_wqe_ctrl_seg *)
437 mlx4_get_send_wqe(sq, head_idx);
438 dseg = (struct mlx4_wqe_data_seg *)((uintptr_t)ctrl +
439 sizeof(struct mlx4_wqe_ctrl_seg));
440 addr = rte_pktmbuf_mtod(buf, uintptr_t);
441 rte_prefetch0((volatile void *)addr);
442 /* Handle WQE wraparound. */
443 if (dseg >= (struct mlx4_wqe_data_seg *)sq->eob)
444 dseg = (struct mlx4_wqe_data_seg *)sq->buf;
445 dseg->addr = rte_cpu_to_be_64(addr);
446 /* Memory region key (big endian). */
447 lkey = mlx4_txq_mp2mr(txq, mlx4_txq_mb2mp(buf));
448 dseg->lkey = rte_cpu_to_be_32(lkey);
450 if (unlikely(dseg->lkey ==
451 rte_cpu_to_be_32((uint32_t)-1))) {
452 /* MR does not exist. */
453 DEBUG("%p: unable to get MP <-> MR association",
456 * Restamp entry in case of failure.
457 * Make sure that size is written correctly
458 * Note that we give ownership to the SW,
462 (WQE_ONE_DATA_SEG_SIZE >> 4) & 0x3f;
463 mlx4_txq_stamp_freed_wqe(sq, head_idx,
464 (sq->head & sq->txbb_cnt) ? 0 : 1);
469 /* Need a barrier here before byte count store. */
471 dseg->byte_count = rte_cpu_to_be_32(buf->data_len);
472 /* Fill the control parameters for this packet. */
473 ctrl->fence_size = (WQE_ONE_DATA_SEG_SIZE >> 4) & 0x3f;
476 nr_txbbs = mlx4_tx_burst_segs(buf, txq, &ctrl);
483 * For raw Ethernet, the SOLICIT flag is used to indicate
484 * that no ICRC should be calculated.
486 txq->elts_comp_cd -= nr_txbbs;
487 if (unlikely(txq->elts_comp_cd <= 0)) {
488 txq->elts_comp_cd = txq->elts_comp_cd_init;
489 srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT |
490 MLX4_WQE_CTRL_CQ_UPDATE);
492 srcrb.flags = RTE_BE32(MLX4_WQE_CTRL_SOLICIT);
494 /* Enable HW checksum offload if requested */
497 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))) {
498 const uint64_t is_tunneled = (buf->ol_flags &
500 PKT_TX_TUNNEL_VXLAN));
502 if (is_tunneled && txq->csum_l2tun) {
503 owner_opcode |= MLX4_WQE_CTRL_IIP_HDR_CSUM |
504 MLX4_WQE_CTRL_IL4_HDR_CSUM;
505 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
507 RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM);
510 RTE_BE32(MLX4_WQE_CTRL_IP_HDR_CSUM |
511 MLX4_WQE_CTRL_TCP_UDP_CSUM);
516 * Copy destination MAC address to the WQE, this allows
517 * loopback in eSwitch, so that VFs and PF can
518 * communicate with each other.
520 srcrb.flags16[0] = *(rte_pktmbuf_mtod(buf, uint16_t *));
521 ctrl->imm = *(rte_pktmbuf_mtod_offset(buf, uint32_t *,
526 ctrl->srcrb_flags = srcrb.flags;
528 * Make sure descriptor is fully written before
529 * setting ownership bit (because HW can start
530 * executing as soon as we do).
533 ctrl->owner_opcode = rte_cpu_to_be_32(owner_opcode |
534 ((sq->head & sq->txbb_cnt) ?
535 MLX4_BIT_WQE_OWN : 0));
536 sq->head += nr_txbbs;
538 bytes_sent += buf->pkt_len;
539 elts_head = elts_head_next;
541 /* Take a shortcut if nothing must be sent. */
542 if (unlikely(i == 0))
544 /* Increment send statistics counters. */
545 txq->stats.opackets += i;
546 txq->stats.obytes += bytes_sent;
547 /* Make sure that descriptors are written before doorbell record. */
549 /* Ring QP doorbell. */
550 rte_write32(txq->msq.doorbell_qpn, txq->msq.db);
551 txq->elts_head = elts_head;
557 * Translate Rx completion flags to packet type.
560 * Rx completion flags returned by mlx4_cqe_flags().
563 * Packet type in mbuf format.
565 static inline uint32_t
566 rxq_cq_to_pkt_type(uint32_t flags)
570 if (flags & MLX4_CQE_L2_TUNNEL)
572 mlx4_transpose(flags,
573 MLX4_CQE_L2_TUNNEL_IPV4,
574 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN) |
575 mlx4_transpose(flags,
576 MLX4_CQE_STATUS_IPV4_PKT,
577 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN);
579 pkt_type = mlx4_transpose(flags,
580 MLX4_CQE_STATUS_IPV4_PKT,
581 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
586 * Translate Rx completion flags to offload flags.
589 * Rx completion flags returned by mlx4_cqe_flags().
591 * Whether Rx checksums are enabled.
593 * Whether Rx L2 tunnel checksums are enabled.
596 * Offload flags (ol_flags) in mbuf format.
598 static inline uint32_t
599 rxq_cq_to_ol_flags(uint32_t flags, int csum, int csum_l2tun)
601 uint32_t ol_flags = 0;
605 mlx4_transpose(flags,
606 MLX4_CQE_STATUS_IP_HDR_CSUM_OK,
607 PKT_RX_IP_CKSUM_GOOD) |
608 mlx4_transpose(flags,
609 MLX4_CQE_STATUS_TCP_UDP_CSUM_OK,
610 PKT_RX_L4_CKSUM_GOOD);
611 if ((flags & MLX4_CQE_L2_TUNNEL) && csum_l2tun)
613 mlx4_transpose(flags,
614 MLX4_CQE_L2_TUNNEL_IPOK,
615 PKT_RX_IP_CKSUM_GOOD) |
616 mlx4_transpose(flags,
617 MLX4_CQE_L2_TUNNEL_L4_CSUM,
618 PKT_RX_L4_CKSUM_GOOD);
623 * Extract checksum information from CQE flags.
626 * Pointer to CQE structure.
628 * Whether Rx checksums are enabled.
630 * Whether Rx L2 tunnel checksums are enabled.
633 * CQE checksum information.
635 static inline uint32_t
636 mlx4_cqe_flags(struct mlx4_cqe *cqe, int csum, int csum_l2tun)
641 * The relevant bits are in different locations on their
642 * CQE fields therefore we can join them in one 32bit
646 flags = (rte_be_to_cpu_32(cqe->status) &
647 MLX4_CQE_STATUS_IPV4_CSUM_OK);
649 flags |= (rte_be_to_cpu_32(cqe->vlan_my_qpn) &
650 (MLX4_CQE_L2_TUNNEL |
651 MLX4_CQE_L2_TUNNEL_IPOK |
652 MLX4_CQE_L2_TUNNEL_L4_CSUM |
653 MLX4_CQE_L2_TUNNEL_IPV4));
658 * Poll one CQE from CQ.
661 * Pointer to the receive queue structure.
666 * Number of bytes of the CQE, 0 in case there is no completion.
669 mlx4_cq_poll_one(struct rxq *rxq, struct mlx4_cqe **out)
672 struct mlx4_cqe *cqe = NULL;
673 struct mlx4_cq *cq = &rxq->mcq;
675 cqe = (struct mlx4_cqe *)mlx4_get_cqe(cq, cq->cons_index);
676 if (!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
677 !!(cq->cons_index & cq->cqe_cnt))
680 * Make sure we read CQ entry contents after we've checked the
684 assert(!(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK));
685 assert((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) !=
686 MLX4_CQE_OPCODE_ERROR);
687 ret = rte_be_to_cpu_32(cqe->byte_cnt);
695 * DPDK callback for Rx with scattered packets support.
698 * Generic pointer to Rx queue structure.
700 * Array to store received packets.
702 * Maximum number of packets in array.
705 * Number of packets successfully received (<= pkts_n).
708 mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
710 struct rxq *rxq = dpdk_rxq;
711 const uint32_t wr_cnt = (1 << rxq->elts_n) - 1;
712 const uint16_t sges_n = rxq->sges_n;
713 struct rte_mbuf *pkt = NULL;
714 struct rte_mbuf *seg = NULL;
716 uint32_t rq_ci = rxq->rq_ci << sges_n;
720 struct mlx4_cqe *cqe;
721 uint32_t idx = rq_ci & wr_cnt;
722 struct rte_mbuf *rep = (*rxq->elts)[idx];
723 volatile struct mlx4_wqe_data_seg *scat = &(*rxq->wqes)[idx];
725 /* Update the 'next' pointer of the previous segment. */
731 rep = rte_mbuf_raw_alloc(rxq->mp);
732 if (unlikely(rep == NULL)) {
733 ++rxq->stats.rx_nombuf;
736 * No buffers before we even started,
742 assert(pkt != (*rxq->elts)[idx]);
746 rte_mbuf_raw_free(pkt);
752 /* Looking for the new packet. */
753 len = mlx4_cq_poll_one(rxq, &cqe);
755 rte_mbuf_raw_free(rep);
758 if (unlikely(len < 0)) {
759 /* Rx error, packet is likely too large. */
760 rte_mbuf_raw_free(rep);
761 ++rxq->stats.idropped;
765 if (rxq->csum | rxq->csum_l2tun) {
772 rxq_cq_to_ol_flags(flags,
775 pkt->packet_type = rxq_cq_to_pkt_type(flags);
777 pkt->packet_type = 0;
783 rep->port = rxq->port_id;
784 rep->data_len = seg->data_len;
785 rep->data_off = seg->data_off;
786 (*rxq->elts)[idx] = rep;
788 * Fill NIC descriptor with the new buffer. The lkey and size
789 * of the buffers are already known, only the buffer address
792 scat->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
793 if (len > seg->data_len) {
794 len -= seg->data_len;
799 /* The last segment. */
801 /* Increment bytes counter. */
802 rxq->stats.ibytes += pkt->pkt_len;
809 /* Align consumer index to the next stride. */
814 if (unlikely(i == 0 && (rq_ci >> sges_n) == rxq->rq_ci))
816 /* Update the consumer index. */
817 rxq->rq_ci = rq_ci >> sges_n;
819 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
820 *rxq->mcq.set_ci_db =
821 rte_cpu_to_be_32(rxq->mcq.cons_index & MLX4_CQ_DB_CI_MASK);
822 /* Increment packets counter. */
823 rxq->stats.ipackets += i;
828 * Dummy DPDK callback for Tx.
830 * This function is used to temporarily replace the real callback during
831 * unsafe control operations on the queue, or in case of error.
834 * Generic pointer to Tx queue structure.
836 * Packets to transmit.
838 * Number of packets in array.
841 * Number of packets successfully transmitted (<= pkts_n).
844 mlx4_tx_burst_removed(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
853 * Dummy DPDK callback for Rx.
855 * This function is used to temporarily replace the real callback during
856 * unsafe control operations on the queue, or in case of error.
859 * Generic pointer to Rx queue structure.
861 * Array to store received packets.
863 * Maximum number of packets in array.
866 * Number of packets successfully received (<= pkts_n).
869 mlx4_rx_burst_removed(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)