1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2017 6WIND S.A.
3 * Copyright 2017 Mellanox
10 #include <sys/queue.h>
12 /* Verbs headers do not support -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/mlx4dv.h>
17 #include <infiniband/verbs.h>
19 #pragma GCC diagnostic error "-Wpedantic"
22 #include <rte_ethdev_driver.h>
24 #include <rte_mempool.h>
29 /** Rx queue counters. */
30 struct mlx4_rxq_stats {
31 unsigned int idx; /**< Mapping index. */
32 uint64_t ipackets; /**< Total of successfully received packets. */
33 uint64_t ibytes; /**< Total of successfully received bytes. */
34 uint64_t idropped; /**< Total of packets dropped when Rx ring full. */
35 uint64_t rx_nombuf; /**< Total of Rx mbuf allocation failures. */
38 /** Rx queue descriptor. */
40 struct priv *priv; /**< Back pointer to private data. */
41 struct rte_mempool *mp; /**< Memory pool for allocations. */
42 struct mlx4_mr *mr; /**< Memory region. */
43 struct ibv_cq *cq; /**< Completion queue. */
44 struct ibv_wq *wq; /**< Work queue. */
45 struct ibv_comp_channel *channel; /**< Rx completion channel. */
46 uint16_t rq_ci; /**< Saved RQ consumer index. */
47 uint16_t port_id; /**< Port ID for incoming packets. */
48 uint16_t sges_n; /**< Number of segments per packet (log2 value). */
49 uint16_t elts_n; /**< Mbuf queue size (log2 value). */
50 struct rte_mbuf *(*elts)[]; /**< Rx elements. */
51 volatile struct mlx4_wqe_data_seg (*wqes)[]; /**< HW queue entries. */
52 volatile uint32_t *rq_db; /**< RQ doorbell record. */
53 uint32_t csum:1; /**< Enable checksum offloading. */
54 uint32_t csum_l2tun:1; /**< Same for L2 tunnels. */
55 uint32_t l2tun_offload:1; /**< L2 tunnel offload is enabled. */
56 struct mlx4_cq mcq; /**< Info for directly manipulating the CQ. */
57 struct mlx4_rxq_stats stats; /**< Rx queue counters. */
58 unsigned int socket; /**< CPU socket ID for allocations. */
59 uint32_t usecnt; /**< Number of users relying on queue resources. */
60 uint8_t data[]; /**< Remaining queue resources. */
63 /** Shared flow target for Rx queues. */
65 LIST_ENTRY(mlx4_rss) next; /**< Next entry in list. */
66 struct priv *priv; /**< Back pointer to private data. */
67 uint32_t refcnt; /**< Reference count for this object. */
68 uint32_t usecnt; /**< Number of users relying on @p qp and @p ind. */
69 struct ibv_qp *qp; /**< Queue pair. */
70 struct ibv_rwq_ind_table *ind; /**< Indirection table. */
71 uint64_t fields; /**< Fields for RSS processing (Verbs format). */
72 uint8_t key[MLX4_RSS_HASH_KEY_SIZE]; /**< Hash key to use. */
73 uint16_t queues; /**< Number of target queues. */
74 uint16_t queue_id[]; /**< Target queues. */
79 struct rte_mbuf *buf; /**< Buffer. */
81 volatile struct mlx4_wqe_ctrl_seg *wqe; /**< SQ WQE. */
82 volatile uint32_t *eocb; /**< End of completion burst. */
86 /** Rx queue counters. */
87 struct mlx4_txq_stats {
88 unsigned int idx; /**< Mapping index. */
89 uint64_t opackets; /**< Total of successfully sent packets. */
90 uint64_t obytes; /**< Total of successfully sent bytes. */
91 uint64_t odropped; /**< Total of packets not sent when Tx ring full. */
94 /** Tx queue descriptor. */
96 struct mlx4_sq msq; /**< Info for directly manipulating the SQ. */
97 struct mlx4_cq mcq; /**< Info for directly manipulating the CQ. */
98 unsigned int elts_head; /**< Current index in (*elts)[]. */
99 unsigned int elts_tail; /**< First element awaiting completion. */
100 int elts_comp_cd; /**< Countdown for next completion. */
101 unsigned int elts_comp_cd_init; /**< Initial value for countdown. */
102 unsigned int elts_n; /**< (*elts)[] length. */
103 struct txq_elt (*elts)[]; /**< Tx elements. */
104 struct mlx4_txq_stats stats; /**< Tx queue counters. */
105 uint32_t max_inline; /**< Max inline send size. */
106 uint32_t csum:1; /**< Enable checksum offloading. */
107 uint32_t csum_l2tun:1; /**< Same for L2 tunnels. */
108 uint32_t lb:1; /**< Whether packets should be looped back by eSwitch. */
110 /**< Memory used for storing the first DWORD of data TXBBs. */
112 const struct rte_mempool *mp; /**< Cached memory pool. */
113 struct mlx4_mr *mr; /**< Memory region (for mp). */
114 uint32_t lkey; /**< mr->lkey copy. */
115 } mp2mr[MLX4_PMD_TX_MP_CACHE]; /**< MP to MR translation table. */
116 struct priv *priv; /**< Back pointer to private data. */
117 unsigned int socket; /**< CPU socket ID for allocations. */
118 struct ibv_cq *cq; /**< Completion queue. */
119 struct ibv_qp *qp; /**< Queue pair. */
120 uint8_t data[]; /**< Remaining queue resources. */
125 uint8_t mlx4_rss_hash_key_default[MLX4_RSS_HASH_KEY_SIZE];
126 int mlx4_rss_init(struct priv *priv);
127 void mlx4_rss_deinit(struct priv *priv);
128 struct mlx4_rss *mlx4_rss_get(struct priv *priv, uint64_t fields,
129 uint8_t key[MLX4_RSS_HASH_KEY_SIZE],
130 uint16_t queues, const uint16_t queue_id[]);
131 void mlx4_rss_put(struct mlx4_rss *rss);
132 int mlx4_rss_attach(struct mlx4_rss *rss);
133 void mlx4_rss_detach(struct mlx4_rss *rss);
134 int mlx4_rxq_attach(struct rxq *rxq);
135 void mlx4_rxq_detach(struct rxq *rxq);
136 uint64_t mlx4_get_rx_port_offloads(struct priv *priv);
137 uint64_t mlx4_get_rx_queue_offloads(struct priv *priv);
138 int mlx4_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
139 uint16_t desc, unsigned int socket,
140 const struct rte_eth_rxconf *conf,
141 struct rte_mempool *mp);
142 void mlx4_rx_queue_release(void *dpdk_rxq);
146 uint16_t mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
148 uint16_t mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
150 uint16_t mlx4_tx_burst_removed(void *dpdk_txq, struct rte_mbuf **pkts,
152 uint16_t mlx4_rx_burst_removed(void *dpdk_rxq, struct rte_mbuf **pkts,
157 uint64_t mlx4_get_tx_port_offloads(struct priv *priv);
158 int mlx4_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
159 uint16_t desc, unsigned int socket,
160 const struct rte_eth_txconf *conf);
161 void mlx4_tx_queue_release(void *dpdk_txq);
164 * Get memory region (MR) <-> memory pool (MP) association from txq->mp2mr[].
165 * Call mlx4_txq_add_mr() if MP is not registered yet.
168 * Pointer to Tx queue structure.
170 * Memory pool for which a memory region lkey must be returned.
173 * mr->lkey on success, (uint32_t)-1 on failure.
175 static inline uint32_t
176 mlx4_txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
180 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
181 if (unlikely(txq->mp2mr[i].mp == NULL)) {
182 /* Unknown MP, add a new MR for it. */
185 if (txq->mp2mr[i].mp == mp) {
187 return txq->mp2mr[i].lkey;
190 return mlx4_txq_add_mr(txq, mp, i);
193 #endif /* MLX4_RXTX_H_ */