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5 * Copyright 2017 Mellanox
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39 /* Verbs headers do not support -pedantic. */
41 #pragma GCC diagnostic ignored "-Wpedantic"
43 #include <infiniband/verbs.h>
45 #pragma GCC diagnostic error "-Wpedantic"
48 #include <rte_ethdev.h>
50 #include <rte_mempool.h>
54 /** Rx queue counters. */
55 struct mlx4_rxq_stats {
56 unsigned int idx; /**< Mapping index. */
57 uint64_t ipackets; /**< Total of successfully received packets. */
58 uint64_t ibytes; /**< Total of successfully received bytes. */
59 uint64_t idropped; /**< Total of packets dropped when Rx ring full. */
60 uint64_t rx_nombuf; /**< Total of Rx mbuf allocation failures. */
65 struct ibv_recv_wr wr; /**< Work request. */
66 struct ibv_sge sge; /**< Scatter/gather element. */
67 struct rte_mbuf *buf; /**< Buffer. */
70 /** Rx queue descriptor. */
72 struct priv *priv; /**< Back pointer to private data. */
73 struct rte_mempool *mp; /**< Memory pool for allocations. */
74 struct ibv_mr *mr; /**< Memory region (for mp). */
75 struct ibv_cq *cq; /**< Completion queue. */
76 struct ibv_qp *qp; /**< Queue pair. */
77 struct ibv_comp_channel *channel; /**< Rx completion channel. */
78 unsigned int port_id; /**< Port ID for incoming packets. */
79 unsigned int elts_n; /**< (*elts)[] length. */
80 unsigned int elts_head; /**< Current index in (*elts)[]. */
81 struct rxq_elt (*elts)[]; /**< Rx elements. */
82 struct mlx4_rxq_stats stats; /**< Rx queue counters. */
83 unsigned int socket; /**< CPU socket ID for allocations. */
88 struct ibv_send_wr wr; /* Work request. */
89 struct ibv_sge sge; /* Scatter/gather element. */
90 struct rte_mbuf *buf; /**< Buffer. */
93 /** Rx queue counters. */
94 struct mlx4_txq_stats {
95 unsigned int idx; /**< Mapping index. */
96 uint64_t opackets; /**< Total of successfully sent packets. */
97 uint64_t obytes; /**< Total of successfully sent bytes. */
98 uint64_t odropped; /**< Total of packets not sent when Tx ring full. */
101 /** Tx queue descriptor. */
103 struct priv *priv; /**< Back pointer to private data. */
105 const struct rte_mempool *mp; /**< Cached memory pool. */
106 struct ibv_mr *mr; /**< Memory region (for mp). */
107 uint32_t lkey; /**< mr->lkey copy. */
108 } mp2mr[MLX4_PMD_TX_MP_CACHE]; /**< MP to MR translation table. */
109 struct ibv_cq *cq; /**< Completion queue. */
110 struct ibv_qp *qp; /**< Queue pair. */
111 uint32_t max_inline; /**< Max inline send size. */
112 unsigned int elts_n; /**< (*elts)[] length. */
113 struct txq_elt (*elts)[]; /**< Tx elements. */
114 unsigned int elts_head; /**< Current index in (*elts)[]. */
115 unsigned int elts_tail; /**< First element awaiting completion. */
116 unsigned int elts_comp; /**< Number of completion requests. */
117 unsigned int elts_comp_cd; /**< Countdown for next completion. */
118 unsigned int elts_comp_cd_init; /**< Initial value for countdown. */
119 struct mlx4_txq_stats stats; /**< Tx queue counters. */
120 unsigned int socket; /**< CPU socket ID for allocations. */
125 void mlx4_rxq_cleanup(struct rxq *rxq);
126 int mlx4_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
127 uint16_t desc, unsigned int socket,
128 const struct rte_eth_rxconf *conf,
129 struct rte_mempool *mp);
130 void mlx4_rx_queue_release(void *dpdk_rxq);
131 void mlx4_mac_addr_del(struct priv *priv);
132 int mlx4_mac_addr_add(struct priv *priv);
136 uint32_t mlx4_txq_mp2mr(struct txq *txq, struct rte_mempool *mp);
137 uint16_t mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
139 uint16_t mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
141 uint16_t mlx4_tx_burst_removed(void *dpdk_txq, struct rte_mbuf **pkts,
143 uint16_t mlx4_rx_burst_removed(void *dpdk_rxq, struct rte_mbuf **pkts,
148 void mlx4_txq_cleanup(struct txq *txq);
149 int mlx4_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
150 uint16_t desc, unsigned int socket,
151 const struct rte_eth_txconf *conf);
152 void mlx4_tx_queue_release(void *dpdk_txq);
154 #endif /* MLX4_RXTX_H_ */