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36 * Tx queues configuration for mlx4 driver.
46 /* Verbs headers do not support -pedantic. */
48 #pragma GCC diagnostic ignored "-Wpedantic"
50 #include <infiniband/verbs.h>
52 #pragma GCC diagnostic error "-Wpedantic"
55 #include <rte_common.h>
56 #include <rte_errno.h>
57 #include <rte_ethdev_driver.h>
58 #include <rte_malloc.h>
60 #include <rte_mempool.h>
64 #include "mlx4_rxtx.h"
65 #include "mlx4_utils.h"
68 * Free Tx queue elements.
71 * Pointer to Tx queue structure.
74 mlx4_txq_free_elts(struct txq *txq)
76 unsigned int elts_head = txq->elts_head;
77 unsigned int elts_tail = txq->elts_tail;
78 struct txq_elt (*elts)[txq->elts_n] = txq->elts;
79 unsigned int elts_m = txq->elts_n - 1;
81 DEBUG("%p: freeing WRs", (void *)txq);
82 while (elts_tail != elts_head) {
83 struct txq_elt *elt = &(*elts)[elts_tail++ & elts_m];
85 assert(elt->buf != NULL);
86 rte_pktmbuf_free(elt->buf);
90 txq->elts_tail = txq->elts_head;
93 struct txq_mp2mr_mbuf_check_data {
98 * Callback function for rte_mempool_obj_iter() to check whether a given
99 * mempool object looks like a mbuf.
102 * The mempool pointer
104 * Context data (struct mlx4_txq_mp2mr_mbuf_check_data). Contains the
109 * Object index, unused.
112 mlx4_txq_mp2mr_mbuf_check(struct rte_mempool *mp, void *arg, void *obj,
115 struct txq_mp2mr_mbuf_check_data *data = arg;
116 struct rte_mbuf *buf = obj;
120 * Check whether mbuf structure fits element size and whether mempool
123 if (sizeof(*buf) > mp->elt_size || buf->pool != mp)
128 * Iterator function for rte_mempool_walk() to register existing mempools and
129 * fill the MP to MR cache of a Tx queue.
132 * Memory Pool to register.
134 * Pointer to Tx queue structure.
137 mlx4_txq_mp2mr_iter(struct rte_mempool *mp, void *arg)
139 struct txq *txq = arg;
140 struct txq_mp2mr_mbuf_check_data data = {
144 /* Register mempool only if the first element looks like a mbuf. */
145 if (rte_mempool_obj_iter(mp, mlx4_txq_mp2mr_mbuf_check, &data) == 0 ||
148 mlx4_txq_mp2mr(txq, mp);
152 * Retrieves information needed in order to directly access the Tx queue.
155 * Pointer to Tx queue structure.
157 * Pointer to device information for this Tx queue.
160 mlx4_txq_fill_dv_obj_info(struct txq *txq, struct mlx4dv_obj *mlxdv)
162 struct mlx4_sq *sq = &txq->msq;
163 struct mlx4_cq *cq = &txq->mcq;
164 struct mlx4dv_qp *dqp = mlxdv->qp.out;
165 struct mlx4dv_cq *dcq = mlxdv->cq.out;
167 /* Total length, including headroom and spare WQEs. */
168 sq->size = (uint32_t)dqp->rq.offset - (uint32_t)dqp->sq.offset;
169 sq->buf = (uint8_t *)dqp->buf.buf + dqp->sq.offset;
170 sq->eob = sq->buf + sq->size;
171 uint32_t headroom_size = 2048 + (1 << dqp->sq.wqe_shift);
172 /* Continuous headroom size bytes must always stay freed. */
173 sq->remain_size = sq->size - headroom_size;
174 sq->owner_opcode = MLX4_OPCODE_SEND | (0 << MLX4_SQ_OWNER_BIT);
175 sq->stamp = rte_cpu_to_be_32(MLX4_SQ_STAMP_VAL |
176 (0 << MLX4_SQ_OWNER_BIT));
178 sq->doorbell_qpn = dqp->doorbell_qpn;
179 cq->buf = dcq->buf.buf;
180 cq->cqe_cnt = dcq->cqe_cnt;
181 cq->set_ci_db = dcq->set_ci_db;
182 cq->cqe_64 = (dcq->cqe_size & 64) ? 1 : 0;
186 * Returns the per-port supported offloads.
189 * Pointer to private structure.
192 * Supported Tx offloads.
195 mlx4_get_tx_port_offloads(struct priv *priv)
197 uint64_t offloads = DEV_TX_OFFLOAD_MULTI_SEGS;
200 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
201 DEV_TX_OFFLOAD_UDP_CKSUM |
202 DEV_TX_OFFLOAD_TCP_CKSUM);
204 if (priv->hw_csum_l2tun)
205 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
210 * Checks if the per-queue offload configuration is valid.
213 * Pointer to private structure.
215 * Per-queue offloads configuration.
218 * Nonzero when configuration is valid.
221 mlx4_check_tx_queue_offloads(struct priv *priv, uint64_t requested)
223 uint64_t mandatory = priv->dev->data->dev_conf.txmode.offloads;
224 uint64_t supported = mlx4_get_tx_port_offloads(priv);
226 return !((mandatory ^ requested) & supported);
230 * DPDK callback to configure a Tx queue.
233 * Pointer to Ethernet device structure.
237 * Number of descriptors to configure in queue.
239 * NUMA socket on which memory must be allocated.
241 * Thresholds parameters.
244 * 0 on success, negative errno value otherwise and rte_errno is set.
247 mlx4_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
248 unsigned int socket, const struct rte_eth_txconf *conf)
250 struct priv *priv = dev->data->dev_private;
251 struct mlx4dv_obj mlxdv;
252 struct mlx4dv_qp dv_qp;
253 struct mlx4dv_cq dv_cq;
254 struct txq_elt (*elts)[rte_align32pow2(desc)];
255 struct ibv_qp_init_attr qp_init_attr;
258 struct mlx4_malloc_vec vec[] = {
260 .align = RTE_CACHE_LINE_SIZE,
261 .size = sizeof(*txq),
262 .addr = (void **)&txq,
265 .align = RTE_CACHE_LINE_SIZE,
266 .size = sizeof(*elts),
267 .addr = (void **)&elts,
270 .align = RTE_CACHE_LINE_SIZE,
271 .size = MLX4_MAX_WQE_SIZE,
272 .addr = (void **)&bounce_buf,
277 DEBUG("%p: configuring queue %u for %u descriptors",
278 (void *)dev, idx, desc);
280 * Don't verify port offloads for application which
283 if ((conf->txq_flags & ETH_TXQ_FLAGS_IGNORE) &&
284 !mlx4_check_tx_queue_offloads(priv, conf->offloads)) {
286 ERROR("%p: Tx queue offloads 0x%" PRIx64 " don't match port "
287 "offloads 0x%" PRIx64 " or supported offloads 0x%" PRIx64,
288 (void *)dev, conf->offloads,
289 dev->data->dev_conf.txmode.offloads,
290 mlx4_get_tx_port_offloads(priv));
293 if (idx >= dev->data->nb_tx_queues) {
294 rte_errno = EOVERFLOW;
295 ERROR("%p: queue index out of range (%u >= %u)",
296 (void *)dev, idx, dev->data->nb_tx_queues);
299 txq = dev->data->tx_queues[idx];
302 DEBUG("%p: Tx queue %u already configured, release it first",
308 ERROR("%p: invalid number of Tx descriptors", (void *)dev);
311 if (desc != RTE_DIM(*elts)) {
312 desc = RTE_DIM(*elts);
313 WARN("%p: increased number of descriptors in Tx queue %u"
314 " to the next power of two (%u)",
315 (void *)dev, idx, desc);
317 /* Allocate and initialize Tx queue. */
318 mlx4_zmallocv_socket("TXQ", vec, RTE_DIM(vec), socket);
320 ERROR("%p: unable to allocate queue index %u",
335 * Request send completion every MLX4_PMD_TX_PER_COMP_REQ
336 * packets or at least 4 times per ring.
339 RTE_MIN(MLX4_PMD_TX_PER_COMP_REQ, desc / 4),
341 RTE_MIN(MLX4_PMD_TX_PER_COMP_REQ, desc / 4),
342 .csum = priv->hw_csum &&
343 (conf->offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
344 DEV_TX_OFFLOAD_UDP_CKSUM |
345 DEV_TX_OFFLOAD_TCP_CKSUM)),
346 .csum_l2tun = priv->hw_csum_l2tun &&
348 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM),
349 /* Enable Tx loopback for VF devices. */
351 .bounce_buf = bounce_buf,
353 txq->cq = ibv_create_cq(priv->ctx, desc, NULL, NULL, 0);
356 ERROR("%p: CQ creation failure: %s",
357 (void *)dev, strerror(rte_errno));
360 qp_init_attr = (struct ibv_qp_init_attr){
365 RTE_MIN(priv->device_attr.max_qp_wr, desc),
367 .max_inline_data = MLX4_PMD_MAX_INLINE,
369 .qp_type = IBV_QPT_RAW_PACKET,
370 /* No completion events must occur by default. */
373 txq->qp = ibv_create_qp(priv->pd, &qp_init_attr);
375 rte_errno = errno ? errno : EINVAL;
376 ERROR("%p: QP creation failure: %s",
377 (void *)dev, strerror(rte_errno));
380 txq->max_inline = qp_init_attr.cap.max_inline_data;
383 &(struct ibv_qp_attr){
384 .qp_state = IBV_QPS_INIT,
385 .port_num = priv->port,
387 IBV_QP_STATE | IBV_QP_PORT);
390 ERROR("%p: QP state to IBV_QPS_INIT failed: %s",
391 (void *)dev, strerror(rte_errno));
396 &(struct ibv_qp_attr){
397 .qp_state = IBV_QPS_RTR,
402 ERROR("%p: QP state to IBV_QPS_RTR failed: %s",
403 (void *)dev, strerror(rte_errno));
408 &(struct ibv_qp_attr){
409 .qp_state = IBV_QPS_RTS,
414 ERROR("%p: QP state to IBV_QPS_RTS failed: %s",
415 (void *)dev, strerror(rte_errno));
418 /* Retrieve device queue information. */
419 mlxdv.cq.in = txq->cq;
420 mlxdv.cq.out = &dv_cq;
421 mlxdv.qp.in = txq->qp;
422 mlxdv.qp.out = &dv_qp;
423 ret = mlx4dv_init_obj(&mlxdv, MLX4DV_OBJ_QP | MLX4DV_OBJ_CQ);
426 ERROR("%p: failed to obtain information needed for"
427 " accessing the device queues", (void *)dev);
430 mlx4_txq_fill_dv_obj_info(txq, &mlxdv);
431 /* Save first wqe pointer in the first element. */
432 (&(*txq->elts)[0])->wqe =
433 (volatile struct mlx4_wqe_ctrl_seg *)txq->msq.buf;
434 /* Pre-register known mempools. */
435 rte_mempool_walk(mlx4_txq_mp2mr_iter, txq);
436 DEBUG("%p: adding Tx queue %p to list", (void *)dev, (void *)txq);
437 dev->data->tx_queues[idx] = txq;
440 dev->data->tx_queues[idx] = NULL;
442 mlx4_tx_queue_release(txq);
444 assert(rte_errno > 0);
449 * DPDK callback to release a Tx queue.
452 * Generic Tx queue pointer.
455 mlx4_tx_queue_release(void *dpdk_txq)
457 struct txq *txq = (struct txq *)dpdk_txq;
464 for (i = 0; i != priv->dev->data->nb_tx_queues; ++i)
465 if (priv->dev->data->tx_queues[i] == txq) {
466 DEBUG("%p: removing Tx queue %p from list",
467 (void *)priv->dev, (void *)txq);
468 priv->dev->data->tx_queues[i] = NULL;
471 mlx4_txq_free_elts(txq);
473 claim_zero(ibv_destroy_qp(txq->qp));
475 claim_zero(ibv_destroy_cq(txq->cq));
476 for (i = 0; i != RTE_DIM(txq->mp2mr); ++i) {
477 if (!txq->mp2mr[i].mp)
479 assert(txq->mp2mr[i].mr);
480 mlx4_mr_put(txq->mp2mr[i].mr);