1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2017 6WIND S.A.
3 * Copyright 2017 Mellanox Technologies, Ltd
8 * Tx queues configuration for mlx4 driver.
18 /* Verbs headers do not support -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
27 #include <rte_common.h>
28 #include <rte_errno.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_malloc.h>
32 #include <rte_mempool.h>
35 #include "mlx4_glue.h"
37 #include "mlx4_rxtx.h"
38 #include "mlx4_utils.h"
41 * Free Tx queue elements.
44 * Pointer to Tx queue structure.
47 mlx4_txq_free_elts(struct txq *txq)
49 unsigned int elts_head = txq->elts_head;
50 unsigned int elts_tail = txq->elts_tail;
51 struct txq_elt (*elts)[txq->elts_n] = txq->elts;
52 unsigned int elts_m = txq->elts_n - 1;
54 DEBUG("%p: freeing WRs", (void *)txq);
55 while (elts_tail != elts_head) {
56 struct txq_elt *elt = &(*elts)[elts_tail++ & elts_m];
58 assert(elt->buf != NULL);
59 rte_pktmbuf_free(elt->buf);
63 txq->elts_tail = txq->elts_head;
67 * Retrieves information needed in order to directly access the Tx queue.
70 * Pointer to Tx queue structure.
72 * Pointer to device information for this Tx queue.
75 mlx4_txq_fill_dv_obj_info(struct txq *txq, struct mlx4dv_obj *mlxdv)
77 struct mlx4_sq *sq = &txq->msq;
78 struct mlx4_cq *cq = &txq->mcq;
79 struct mlx4dv_qp *dqp = mlxdv->qp.out;
80 struct mlx4dv_cq *dcq = mlxdv->cq.out;
82 /* Total length, including headroom and spare WQEs. */
83 sq->size = (uint32_t)dqp->rq.offset - (uint32_t)dqp->sq.offset;
84 sq->buf = (uint8_t *)dqp->buf.buf + dqp->sq.offset;
85 sq->eob = sq->buf + sq->size;
86 uint32_t headroom_size = 2048 + (1 << dqp->sq.wqe_shift);
87 /* Continuous headroom size bytes must always stay freed. */
88 sq->remain_size = sq->size - headroom_size;
89 sq->owner_opcode = MLX4_OPCODE_SEND | (0 << MLX4_SQ_OWNER_BIT);
90 sq->stamp = rte_cpu_to_be_32(MLX4_SQ_STAMP_VAL |
91 (0 << MLX4_SQ_OWNER_BIT));
93 sq->doorbell_qpn = dqp->doorbell_qpn;
94 cq->buf = dcq->buf.buf;
95 cq->cqe_cnt = dcq->cqe_cnt;
96 cq->set_ci_db = dcq->set_ci_db;
97 cq->cqe_64 = (dcq->cqe_size & 64) ? 1 : 0;
101 * Returns the per-port supported offloads.
104 * Pointer to private structure.
107 * Supported Tx offloads.
110 mlx4_get_tx_port_offloads(struct priv *priv)
112 uint64_t offloads = DEV_TX_OFFLOAD_MULTI_SEGS;
115 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
116 DEV_TX_OFFLOAD_UDP_CKSUM |
117 DEV_TX_OFFLOAD_TCP_CKSUM);
119 if (priv->hw_csum_l2tun)
120 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
125 * DPDK callback to configure a Tx queue.
128 * Pointer to Ethernet device structure.
132 * Number of descriptors to configure in queue.
134 * NUMA socket on which memory must be allocated.
136 * Thresholds parameters.
139 * 0 on success, negative errno value otherwise and rte_errno is set.
142 mlx4_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
143 unsigned int socket, const struct rte_eth_txconf *conf)
145 struct priv *priv = dev->data->dev_private;
146 struct mlx4dv_obj mlxdv;
147 struct mlx4dv_qp dv_qp;
148 struct mlx4dv_cq dv_cq;
149 struct txq_elt (*elts)[rte_align32pow2(desc)];
150 struct ibv_qp_init_attr qp_init_attr;
153 struct mlx4_malloc_vec vec[] = {
155 .align = RTE_CACHE_LINE_SIZE,
156 .size = sizeof(*txq),
157 .addr = (void **)&txq,
160 .align = RTE_CACHE_LINE_SIZE,
161 .size = sizeof(*elts),
162 .addr = (void **)&elts,
165 .align = RTE_CACHE_LINE_SIZE,
166 .size = MLX4_MAX_WQE_SIZE,
167 .addr = (void **)&bounce_buf,
173 offloads = conf->offloads | dev->data->dev_conf.txmode.offloads;
175 DEBUG("%p: configuring queue %u for %u descriptors",
176 (void *)dev, idx, desc);
178 if (idx >= dev->data->nb_tx_queues) {
179 rte_errno = EOVERFLOW;
180 ERROR("%p: queue index out of range (%u >= %u)",
181 (void *)dev, idx, dev->data->nb_tx_queues);
184 txq = dev->data->tx_queues[idx];
187 DEBUG("%p: Tx queue %u already configured, release it first",
193 ERROR("%p: invalid number of Tx descriptors", (void *)dev);
196 if (desc != RTE_DIM(*elts)) {
197 desc = RTE_DIM(*elts);
198 WARN("%p: increased number of descriptors in Tx queue %u"
199 " to the next power of two (%u)",
200 (void *)dev, idx, desc);
202 /* Allocate and initialize Tx queue. */
203 mlx4_zmallocv_socket("TXQ", vec, RTE_DIM(vec), socket);
205 ERROR("%p: unable to allocate queue index %u",
220 * Request send completion every MLX4_PMD_TX_PER_COMP_REQ
221 * packets or at least 4 times per ring.
224 RTE_MIN(MLX4_PMD_TX_PER_COMP_REQ, desc / 4),
226 RTE_MIN(MLX4_PMD_TX_PER_COMP_REQ, desc / 4),
227 .csum = priv->hw_csum &&
228 (offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
229 DEV_TX_OFFLOAD_UDP_CKSUM |
230 DEV_TX_OFFLOAD_TCP_CKSUM)),
231 .csum_l2tun = priv->hw_csum_l2tun &&
233 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM),
234 /* Enable Tx loopback for VF devices. */
236 .bounce_buf = bounce_buf,
238 txq->cq = mlx4_glue->create_cq(priv->ctx, desc, NULL, NULL, 0);
241 ERROR("%p: CQ creation failure: %s",
242 (void *)dev, strerror(rte_errno));
245 qp_init_attr = (struct ibv_qp_init_attr){
250 RTE_MIN(priv->device_attr.max_qp_wr, desc),
252 .max_inline_data = MLX4_PMD_MAX_INLINE,
254 .qp_type = IBV_QPT_RAW_PACKET,
255 /* No completion events must occur by default. */
258 txq->qp = mlx4_glue->create_qp(priv->pd, &qp_init_attr);
260 rte_errno = errno ? errno : EINVAL;
261 ERROR("%p: QP creation failure: %s",
262 (void *)dev, strerror(rte_errno));
265 txq->max_inline = qp_init_attr.cap.max_inline_data;
266 ret = mlx4_glue->modify_qp
268 &(struct ibv_qp_attr){
269 .qp_state = IBV_QPS_INIT,
270 .port_num = priv->port,
272 IBV_QP_STATE | IBV_QP_PORT);
275 ERROR("%p: QP state to IBV_QPS_INIT failed: %s",
276 (void *)dev, strerror(rte_errno));
279 ret = mlx4_glue->modify_qp
281 &(struct ibv_qp_attr){
282 .qp_state = IBV_QPS_RTR,
287 ERROR("%p: QP state to IBV_QPS_RTR failed: %s",
288 (void *)dev, strerror(rte_errno));
291 ret = mlx4_glue->modify_qp
293 &(struct ibv_qp_attr){
294 .qp_state = IBV_QPS_RTS,
299 ERROR("%p: QP state to IBV_QPS_RTS failed: %s",
300 (void *)dev, strerror(rte_errno));
303 /* Retrieve device queue information. */
304 mlxdv.cq.in = txq->cq;
305 mlxdv.cq.out = &dv_cq;
306 mlxdv.qp.in = txq->qp;
307 mlxdv.qp.out = &dv_qp;
308 ret = mlx4_glue->dv_init_obj(&mlxdv, MLX4DV_OBJ_QP | MLX4DV_OBJ_CQ);
311 ERROR("%p: failed to obtain information needed for"
312 " accessing the device queues", (void *)dev);
315 mlx4_txq_fill_dv_obj_info(txq, &mlxdv);
316 /* Save first wqe pointer in the first element. */
317 (&(*txq->elts)[0])->wqe =
318 (volatile struct mlx4_wqe_ctrl_seg *)txq->msq.buf;
319 DEBUG("%p: adding Tx queue %p to list", (void *)dev, (void *)txq);
320 dev->data->tx_queues[idx] = txq;
323 dev->data->tx_queues[idx] = NULL;
325 mlx4_tx_queue_release(txq);
327 assert(rte_errno > 0);
332 * DPDK callback to release a Tx queue.
335 * Generic Tx queue pointer.
338 mlx4_tx_queue_release(void *dpdk_txq)
340 struct txq *txq = (struct txq *)dpdk_txq;
347 for (i = 0; i != priv->dev->data->nb_tx_queues; ++i)
348 if (priv->dev->data->tx_queues[i] == txq) {
349 DEBUG("%p: removing Tx queue %p from list",
350 (void *)priv->dev, (void *)txq);
351 priv->dev->data->tx_queues[i] = NULL;
354 mlx4_txq_free_elts(txq);
356 claim_zero(mlx4_glue->destroy_qp(txq->qp));
358 claim_zero(mlx4_glue->destroy_cq(txq->cq));