1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2017 6WIND S.A.
3 * Copyright 2017 Mellanox Technologies, Ltd
8 * Tx queues configuration for mlx4 driver.
18 /* Verbs headers do not support -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
27 #include <rte_common.h>
28 #include <rte_errno.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_malloc.h>
32 #include <rte_mempool.h>
35 #include "mlx4_glue.h"
37 #include "mlx4_rxtx.h"
38 #include "mlx4_utils.h"
41 * Free Tx queue elements.
44 * Pointer to Tx queue structure.
47 mlx4_txq_free_elts(struct txq *txq)
49 unsigned int elts_head = txq->elts_head;
50 unsigned int elts_tail = txq->elts_tail;
51 struct txq_elt (*elts)[txq->elts_n] = txq->elts;
52 unsigned int elts_m = txq->elts_n - 1;
54 DEBUG("%p: freeing WRs", (void *)txq);
55 while (elts_tail != elts_head) {
56 struct txq_elt *elt = &(*elts)[elts_tail++ & elts_m];
58 assert(elt->buf != NULL);
59 rte_pktmbuf_free(elt->buf);
63 txq->elts_tail = txq->elts_head;
66 struct txq_mp2mr_mbuf_check_data {
71 * Callback function for rte_mempool_obj_iter() to check whether a given
72 * mempool object looks like a mbuf.
77 * Context data (struct mlx4_txq_mp2mr_mbuf_check_data). Contains the
82 * Object index, unused.
85 mlx4_txq_mp2mr_mbuf_check(struct rte_mempool *mp, void *arg, void *obj,
88 struct txq_mp2mr_mbuf_check_data *data = arg;
89 struct rte_mbuf *buf = obj;
93 * Check whether mbuf structure fits element size and whether mempool
96 if (sizeof(*buf) > mp->elt_size || buf->pool != mp)
101 * Iterator function for rte_mempool_walk() to register existing mempools and
102 * fill the MP to MR cache of a Tx queue.
105 * Memory Pool to register.
107 * Pointer to Tx queue structure.
110 mlx4_txq_mp2mr_iter(struct rte_mempool *mp, void *arg)
112 struct txq *txq = arg;
113 struct txq_mp2mr_mbuf_check_data data = {
117 /* Register mempool only if the first element looks like a mbuf. */
118 if (rte_mempool_obj_iter(mp, mlx4_txq_mp2mr_mbuf_check, &data) == 0 ||
121 mlx4_txq_mp2mr(txq, mp);
125 * Retrieves information needed in order to directly access the Tx queue.
128 * Pointer to Tx queue structure.
130 * Pointer to device information for this Tx queue.
133 mlx4_txq_fill_dv_obj_info(struct txq *txq, struct mlx4dv_obj *mlxdv)
135 struct mlx4_sq *sq = &txq->msq;
136 struct mlx4_cq *cq = &txq->mcq;
137 struct mlx4dv_qp *dqp = mlxdv->qp.out;
138 struct mlx4dv_cq *dcq = mlxdv->cq.out;
140 /* Total length, including headroom and spare WQEs. */
141 sq->size = (uint32_t)dqp->rq.offset - (uint32_t)dqp->sq.offset;
142 sq->buf = (uint8_t *)dqp->buf.buf + dqp->sq.offset;
143 sq->eob = sq->buf + sq->size;
144 uint32_t headroom_size = 2048 + (1 << dqp->sq.wqe_shift);
145 /* Continuous headroom size bytes must always stay freed. */
146 sq->remain_size = sq->size - headroom_size;
147 sq->owner_opcode = MLX4_OPCODE_SEND | (0 << MLX4_SQ_OWNER_BIT);
148 sq->stamp = rte_cpu_to_be_32(MLX4_SQ_STAMP_VAL |
149 (0 << MLX4_SQ_OWNER_BIT));
151 sq->doorbell_qpn = dqp->doorbell_qpn;
152 cq->buf = dcq->buf.buf;
153 cq->cqe_cnt = dcq->cqe_cnt;
154 cq->set_ci_db = dcq->set_ci_db;
155 cq->cqe_64 = (dcq->cqe_size & 64) ? 1 : 0;
159 * Returns the per-port supported offloads.
162 * Pointer to private structure.
165 * Supported Tx offloads.
168 mlx4_get_tx_port_offloads(struct priv *priv)
170 uint64_t offloads = DEV_TX_OFFLOAD_MULTI_SEGS;
173 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
174 DEV_TX_OFFLOAD_UDP_CKSUM |
175 DEV_TX_OFFLOAD_TCP_CKSUM);
177 if (priv->hw_csum_l2tun)
178 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
183 * Checks if the per-queue offload configuration is valid.
186 * Pointer to private structure.
188 * Per-queue offloads configuration.
191 * Nonzero when configuration is valid.
194 mlx4_check_tx_queue_offloads(struct priv *priv, uint64_t requested)
196 uint64_t mandatory = priv->dev->data->dev_conf.txmode.offloads;
197 uint64_t supported = mlx4_get_tx_port_offloads(priv);
199 return !((mandatory ^ requested) & supported);
203 * DPDK callback to configure a Tx queue.
206 * Pointer to Ethernet device structure.
210 * Number of descriptors to configure in queue.
212 * NUMA socket on which memory must be allocated.
214 * Thresholds parameters.
217 * 0 on success, negative errno value otherwise and rte_errno is set.
220 mlx4_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
221 unsigned int socket, const struct rte_eth_txconf *conf)
223 struct priv *priv = dev->data->dev_private;
224 struct mlx4dv_obj mlxdv;
225 struct mlx4dv_qp dv_qp;
226 struct mlx4dv_cq dv_cq;
227 struct txq_elt (*elts)[rte_align32pow2(desc)];
228 struct ibv_qp_init_attr qp_init_attr;
231 struct mlx4_malloc_vec vec[] = {
233 .align = RTE_CACHE_LINE_SIZE,
234 .size = sizeof(*txq),
235 .addr = (void **)&txq,
238 .align = RTE_CACHE_LINE_SIZE,
239 .size = sizeof(*elts),
240 .addr = (void **)&elts,
243 .align = RTE_CACHE_LINE_SIZE,
244 .size = MLX4_MAX_WQE_SIZE,
245 .addr = (void **)&bounce_buf,
250 DEBUG("%p: configuring queue %u for %u descriptors",
251 (void *)dev, idx, desc);
253 * Don't verify port offloads for application which
256 if ((conf->txq_flags & ETH_TXQ_FLAGS_IGNORE) &&
257 !mlx4_check_tx_queue_offloads(priv, conf->offloads)) {
259 ERROR("%p: Tx queue offloads 0x%" PRIx64 " don't match port "
260 "offloads 0x%" PRIx64 " or supported offloads 0x%" PRIx64,
261 (void *)dev, conf->offloads,
262 dev->data->dev_conf.txmode.offloads,
263 mlx4_get_tx_port_offloads(priv));
266 if (idx >= dev->data->nb_tx_queues) {
267 rte_errno = EOVERFLOW;
268 ERROR("%p: queue index out of range (%u >= %u)",
269 (void *)dev, idx, dev->data->nb_tx_queues);
272 txq = dev->data->tx_queues[idx];
275 DEBUG("%p: Tx queue %u already configured, release it first",
281 ERROR("%p: invalid number of Tx descriptors", (void *)dev);
284 if (desc != RTE_DIM(*elts)) {
285 desc = RTE_DIM(*elts);
286 WARN("%p: increased number of descriptors in Tx queue %u"
287 " to the next power of two (%u)",
288 (void *)dev, idx, desc);
290 /* Allocate and initialize Tx queue. */
291 mlx4_zmallocv_socket("TXQ", vec, RTE_DIM(vec), socket);
293 ERROR("%p: unable to allocate queue index %u",
308 * Request send completion every MLX4_PMD_TX_PER_COMP_REQ
309 * packets or at least 4 times per ring.
312 RTE_MIN(MLX4_PMD_TX_PER_COMP_REQ, desc / 4),
314 RTE_MIN(MLX4_PMD_TX_PER_COMP_REQ, desc / 4),
315 .csum = priv->hw_csum &&
316 (conf->offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
317 DEV_TX_OFFLOAD_UDP_CKSUM |
318 DEV_TX_OFFLOAD_TCP_CKSUM)),
319 .csum_l2tun = priv->hw_csum_l2tun &&
321 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM),
322 /* Enable Tx loopback for VF devices. */
324 .bounce_buf = bounce_buf,
326 txq->cq = mlx4_glue->create_cq(priv->ctx, desc, NULL, NULL, 0);
329 ERROR("%p: CQ creation failure: %s",
330 (void *)dev, strerror(rte_errno));
333 qp_init_attr = (struct ibv_qp_init_attr){
338 RTE_MIN(priv->device_attr.max_qp_wr, desc),
340 .max_inline_data = MLX4_PMD_MAX_INLINE,
342 .qp_type = IBV_QPT_RAW_PACKET,
343 /* No completion events must occur by default. */
346 txq->qp = mlx4_glue->create_qp(priv->pd, &qp_init_attr);
348 rte_errno = errno ? errno : EINVAL;
349 ERROR("%p: QP creation failure: %s",
350 (void *)dev, strerror(rte_errno));
353 txq->max_inline = qp_init_attr.cap.max_inline_data;
354 ret = mlx4_glue->modify_qp
356 &(struct ibv_qp_attr){
357 .qp_state = IBV_QPS_INIT,
358 .port_num = priv->port,
360 IBV_QP_STATE | IBV_QP_PORT);
363 ERROR("%p: QP state to IBV_QPS_INIT failed: %s",
364 (void *)dev, strerror(rte_errno));
367 ret = mlx4_glue->modify_qp
369 &(struct ibv_qp_attr){
370 .qp_state = IBV_QPS_RTR,
375 ERROR("%p: QP state to IBV_QPS_RTR failed: %s",
376 (void *)dev, strerror(rte_errno));
379 ret = mlx4_glue->modify_qp
381 &(struct ibv_qp_attr){
382 .qp_state = IBV_QPS_RTS,
387 ERROR("%p: QP state to IBV_QPS_RTS failed: %s",
388 (void *)dev, strerror(rte_errno));
391 /* Retrieve device queue information. */
392 mlxdv.cq.in = txq->cq;
393 mlxdv.cq.out = &dv_cq;
394 mlxdv.qp.in = txq->qp;
395 mlxdv.qp.out = &dv_qp;
396 ret = mlx4_glue->dv_init_obj(&mlxdv, MLX4DV_OBJ_QP | MLX4DV_OBJ_CQ);
399 ERROR("%p: failed to obtain information needed for"
400 " accessing the device queues", (void *)dev);
403 mlx4_txq_fill_dv_obj_info(txq, &mlxdv);
404 /* Save first wqe pointer in the first element. */
405 (&(*txq->elts)[0])->wqe =
406 (volatile struct mlx4_wqe_ctrl_seg *)txq->msq.buf;
407 /* Pre-register known mempools. */
408 rte_mempool_walk(mlx4_txq_mp2mr_iter, txq);
409 DEBUG("%p: adding Tx queue %p to list", (void *)dev, (void *)txq);
410 dev->data->tx_queues[idx] = txq;
413 dev->data->tx_queues[idx] = NULL;
415 mlx4_tx_queue_release(txq);
417 assert(rte_errno > 0);
422 * DPDK callback to release a Tx queue.
425 * Generic Tx queue pointer.
428 mlx4_tx_queue_release(void *dpdk_txq)
430 struct txq *txq = (struct txq *)dpdk_txq;
437 for (i = 0; i != priv->dev->data->nb_tx_queues; ++i)
438 if (priv->dev->data->tx_queues[i] == txq) {
439 DEBUG("%p: removing Tx queue %p from list",
440 (void *)priv->dev, (void *)txq);
441 priv->dev->data->tx_queues[i] = NULL;
444 mlx4_txq_free_elts(txq);
446 claim_zero(mlx4_glue->destroy_qp(txq->qp));
448 claim_zero(mlx4_glue->destroy_cq(txq->cq));
449 for (i = 0; i != RTE_DIM(txq->mp2mr); ++i) {
450 if (!txq->mp2mr[i].mp)
452 assert(txq->mp2mr[i].mr);
453 mlx4_mr_put(txq->mp2mr[i].mr);