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36 * Tx queues configuration for mlx4 driver.
45 /* Verbs headers do not support -pedantic. */
47 #pragma GCC diagnostic ignored "-Wpedantic"
49 #include <infiniband/verbs.h>
51 #pragma GCC diagnostic error "-Wpedantic"
54 #include <rte_common.h>
55 #include <rte_errno.h>
56 #include <rte_ethdev.h>
57 #include <rte_malloc.h>
59 #include <rte_mempool.h>
63 #include "mlx4_rxtx.h"
64 #include "mlx4_utils.h"
67 * Free Tx queue elements.
70 * Pointer to Tx queue structure.
73 mlx4_txq_free_elts(struct txq *txq)
75 unsigned int elts_head = txq->elts_head;
76 unsigned int elts_tail = txq->elts_tail;
77 struct txq_elt (*elts)[txq->elts_n] = txq->elts;
79 DEBUG("%p: freeing WRs", (void *)txq);
80 while (elts_tail != elts_head) {
81 struct txq_elt *elt = &(*elts)[elts_tail];
83 assert(elt->buf != NULL);
84 rte_pktmbuf_free(elt->buf);
86 if (++elts_tail == RTE_DIM(*elts))
89 txq->elts_tail = txq->elts_head;
92 struct txq_mp2mr_mbuf_check_data {
97 * Callback function for rte_mempool_obj_iter() to check whether a given
98 * mempool object looks like a mbuf.
101 * The mempool pointer
103 * Context data (struct mlx4_txq_mp2mr_mbuf_check_data). Contains the
108 * Object index, unused.
111 mlx4_txq_mp2mr_mbuf_check(struct rte_mempool *mp, void *arg, void *obj,
114 struct txq_mp2mr_mbuf_check_data *data = arg;
115 struct rte_mbuf *buf = obj;
119 * Check whether mbuf structure fits element size and whether mempool
122 if (sizeof(*buf) > mp->elt_size || buf->pool != mp)
127 * Iterator function for rte_mempool_walk() to register existing mempools and
128 * fill the MP to MR cache of a Tx queue.
131 * Memory Pool to register.
133 * Pointer to Tx queue structure.
136 mlx4_txq_mp2mr_iter(struct rte_mempool *mp, void *arg)
138 struct txq *txq = arg;
139 struct txq_mp2mr_mbuf_check_data data = {
143 /* Register mempool only if the first element looks like a mbuf. */
144 if (rte_mempool_obj_iter(mp, mlx4_txq_mp2mr_mbuf_check, &data) == 0 ||
147 mlx4_txq_mp2mr(txq, mp);
151 * Retrieves information needed in order to directly access the Tx queue.
154 * Pointer to Tx queue structure.
156 * Pointer to device information for this Tx queue.
159 mlx4_txq_fill_dv_obj_info(struct txq *txq, struct mlx4dv_obj *mlxdv)
161 struct mlx4_sq *sq = &txq->msq;
162 struct mlx4_cq *cq = &txq->mcq;
163 struct mlx4dv_qp *dqp = mlxdv->qp.out;
164 struct mlx4dv_cq *dcq = mlxdv->cq.out;
165 uint32_t sq_size = (uint32_t)dqp->rq.offset - (uint32_t)dqp->sq.offset;
167 sq->buf = (uint8_t *)dqp->buf.buf + dqp->sq.offset;
168 /* Total length, including headroom and spare WQEs. */
169 sq->eob = sq->buf + sq_size;
173 (dqp->sq.wqe_cnt << dqp->sq.wqe_shift) >> MLX4_TXBB_SHIFT;
174 sq->txbb_cnt_mask = sq->txbb_cnt - 1;
176 sq->doorbell_qpn = dqp->doorbell_qpn;
178 (2048 + (1 << dqp->sq.wqe_shift)) >> MLX4_TXBB_SHIFT;
179 cq->buf = dcq->buf.buf;
180 cq->cqe_cnt = dcq->cqe_cnt;
181 cq->set_ci_db = dcq->set_ci_db;
182 cq->cqe_64 = (dcq->cqe_size & 64) ? 1 : 0;
186 * DPDK callback to configure a Tx queue.
189 * Pointer to Ethernet device structure.
193 * Number of descriptors to configure in queue.
195 * NUMA socket on which memory must be allocated.
197 * Thresholds parameters.
200 * 0 on success, negative errno value otherwise and rte_errno is set.
203 mlx4_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
204 unsigned int socket, const struct rte_eth_txconf *conf)
206 struct priv *priv = dev->data->dev_private;
207 struct mlx4dv_obj mlxdv;
208 struct mlx4dv_qp dv_qp;
209 struct mlx4dv_cq dv_cq;
210 struct txq_elt (*elts)[desc];
211 struct ibv_qp_init_attr qp_init_attr;
214 struct mlx4_malloc_vec vec[] = {
216 .align = RTE_CACHE_LINE_SIZE,
217 .size = sizeof(*txq),
218 .addr = (void **)&txq,
221 .align = RTE_CACHE_LINE_SIZE,
222 .size = sizeof(*elts),
223 .addr = (void **)&elts,
226 .align = RTE_CACHE_LINE_SIZE,
227 .size = MLX4_MAX_WQE_SIZE,
228 .addr = (void **)&bounce_buf,
233 (void)conf; /* Thresholds configuration (ignored). */
234 DEBUG("%p: configuring queue %u for %u descriptors",
235 (void *)dev, idx, desc);
236 if (idx >= dev->data->nb_tx_queues) {
237 rte_errno = EOVERFLOW;
238 ERROR("%p: queue index out of range (%u >= %u)",
239 (void *)dev, idx, dev->data->nb_tx_queues);
242 txq = dev->data->tx_queues[idx];
245 DEBUG("%p: Tx queue %u already configured, release it first",
251 ERROR("%p: invalid number of Tx descriptors", (void *)dev);
254 /* Allocate and initialize Tx queue. */
255 mlx4_zmallocv_socket("TXQ", vec, RTE_DIM(vec), socket);
257 ERROR("%p: unable to allocate queue index %u",
273 * Request send completion every MLX4_PMD_TX_PER_COMP_REQ
274 * packets or at least 4 times per ring.
277 RTE_MIN(MLX4_PMD_TX_PER_COMP_REQ, desc / 4),
279 RTE_MIN(MLX4_PMD_TX_PER_COMP_REQ, desc / 4),
280 .csum = priv->hw_csum,
281 .csum_l2tun = priv->hw_csum_l2tun,
282 /* Enable Tx loopback for VF devices. */
284 .bounce_buf = bounce_buf,
286 txq->cq = ibv_create_cq(priv->ctx, desc, NULL, NULL, 0);
289 ERROR("%p: CQ creation failure: %s",
290 (void *)dev, strerror(rte_errno));
293 qp_init_attr = (struct ibv_qp_init_attr){
298 RTE_MIN(priv->device_attr.max_qp_wr, desc),
300 .max_inline_data = MLX4_PMD_MAX_INLINE,
302 .qp_type = IBV_QPT_RAW_PACKET,
303 /* No completion events must occur by default. */
306 txq->qp = ibv_create_qp(priv->pd, &qp_init_attr);
308 rte_errno = errno ? errno : EINVAL;
309 ERROR("%p: QP creation failure: %s",
310 (void *)dev, strerror(rte_errno));
313 txq->max_inline = qp_init_attr.cap.max_inline_data;
316 &(struct ibv_qp_attr){
317 .qp_state = IBV_QPS_INIT,
318 .port_num = priv->port,
320 IBV_QP_STATE | IBV_QP_PORT);
323 ERROR("%p: QP state to IBV_QPS_INIT failed: %s",
324 (void *)dev, strerror(rte_errno));
329 &(struct ibv_qp_attr){
330 .qp_state = IBV_QPS_RTR,
335 ERROR("%p: QP state to IBV_QPS_RTR failed: %s",
336 (void *)dev, strerror(rte_errno));
341 &(struct ibv_qp_attr){
342 .qp_state = IBV_QPS_RTS,
347 ERROR("%p: QP state to IBV_QPS_RTS failed: %s",
348 (void *)dev, strerror(rte_errno));
351 /* Retrieve device queue information. */
352 mlxdv.cq.in = txq->cq;
353 mlxdv.cq.out = &dv_cq;
354 mlxdv.qp.in = txq->qp;
355 mlxdv.qp.out = &dv_qp;
356 ret = mlx4dv_init_obj(&mlxdv, MLX4DV_OBJ_QP | MLX4DV_OBJ_CQ);
359 ERROR("%p: failed to obtain information needed for"
360 " accessing the device queues", (void *)dev);
363 mlx4_txq_fill_dv_obj_info(txq, &mlxdv);
364 /* Pre-register known mempools. */
365 rte_mempool_walk(mlx4_txq_mp2mr_iter, txq);
366 DEBUG("%p: adding Tx queue %p to list", (void *)dev, (void *)txq);
367 dev->data->tx_queues[idx] = txq;
370 dev->data->tx_queues[idx] = NULL;
372 mlx4_tx_queue_release(txq);
374 assert(rte_errno > 0);
379 * DPDK callback to release a Tx queue.
382 * Generic Tx queue pointer.
385 mlx4_tx_queue_release(void *dpdk_txq)
387 struct txq *txq = (struct txq *)dpdk_txq;
394 for (i = 0; i != priv->dev->data->nb_tx_queues; ++i)
395 if (priv->dev->data->tx_queues[i] == txq) {
396 DEBUG("%p: removing Tx queue %p from list",
397 (void *)priv->dev, (void *)txq);
398 priv->dev->data->tx_queues[i] = NULL;
401 mlx4_txq_free_elts(txq);
403 claim_zero(ibv_destroy_qp(txq->qp));
405 claim_zero(ibv_destroy_cq(txq->cq));
406 for (i = 0; i != RTE_DIM(txq->mp2mr); ++i) {
407 if (!txq->mp2mr[i].mp)
409 assert(txq->mp2mr[i].mr);
410 mlx4_mr_put(txq->mp2mr[i].mr);