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36 * Tx queues configuration for mlx4 driver.
46 /* Verbs headers do not support -pedantic. */
48 #pragma GCC diagnostic ignored "-Wpedantic"
50 #include <infiniband/verbs.h>
52 #pragma GCC diagnostic error "-Wpedantic"
55 #include <rte_common.h>
56 #include <rte_errno.h>
57 #include <rte_ethdev_driver.h>
58 #include <rte_malloc.h>
60 #include <rte_mempool.h>
63 #include "mlx4_glue.h"
65 #include "mlx4_rxtx.h"
66 #include "mlx4_utils.h"
69 * Free Tx queue elements.
72 * Pointer to Tx queue structure.
75 mlx4_txq_free_elts(struct txq *txq)
77 unsigned int elts_head = txq->elts_head;
78 unsigned int elts_tail = txq->elts_tail;
79 struct txq_elt (*elts)[txq->elts_n] = txq->elts;
80 unsigned int elts_m = txq->elts_n - 1;
82 DEBUG("%p: freeing WRs", (void *)txq);
83 while (elts_tail != elts_head) {
84 struct txq_elt *elt = &(*elts)[elts_tail++ & elts_m];
86 assert(elt->buf != NULL);
87 rte_pktmbuf_free(elt->buf);
91 txq->elts_tail = txq->elts_head;
94 struct txq_mp2mr_mbuf_check_data {
99 * Callback function for rte_mempool_obj_iter() to check whether a given
100 * mempool object looks like a mbuf.
103 * The mempool pointer
105 * Context data (struct mlx4_txq_mp2mr_mbuf_check_data). Contains the
110 * Object index, unused.
113 mlx4_txq_mp2mr_mbuf_check(struct rte_mempool *mp, void *arg, void *obj,
116 struct txq_mp2mr_mbuf_check_data *data = arg;
117 struct rte_mbuf *buf = obj;
121 * Check whether mbuf structure fits element size and whether mempool
124 if (sizeof(*buf) > mp->elt_size || buf->pool != mp)
129 * Iterator function for rte_mempool_walk() to register existing mempools and
130 * fill the MP to MR cache of a Tx queue.
133 * Memory Pool to register.
135 * Pointer to Tx queue structure.
138 mlx4_txq_mp2mr_iter(struct rte_mempool *mp, void *arg)
140 struct txq *txq = arg;
141 struct txq_mp2mr_mbuf_check_data data = {
145 /* Register mempool only if the first element looks like a mbuf. */
146 if (rte_mempool_obj_iter(mp, mlx4_txq_mp2mr_mbuf_check, &data) == 0 ||
149 mlx4_txq_mp2mr(txq, mp);
153 * Retrieves information needed in order to directly access the Tx queue.
156 * Pointer to Tx queue structure.
158 * Pointer to device information for this Tx queue.
161 mlx4_txq_fill_dv_obj_info(struct txq *txq, struct mlx4dv_obj *mlxdv)
163 struct mlx4_sq *sq = &txq->msq;
164 struct mlx4_cq *cq = &txq->mcq;
165 struct mlx4dv_qp *dqp = mlxdv->qp.out;
166 struct mlx4dv_cq *dcq = mlxdv->cq.out;
168 /* Total length, including headroom and spare WQEs. */
169 sq->size = (uint32_t)dqp->rq.offset - (uint32_t)dqp->sq.offset;
170 sq->buf = (uint8_t *)dqp->buf.buf + dqp->sq.offset;
171 sq->eob = sq->buf + sq->size;
172 uint32_t headroom_size = 2048 + (1 << dqp->sq.wqe_shift);
173 /* Continuous headroom size bytes must always stay freed. */
174 sq->remain_size = sq->size - headroom_size;
175 sq->owner_opcode = MLX4_OPCODE_SEND | (0 << MLX4_SQ_OWNER_BIT);
176 sq->stamp = rte_cpu_to_be_32(MLX4_SQ_STAMP_VAL |
177 (0 << MLX4_SQ_OWNER_BIT));
179 sq->doorbell_qpn = dqp->doorbell_qpn;
180 cq->buf = dcq->buf.buf;
181 cq->cqe_cnt = dcq->cqe_cnt;
182 cq->set_ci_db = dcq->set_ci_db;
183 cq->cqe_64 = (dcq->cqe_size & 64) ? 1 : 0;
187 * Returns the per-port supported offloads.
190 * Pointer to private structure.
193 * Supported Tx offloads.
196 mlx4_get_tx_port_offloads(struct priv *priv)
198 uint64_t offloads = DEV_TX_OFFLOAD_MULTI_SEGS;
201 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
202 DEV_TX_OFFLOAD_UDP_CKSUM |
203 DEV_TX_OFFLOAD_TCP_CKSUM);
205 if (priv->hw_csum_l2tun)
206 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
211 * Checks if the per-queue offload configuration is valid.
214 * Pointer to private structure.
216 * Per-queue offloads configuration.
219 * Nonzero when configuration is valid.
222 mlx4_check_tx_queue_offloads(struct priv *priv, uint64_t requested)
224 uint64_t mandatory = priv->dev->data->dev_conf.txmode.offloads;
225 uint64_t supported = mlx4_get_tx_port_offloads(priv);
227 return !((mandatory ^ requested) & supported);
231 * DPDK callback to configure a Tx queue.
234 * Pointer to Ethernet device structure.
238 * Number of descriptors to configure in queue.
240 * NUMA socket on which memory must be allocated.
242 * Thresholds parameters.
245 * 0 on success, negative errno value otherwise and rte_errno is set.
248 mlx4_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
249 unsigned int socket, const struct rte_eth_txconf *conf)
251 struct priv *priv = dev->data->dev_private;
252 struct mlx4dv_obj mlxdv;
253 struct mlx4dv_qp dv_qp;
254 struct mlx4dv_cq dv_cq;
255 struct txq_elt (*elts)[rte_align32pow2(desc)];
256 struct ibv_qp_init_attr qp_init_attr;
259 struct mlx4_malloc_vec vec[] = {
261 .align = RTE_CACHE_LINE_SIZE,
262 .size = sizeof(*txq),
263 .addr = (void **)&txq,
266 .align = RTE_CACHE_LINE_SIZE,
267 .size = sizeof(*elts),
268 .addr = (void **)&elts,
271 .align = RTE_CACHE_LINE_SIZE,
272 .size = MLX4_MAX_WQE_SIZE,
273 .addr = (void **)&bounce_buf,
278 DEBUG("%p: configuring queue %u for %u descriptors",
279 (void *)dev, idx, desc);
281 * Don't verify port offloads for application which
284 if ((conf->txq_flags & ETH_TXQ_FLAGS_IGNORE) &&
285 !mlx4_check_tx_queue_offloads(priv, conf->offloads)) {
287 ERROR("%p: Tx queue offloads 0x%" PRIx64 " don't match port "
288 "offloads 0x%" PRIx64 " or supported offloads 0x%" PRIx64,
289 (void *)dev, conf->offloads,
290 dev->data->dev_conf.txmode.offloads,
291 mlx4_get_tx_port_offloads(priv));
294 if (idx >= dev->data->nb_tx_queues) {
295 rte_errno = EOVERFLOW;
296 ERROR("%p: queue index out of range (%u >= %u)",
297 (void *)dev, idx, dev->data->nb_tx_queues);
300 txq = dev->data->tx_queues[idx];
303 DEBUG("%p: Tx queue %u already configured, release it first",
309 ERROR("%p: invalid number of Tx descriptors", (void *)dev);
312 if (desc != RTE_DIM(*elts)) {
313 desc = RTE_DIM(*elts);
314 WARN("%p: increased number of descriptors in Tx queue %u"
315 " to the next power of two (%u)",
316 (void *)dev, idx, desc);
318 /* Allocate and initialize Tx queue. */
319 mlx4_zmallocv_socket("TXQ", vec, RTE_DIM(vec), socket);
321 ERROR("%p: unable to allocate queue index %u",
336 * Request send completion every MLX4_PMD_TX_PER_COMP_REQ
337 * packets or at least 4 times per ring.
340 RTE_MIN(MLX4_PMD_TX_PER_COMP_REQ, desc / 4),
342 RTE_MIN(MLX4_PMD_TX_PER_COMP_REQ, desc / 4),
343 .csum = priv->hw_csum &&
344 (conf->offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
345 DEV_TX_OFFLOAD_UDP_CKSUM |
346 DEV_TX_OFFLOAD_TCP_CKSUM)),
347 .csum_l2tun = priv->hw_csum_l2tun &&
349 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM),
350 /* Enable Tx loopback for VF devices. */
352 .bounce_buf = bounce_buf,
354 txq->cq = mlx4_glue->create_cq(priv->ctx, desc, NULL, NULL, 0);
357 ERROR("%p: CQ creation failure: %s",
358 (void *)dev, strerror(rte_errno));
361 qp_init_attr = (struct ibv_qp_init_attr){
366 RTE_MIN(priv->device_attr.max_qp_wr, desc),
368 .max_inline_data = MLX4_PMD_MAX_INLINE,
370 .qp_type = IBV_QPT_RAW_PACKET,
371 /* No completion events must occur by default. */
374 txq->qp = mlx4_glue->create_qp(priv->pd, &qp_init_attr);
376 rte_errno = errno ? errno : EINVAL;
377 ERROR("%p: QP creation failure: %s",
378 (void *)dev, strerror(rte_errno));
381 txq->max_inline = qp_init_attr.cap.max_inline_data;
382 ret = mlx4_glue->modify_qp
384 &(struct ibv_qp_attr){
385 .qp_state = IBV_QPS_INIT,
386 .port_num = priv->port,
388 IBV_QP_STATE | IBV_QP_PORT);
391 ERROR("%p: QP state to IBV_QPS_INIT failed: %s",
392 (void *)dev, strerror(rte_errno));
395 ret = mlx4_glue->modify_qp
397 &(struct ibv_qp_attr){
398 .qp_state = IBV_QPS_RTR,
403 ERROR("%p: QP state to IBV_QPS_RTR failed: %s",
404 (void *)dev, strerror(rte_errno));
407 ret = mlx4_glue->modify_qp
409 &(struct ibv_qp_attr){
410 .qp_state = IBV_QPS_RTS,
415 ERROR("%p: QP state to IBV_QPS_RTS failed: %s",
416 (void *)dev, strerror(rte_errno));
419 /* Retrieve device queue information. */
420 mlxdv.cq.in = txq->cq;
421 mlxdv.cq.out = &dv_cq;
422 mlxdv.qp.in = txq->qp;
423 mlxdv.qp.out = &dv_qp;
424 ret = mlx4_glue->dv_init_obj(&mlxdv, MLX4DV_OBJ_QP | MLX4DV_OBJ_CQ);
427 ERROR("%p: failed to obtain information needed for"
428 " accessing the device queues", (void *)dev);
431 mlx4_txq_fill_dv_obj_info(txq, &mlxdv);
432 /* Save first wqe pointer in the first element. */
433 (&(*txq->elts)[0])->wqe =
434 (volatile struct mlx4_wqe_ctrl_seg *)txq->msq.buf;
435 /* Pre-register known mempools. */
436 rte_mempool_walk(mlx4_txq_mp2mr_iter, txq);
437 DEBUG("%p: adding Tx queue %p to list", (void *)dev, (void *)txq);
438 dev->data->tx_queues[idx] = txq;
441 dev->data->tx_queues[idx] = NULL;
443 mlx4_tx_queue_release(txq);
445 assert(rte_errno > 0);
450 * DPDK callback to release a Tx queue.
453 * Generic Tx queue pointer.
456 mlx4_tx_queue_release(void *dpdk_txq)
458 struct txq *txq = (struct txq *)dpdk_txq;
465 for (i = 0; i != priv->dev->data->nb_tx_queues; ++i)
466 if (priv->dev->data->tx_queues[i] == txq) {
467 DEBUG("%p: removing Tx queue %p from list",
468 (void *)priv->dev, (void *)txq);
469 priv->dev->data->tx_queues[i] = NULL;
472 mlx4_txq_free_elts(txq);
474 claim_zero(mlx4_glue->destroy_qp(txq->qp));
476 claim_zero(mlx4_glue->destroy_cq(txq->cq));
477 for (i = 0; i != RTE_DIM(txq->mp2mr); ++i) {
478 if (!txq->mp2mr[i].mp)
480 assert(txq->mp2mr[i].mr);
481 mlx4_mr_put(txq->mp2mr[i].mr);