1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2020 Mellanox Technologies, Ltd
13 #include <linux/rtnetlink.h>
14 #include <linux/sockios.h>
15 #include <linux/ethtool.h>
18 #include <rte_malloc.h>
19 #include <ethdev_driver.h>
20 #include <ethdev_pci.h>
22 #include <rte_bus_pci.h>
23 #include <rte_bus_auxiliary.h>
24 #include <rte_common.h>
25 #include <rte_kvargs.h>
26 #include <rte_rwlock.h>
27 #include <rte_spinlock.h>
28 #include <rte_string_fns.h>
29 #include <rte_alarm.h>
30 #include <rte_eal_paging.h>
32 #include <mlx5_glue.h>
33 #include <mlx5_devx_cmds.h>
34 #include <mlx5_common.h>
35 #include <mlx5_common_mp.h>
36 #include <mlx5_common_mr.h>
37 #include <mlx5_malloc.h>
39 #include "mlx5_defs.h"
41 #include "mlx5_common_os.h"
42 #include "mlx5_utils.h"
43 #include "mlx5_rxtx.h"
46 #include "mlx5_autoconf.h"
47 #include "mlx5_flow.h"
48 #include "rte_pmd_mlx5.h"
49 #include "mlx5_verbs.h"
51 #include "mlx5_devx.h"
53 #ifndef HAVE_IBV_MLX5_MOD_MPW
54 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
55 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
58 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
59 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
62 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
64 /* Spinlock for mlx5_shared_data allocation. */
65 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
67 /* Process local data for secondary processes. */
68 static struct mlx5_local_data mlx5_local_data;
70 /* rte flow indexed pool configuration. */
71 static struct mlx5_indexed_pool_config icfg[] = {
73 .size = sizeof(struct rte_flow),
77 .malloc = mlx5_malloc,
80 .type = "ctl_flow_ipool",
83 .size = sizeof(struct rte_flow),
89 .malloc = mlx5_malloc,
91 .per_core_cache = 1 << 14,
92 .type = "rte_flow_ipool",
95 .size = sizeof(struct rte_flow),
101 .malloc = mlx5_malloc,
104 .type = "mcp_flow_ipool",
109 * Set the completion channel file descriptor interrupt as non-blocking.
112 * Pointer to RQ channel object, which includes the channel fd
115 * The file descriptor (representing the interrupt) used in this channel.
118 * 0 on successfully setting the fd to non-blocking, non-zero otherwise.
121 mlx5_os_set_nonblock_channel_fd(int fd)
125 flags = fcntl(fd, F_GETFL);
126 return fcntl(fd, F_SETFL, flags | O_NONBLOCK);
130 * Get mlx5 device attributes. The glue function query_device_ex() is called
131 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5
132 * device attributes from the glue out parameter.
135 * Pointer to mlx5 device.
138 * Pointer to mlx5 device attributes.
141 * 0 on success, a negative errno value otherwise and rte_errno is set.
144 mlx5_os_get_dev_attr(struct mlx5_common_device *cdev,
145 struct mlx5_dev_attr *device_attr)
148 struct ibv_context *ctx = cdev->ctx;
149 struct ibv_device_attr_ex attr_ex;
151 memset(device_attr, 0, sizeof(*device_attr));
152 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex);
157 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex;
158 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr;
159 device_attr->max_sge = attr_ex.orig_attr.max_sge;
160 device_attr->max_cq = attr_ex.orig_attr.max_cq;
161 device_attr->max_cqe = attr_ex.orig_attr.max_cqe;
162 device_attr->max_mr = attr_ex.orig_attr.max_mr;
163 device_attr->max_pd = attr_ex.orig_attr.max_pd;
164 device_attr->max_qp = attr_ex.orig_attr.max_qp;
165 device_attr->max_srq = attr_ex.orig_attr.max_srq;
166 device_attr->max_srq_wr = attr_ex.orig_attr.max_srq_wr;
167 device_attr->raw_packet_caps = attr_ex.raw_packet_caps;
168 device_attr->max_rwq_indirection_table_size =
169 attr_ex.rss_caps.max_rwq_indirection_table_size;
170 device_attr->max_tso = attr_ex.tso_caps.max_tso;
171 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts;
173 struct mlx5dv_context dv_attr = { .comp_mask = 0 };
174 #ifdef HAVE_IBV_MLX5_MOD_SWP
175 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
177 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
178 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
180 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
181 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
183 err = mlx5_glue->dv_query_device(ctx, &dv_attr);
189 device_attr->flags = dv_attr.flags;
190 device_attr->comp_mask = dv_attr.comp_mask;
191 #ifdef HAVE_IBV_MLX5_MOD_SWP
192 device_attr->sw_parsing_offloads =
193 dv_attr.sw_parsing_caps.sw_parsing_offloads;
195 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
196 device_attr->min_single_stride_log_num_of_bytes =
197 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes;
198 device_attr->max_single_stride_log_num_of_bytes =
199 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes;
200 device_attr->min_single_wqe_log_num_of_strides =
201 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides;
202 device_attr->max_single_wqe_log_num_of_strides =
203 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides;
204 device_attr->stride_supported_qpts =
205 dv_attr.striding_rq_caps.supported_qpts;
207 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
208 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps;
210 strlcpy(device_attr->fw_ver, attr_ex.orig_attr.fw_ver,
211 sizeof(device_attr->fw_ver));
217 * Detect misc5 support or not
220 * Device private data pointer
222 #ifdef HAVE_MLX5DV_DR
224 __mlx5_discovery_misc5_cap(struct mlx5_priv *priv)
226 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
227 /* Dummy VxLAN matcher to detect rdma-core misc5 cap
228 * Case: IPv4--->UDP--->VxLAN--->vni
231 struct mlx5_flow_dv_match_params matcher_mask;
236 uint32_t *tunnel_header_m;
237 struct mlx5dv_flow_matcher_attr dv_attr;
239 memset(&matcher_mask, 0, sizeof(matcher_mask));
240 matcher_mask.size = sizeof(matcher_mask.buf);
241 match_m = matcher_mask.buf;
242 headers_m = MLX5_ADDR_OF(fte_match_param, match_m, outer_headers);
243 misc5_m = MLX5_ADDR_OF(fte_match_param,
244 match_m, misc_parameters_5);
245 tunnel_header_m = (uint32_t *)
246 MLX5_ADDR_OF(fte_match_set_misc5,
247 misc5_m, tunnel_header_1);
248 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
249 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 4);
250 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
251 *tunnel_header_m = 0xffffff;
253 tbl = mlx5_glue->dr_create_flow_tbl(priv->sh->rx_domain, 1);
255 DRV_LOG(INFO, "No SW steering support");
258 dv_attr.type = IBV_FLOW_ATTR_NORMAL,
259 dv_attr.match_mask = (void *)&matcher_mask,
260 dv_attr.match_criteria_enable =
261 (1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT) |
262 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT);
263 dv_attr.priority = 3;
264 #ifdef HAVE_MLX5DV_DR_ESWITCH
266 if (priv->config.dv_esw_en) {
267 /* FDB enabled reg_c_0 */
268 dv_attr.match_criteria_enable |=
269 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT);
270 misc2_m = MLX5_ADDR_OF(fte_match_param,
271 match_m, misc_parameters_2);
272 MLX5_SET(fte_match_set_misc2, misc2_m,
273 metadata_reg_c_0, 0xffff);
276 matcher = mlx5_glue->dv_create_flow_matcher(priv->sh->cdev->ctx,
279 priv->sh->misc5_cap = 1;
280 mlx5_glue->dv_destroy_flow_matcher(matcher);
282 mlx5_glue->dr_destroy_flow_tbl(tbl);
290 * Initialize DR related data within private structure.
291 * Routine checks the reference counter and does actual
292 * resources creation/initialization only if counter is zero.
295 * Pointer to the private device data structure.
298 * Zero on success, positive error code otherwise.
301 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
303 struct mlx5_dev_ctx_shared *sh = priv->sh;
304 char s[MLX5_NAME_SIZE] __rte_unused;
307 MLX5_ASSERT(sh && sh->refcnt);
310 err = mlx5_alloc_table_hash_list(priv);
313 /* The resources below are only valid with DV support. */
314 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
315 /* Init port id action list. */
316 snprintf(s, sizeof(s), "%s_port_id_action_list", sh->ibdev_name);
317 sh->port_id_action_list = mlx5_list_create(s, sh, true,
318 flow_dv_port_id_create_cb,
319 flow_dv_port_id_match_cb,
320 flow_dv_port_id_remove_cb,
321 flow_dv_port_id_clone_cb,
322 flow_dv_port_id_clone_free_cb);
323 if (!sh->port_id_action_list)
325 /* Init push vlan action list. */
326 snprintf(s, sizeof(s), "%s_push_vlan_action_list", sh->ibdev_name);
327 sh->push_vlan_action_list = mlx5_list_create(s, sh, true,
328 flow_dv_push_vlan_create_cb,
329 flow_dv_push_vlan_match_cb,
330 flow_dv_push_vlan_remove_cb,
331 flow_dv_push_vlan_clone_cb,
332 flow_dv_push_vlan_clone_free_cb);
333 if (!sh->push_vlan_action_list)
335 /* Init sample action list. */
336 snprintf(s, sizeof(s), "%s_sample_action_list", sh->ibdev_name);
337 sh->sample_action_list = mlx5_list_create(s, sh, true,
338 flow_dv_sample_create_cb,
339 flow_dv_sample_match_cb,
340 flow_dv_sample_remove_cb,
341 flow_dv_sample_clone_cb,
342 flow_dv_sample_clone_free_cb);
343 if (!sh->sample_action_list)
345 /* Init dest array action list. */
346 snprintf(s, sizeof(s), "%s_dest_array_list", sh->ibdev_name);
347 sh->dest_array_list = mlx5_list_create(s, sh, true,
348 flow_dv_dest_array_create_cb,
349 flow_dv_dest_array_match_cb,
350 flow_dv_dest_array_remove_cb,
351 flow_dv_dest_array_clone_cb,
352 flow_dv_dest_array_clone_free_cb);
353 if (!sh->dest_array_list)
355 /* Init shared flex parsers list, no need lcore_share */
356 snprintf(s, sizeof(s), "%s_flex_parsers_list", sh->ibdev_name);
357 sh->flex_parsers_dv = mlx5_list_create(s, sh, false,
358 mlx5_flex_parser_create_cb,
359 mlx5_flex_parser_match_cb,
360 mlx5_flex_parser_remove_cb,
361 mlx5_flex_parser_clone_cb,
362 mlx5_flex_parser_clone_free_cb);
363 if (!sh->flex_parsers_dv)
366 #ifdef HAVE_MLX5DV_DR
369 /* Reference counter is zero, we should initialize structures. */
370 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx,
371 MLX5DV_DR_DOMAIN_TYPE_NIC_RX);
373 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed");
377 sh->rx_domain = domain;
378 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx,
379 MLX5DV_DR_DOMAIN_TYPE_NIC_TX);
381 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed");
385 sh->tx_domain = domain;
386 #ifdef HAVE_MLX5DV_DR_ESWITCH
387 if (priv->config.dv_esw_en) {
388 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx,
389 MLX5DV_DR_DOMAIN_TYPE_FDB);
391 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed");
395 sh->fdb_domain = domain;
398 * The drop action is just some dummy placeholder in rdma-core. It
399 * does not belong to domains and has no any attributes, and, can be
400 * shared by the entire device.
402 sh->dr_drop_action = mlx5_glue->dr_create_flow_action_drop();
403 if (!sh->dr_drop_action) {
404 DRV_LOG(ERR, "FDB mlx5dv_dr_create_flow_action_drop");
409 if (!sh->tunnel_hub && priv->config.dv_miss_info)
410 err = mlx5_alloc_tunnel_hub(sh);
412 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err);
415 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) {
416 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1);
417 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1);
419 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1);
421 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan();
422 if (!priv->config.allow_duplicate_pattern) {
423 #ifndef HAVE_MLX5_DR_ALLOW_DUPLICATE
424 DRV_LOG(WARNING, "Disallow duplicate pattern is not supported - maybe old rdma-core version?");
426 mlx5_glue->dr_allow_duplicate_rules(sh->rx_domain, 0);
427 mlx5_glue->dr_allow_duplicate_rules(sh->tx_domain, 0);
429 mlx5_glue->dr_allow_duplicate_rules(sh->fdb_domain, 0);
432 __mlx5_discovery_misc5_cap(priv);
433 #endif /* HAVE_MLX5DV_DR */
434 sh->default_miss_action =
435 mlx5_glue->dr_create_flow_action_default_miss();
436 if (!sh->default_miss_action)
437 DRV_LOG(WARNING, "Default miss action is not supported.");
438 LIST_INIT(&sh->shared_rxqs);
441 /* Rollback the created objects. */
443 mlx5_glue->dr_destroy_domain(sh->rx_domain);
444 sh->rx_domain = NULL;
447 mlx5_glue->dr_destroy_domain(sh->tx_domain);
448 sh->tx_domain = NULL;
450 if (sh->fdb_domain) {
451 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
452 sh->fdb_domain = NULL;
454 if (sh->dr_drop_action) {
455 mlx5_glue->destroy_flow_action(sh->dr_drop_action);
456 sh->dr_drop_action = NULL;
458 if (sh->pop_vlan_action) {
459 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
460 sh->pop_vlan_action = NULL;
462 if (sh->encaps_decaps) {
463 mlx5_hlist_destroy(sh->encaps_decaps);
464 sh->encaps_decaps = NULL;
466 if (sh->modify_cmds) {
467 mlx5_hlist_destroy(sh->modify_cmds);
468 sh->modify_cmds = NULL;
471 /* tags should be destroyed with flow before. */
472 mlx5_hlist_destroy(sh->tag_table);
473 sh->tag_table = NULL;
475 if (sh->tunnel_hub) {
476 mlx5_release_tunnel_hub(sh, priv->dev_port);
477 sh->tunnel_hub = NULL;
479 mlx5_free_table_hash_list(priv);
480 if (sh->port_id_action_list) {
481 mlx5_list_destroy(sh->port_id_action_list);
482 sh->port_id_action_list = NULL;
484 if (sh->push_vlan_action_list) {
485 mlx5_list_destroy(sh->push_vlan_action_list);
486 sh->push_vlan_action_list = NULL;
488 if (sh->sample_action_list) {
489 mlx5_list_destroy(sh->sample_action_list);
490 sh->sample_action_list = NULL;
492 if (sh->dest_array_list) {
493 mlx5_list_destroy(sh->dest_array_list);
494 sh->dest_array_list = NULL;
500 * Destroy DR related data within private structure.
503 * Pointer to the private device data structure.
506 mlx5_os_free_shared_dr(struct mlx5_priv *priv)
508 struct mlx5_dev_ctx_shared *sh = priv->sh;
510 MLX5_ASSERT(sh && sh->refcnt);
513 MLX5_ASSERT(LIST_EMPTY(&sh->shared_rxqs));
514 #ifdef HAVE_MLX5DV_DR
516 mlx5_glue->dr_destroy_domain(sh->rx_domain);
517 sh->rx_domain = NULL;
520 mlx5_glue->dr_destroy_domain(sh->tx_domain);
521 sh->tx_domain = NULL;
523 #ifdef HAVE_MLX5DV_DR_ESWITCH
524 if (sh->fdb_domain) {
525 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
526 sh->fdb_domain = NULL;
528 if (sh->dr_drop_action) {
529 mlx5_glue->destroy_flow_action(sh->dr_drop_action);
530 sh->dr_drop_action = NULL;
533 if (sh->pop_vlan_action) {
534 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
535 sh->pop_vlan_action = NULL;
537 #endif /* HAVE_MLX5DV_DR */
538 if (sh->default_miss_action)
539 mlx5_glue->destroy_flow_action
540 (sh->default_miss_action);
541 if (sh->encaps_decaps) {
542 mlx5_hlist_destroy(sh->encaps_decaps);
543 sh->encaps_decaps = NULL;
545 if (sh->modify_cmds) {
546 mlx5_hlist_destroy(sh->modify_cmds);
547 sh->modify_cmds = NULL;
550 /* tags should be destroyed with flow before. */
551 mlx5_hlist_destroy(sh->tag_table);
552 sh->tag_table = NULL;
554 if (sh->tunnel_hub) {
555 mlx5_release_tunnel_hub(sh, priv->dev_port);
556 sh->tunnel_hub = NULL;
558 mlx5_free_table_hash_list(priv);
559 if (sh->port_id_action_list) {
560 mlx5_list_destroy(sh->port_id_action_list);
561 sh->port_id_action_list = NULL;
563 if (sh->push_vlan_action_list) {
564 mlx5_list_destroy(sh->push_vlan_action_list);
565 sh->push_vlan_action_list = NULL;
567 if (sh->sample_action_list) {
568 mlx5_list_destroy(sh->sample_action_list);
569 sh->sample_action_list = NULL;
571 if (sh->dest_array_list) {
572 mlx5_list_destroy(sh->dest_array_list);
573 sh->dest_array_list = NULL;
578 * Initialize shared data between primary and secondary process.
580 * A memzone is reserved by primary process and secondary processes attach to
584 * 0 on success, a negative errno value otherwise and rte_errno is set.
587 mlx5_init_shared_data(void)
589 const struct rte_memzone *mz;
592 rte_spinlock_lock(&mlx5_shared_data_lock);
593 if (mlx5_shared_data == NULL) {
594 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
595 /* Allocate shared memory. */
596 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
597 sizeof(*mlx5_shared_data),
601 "Cannot allocate mlx5 shared data");
605 mlx5_shared_data = mz->addr;
606 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
607 rte_spinlock_init(&mlx5_shared_data->lock);
609 /* Lookup allocated shared memory. */
610 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
613 "Cannot attach mlx5 shared data");
617 mlx5_shared_data = mz->addr;
618 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
622 rte_spinlock_unlock(&mlx5_shared_data_lock);
627 * PMD global initialization.
629 * Independent from individual device, this function initializes global
630 * per-PMD data structures distinguishing primary and secondary processes.
631 * Hence, each initialization is called once per a process.
634 * 0 on success, a negative errno value otherwise and rte_errno is set.
639 struct mlx5_shared_data *sd;
640 struct mlx5_local_data *ld = &mlx5_local_data;
643 if (mlx5_init_shared_data())
645 sd = mlx5_shared_data;
647 rte_spinlock_lock(&sd->lock);
648 switch (rte_eal_process_type()) {
649 case RTE_PROC_PRIMARY:
652 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
653 mlx5_mp_os_primary_handle);
656 sd->init_done = true;
658 case RTE_PROC_SECONDARY:
661 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
662 mlx5_mp_os_secondary_handle);
666 ld->init_done = true;
672 rte_spinlock_unlock(&sd->lock);
677 * DV flow counter mode detect and config.
680 * Pointer to rte_eth_dev structure.
684 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)
686 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
687 struct mlx5_priv *priv = dev->data->dev_private;
688 struct mlx5_dev_ctx_shared *sh = priv->sh;
689 struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr;
692 #ifndef HAVE_IBV_DEVX_ASYNC
696 if (!sh->cdev->config.devx || !priv->config.dv_flow_en ||
697 !hca_attr->flow_counters_dump ||
698 !(hca_attr->flow_counter_bulk_alloc_bitmap & 0x4) ||
699 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))
703 DRV_LOG(INFO, "Use fall-back DV counter management. Flow "
704 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.",
705 hca_attr->flow_counters_dump,
706 hca_attr->flow_counter_bulk_alloc_bitmap);
707 /* Initialize fallback mode only on the port initializes sh. */
709 sh->cmng.counter_fallback = fallback;
710 else if (fallback != sh->cmng.counter_fallback)
711 DRV_LOG(WARNING, "Port %d in sh has different fallback mode "
712 "with others:%d.", PORT_ID(priv), fallback);
717 * DR flow drop action support detect.
720 * Pointer to rte_eth_dev structure.
724 mlx5_flow_drop_action_config(struct rte_eth_dev *dev __rte_unused)
726 #ifdef HAVE_MLX5DV_DR
727 struct mlx5_priv *priv = dev->data->dev_private;
729 if (!priv->config.dv_flow_en || !priv->sh->dr_drop_action)
732 * DR supports drop action placeholder when it is supported;
733 * otherwise, use the queue drop action.
735 if (!priv->sh->drop_action_check_flag) {
736 if (!mlx5_flow_discover_dr_action_support(dev))
737 priv->sh->dr_drop_action_en = 1;
738 priv->sh->drop_action_check_flag = 1;
740 if (priv->sh->dr_drop_action_en)
741 priv->root_drop_action = priv->sh->dr_drop_action;
743 priv->root_drop_action = priv->drop_queue.hrxq->action;
748 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev)
750 struct mlx5_priv *priv = dev->data->dev_private;
751 void *ctx = priv->sh->cdev->ctx;
753 priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx);
754 if (!priv->q_counters) {
755 struct ibv_cq *cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
758 DRV_LOG(DEBUG, "Port %d queue counter object cannot be created "
759 "by DevX - fall-back to use the kernel driver global "
760 "queue counter.", dev->data->port_id);
761 /* Create WQ by kernel and query its queue counter ID. */
763 wq = mlx5_glue->create_wq(ctx,
764 &(struct ibv_wq_init_attr){
765 .wq_type = IBV_WQT_RQ,
768 .pd = priv->sh->cdev->pd,
772 /* Counter is assigned only on RDY state. */
773 int ret = mlx5_glue->modify_wq(wq,
774 &(struct ibv_wq_attr){
775 .attr_mask = IBV_WQ_ATTR_STATE,
776 .wq_state = IBV_WQS_RDY,
780 mlx5_devx_cmd_wq_query(wq,
781 &priv->counter_set_id);
782 claim_zero(mlx5_glue->destroy_wq(wq));
784 claim_zero(mlx5_glue->destroy_cq(cq));
787 priv->counter_set_id = priv->q_counters->id;
789 if (priv->counter_set_id == 0)
790 DRV_LOG(INFO, "Part of the port %d statistics will not be "
791 "available.", dev->data->port_id);
795 * Check if representor spawn info match devargs.
798 * Verbs device parameters (name, port, switch_info) to spawn.
800 * Device devargs to probe.
806 mlx5_representor_match(struct mlx5_dev_spawn_data *spawn,
807 struct rte_eth_devargs *eth_da)
809 struct mlx5_switch_info *switch_info = &spawn->info;
812 uint16_t repr_id = mlx5_representor_id_encode(switch_info,
815 switch (eth_da->type) {
816 case RTE_ETH_REPRESENTOR_SF:
817 if (!(spawn->info.port_name == -1 &&
818 switch_info->name_type ==
819 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) &&
820 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFSF) {
825 case RTE_ETH_REPRESENTOR_VF:
826 /* Allows HPF representor index -1 as exception. */
827 if (!(spawn->info.port_name == -1 &&
828 switch_info->name_type ==
829 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) &&
830 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFVF) {
835 case RTE_ETH_REPRESENTOR_NONE:
840 DRV_LOG(ERR, "unsupported representor type");
843 /* Check representor ID: */
844 for (p = 0; p < eth_da->nb_ports; ++p) {
845 if (spawn->pf_bond < 0) {
846 /* For non-LAG mode, allow and ignore pf. */
847 switch_info->pf_num = eth_da->ports[p];
848 repr_id = mlx5_representor_id_encode(switch_info,
851 for (f = 0; f < eth_da->nb_representor_ports; ++f) {
852 id = MLX5_REPRESENTOR_ID
853 (eth_da->ports[p], eth_da->type,
854 eth_da->representor_ports[f]);
864 * Spawn an Ethernet device from Verbs information.
867 * Backing DPDK device.
869 * Verbs device parameters (name, port, switch_info) to spawn.
871 * Device configuration parameters.
876 * A valid Ethernet device object on success, NULL otherwise and rte_errno
877 * is set. The following errors are defined:
879 * EBUSY: device is not supposed to be spawned.
880 * EEXIST: device is already spawned
882 static struct rte_eth_dev *
883 mlx5_dev_spawn(struct rte_device *dpdk_dev,
884 struct mlx5_dev_spawn_data *spawn,
885 struct mlx5_dev_config *config,
886 struct rte_eth_devargs *eth_da)
888 const struct mlx5_switch_info *switch_info = &spawn->info;
889 struct mlx5_dev_ctx_shared *sh = NULL;
890 struct mlx5_hca_attr *hca_attr = &spawn->cdev->config.hca_attr;
891 struct ibv_port_attr port_attr = { .state = IBV_PORT_NOP };
892 struct rte_eth_dev *eth_dev = NULL;
893 struct mlx5_priv *priv = NULL;
895 unsigned int hw_padding = 0;
897 unsigned int mpls_en = 0;
898 unsigned int swp = 0;
899 unsigned int mprq = 0;
900 struct rte_ether_addr mac;
901 char name[RTE_ETH_NAME_MAX_LEN];
902 int own_domain_id = 0;
904 struct mlx5_port_info vport_info = { .query_flags = 0 };
908 /* Determine if this port representor is supposed to be spawned. */
909 if (switch_info->representor && dpdk_dev->devargs &&
910 !mlx5_representor_match(spawn, eth_da))
912 /* Build device name. */
913 if (spawn->pf_bond < 0) {
915 if (!switch_info->representor)
916 strlcpy(name, dpdk_dev->name, sizeof(name));
918 err = snprintf(name, sizeof(name), "%s_representor_%s%u",
920 switch_info->name_type ==
921 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf",
922 switch_info->port_name);
924 /* Bonding device. */
925 if (!switch_info->representor) {
926 err = snprintf(name, sizeof(name), "%s_%s",
927 dpdk_dev->name, spawn->phys_dev_name);
929 err = snprintf(name, sizeof(name), "%s_%s_representor_c%dpf%d%s%u",
930 dpdk_dev->name, spawn->phys_dev_name,
931 switch_info->ctrl_num,
933 switch_info->name_type ==
934 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf",
935 switch_info->port_name);
938 if (err >= (int)sizeof(name))
939 DRV_LOG(WARNING, "device name overflow %s", name);
940 /* check if the device is already spawned */
941 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
945 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
946 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
947 struct mlx5_mp_id mp_id;
949 eth_dev = rte_eth_dev_attach_secondary(name);
950 if (eth_dev == NULL) {
951 DRV_LOG(ERR, "can not attach rte ethdev");
955 eth_dev->device = dpdk_dev;
956 eth_dev->dev_ops = &mlx5_dev_sec_ops;
957 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status;
958 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status;
959 err = mlx5_proc_priv_init(eth_dev);
962 mlx5_mp_id_init(&mp_id, eth_dev->data->port_id);
963 /* Receive command fd from primary process */
964 err = mlx5_mp_req_verbs_cmd_fd(&mp_id);
967 /* Remap UAR for Tx queues. */
968 err = mlx5_tx_uar_init_secondary(eth_dev, err);
972 * Ethdev pointer is still required as input since
973 * the primary device is not accessible from the
976 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
977 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
980 mlx5_dev_close(eth_dev);
983 /* Process parameters. */
984 err = mlx5_args(config, dpdk_dev->devargs);
986 DRV_LOG(ERR, "failed to process device arguments: %s",
987 strerror(rte_errno));
990 sh = mlx5_alloc_shared_dev_ctx(spawn, config);
993 /* Update final values for devargs before check sibling config. */
994 if (config->dv_miss_info) {
995 if (switch_info->master || switch_info->representor)
996 config->dv_xmeta_en = MLX5_XMETA_MODE_META16;
998 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR)
999 if (config->dv_flow_en) {
1000 DRV_LOG(WARNING, "DV flow is not supported.");
1001 config->dv_flow_en = 0;
1004 #ifdef HAVE_MLX5DV_DR_ESWITCH
1005 if (!(hca_attr->eswitch_manager && config->dv_flow_en &&
1006 (switch_info->representor || switch_info->master)))
1007 config->dv_esw_en = 0;
1009 config->dv_esw_en = 0;
1011 if (!config->dv_esw_en &&
1012 config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1014 "Metadata mode %u is not supported (no E-Switch).",
1015 config->dv_xmeta_en);
1016 config->dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
1018 /* Check sibling device configurations. */
1019 err = mlx5_dev_check_sibling_config(sh, config, dpdk_dev);
1022 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR
1023 config->dest_tir = 1;
1026 * Multi-packet send is supported by ConnectX-4 Lx PF as well
1027 * as all ConnectX-5 devices.
1029 if (sh->device_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
1030 if (sh->device_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
1031 DRV_LOG(DEBUG, "enhanced MPW is supported");
1032 mps = MLX5_MPW_ENHANCED;
1034 DRV_LOG(DEBUG, "MPW is supported");
1038 DRV_LOG(DEBUG, "MPW isn't supported");
1039 mps = MLX5_MPW_DISABLED;
1041 #ifdef HAVE_IBV_MLX5_MOD_SWP
1042 if (sh->device_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
1043 swp = sh->device_attr.sw_parsing_offloads;
1044 DRV_LOG(DEBUG, "SWP support: %u", swp);
1046 config->swp = swp & (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |
1047 MLX5_SW_PARSING_TSO_CAP);
1048 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1049 if (sh->device_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
1050 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
1051 sh->device_attr.min_single_stride_log_num_of_bytes);
1052 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
1053 sh->device_attr.max_single_stride_log_num_of_bytes);
1054 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
1055 sh->device_attr.min_single_wqe_log_num_of_strides);
1056 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
1057 sh->device_attr.max_single_wqe_log_num_of_strides);
1058 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
1059 sh->device_attr.stride_supported_qpts);
1060 DRV_LOG(DEBUG, "\tmin_stride_wqe_log_size: %d",
1061 config->mprq.log_min_stride_wqe_size);
1062 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
1064 config->mprq.log_min_stride_size =
1065 sh->device_attr.min_single_stride_log_num_of_bytes;
1066 config->mprq.log_max_stride_size =
1067 sh->device_attr.max_single_stride_log_num_of_bytes;
1068 config->mprq.log_min_stride_num =
1069 sh->device_attr.min_single_wqe_log_num_of_strides;
1070 config->mprq.log_max_stride_num =
1071 sh->device_attr.max_single_wqe_log_num_of_strides;
1074 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1075 if (sh->device_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
1076 config->tunnel_en = sh->device_attr.tunnel_offloads_caps &
1077 (MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN |
1078 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE |
1079 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE);
1081 if (config->tunnel_en) {
1082 DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s",
1084 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN ? "[VXLAN]" : "",
1086 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE ? "[GRE]" : "",
1088 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE ? "[GENEVE]" : ""
1091 DRV_LOG(DEBUG, "tunnel offloading is not supported");
1095 "tunnel offloading disabled due to old OFED/rdma-core version");
1097 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
1098 mpls_en = ((sh->device_attr.tunnel_offloads_caps &
1099 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
1100 (sh->device_attr.tunnel_offloads_caps &
1101 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
1102 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
1103 mpls_en ? "" : "not ");
1105 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
1106 " old OFED/rdma-core version or firmware configuration");
1108 config->mpls_en = mpls_en;
1109 nl_rdma = mlx5_nl_init(NETLINK_RDMA);
1110 /* Check port status. */
1111 if (spawn->phys_port <= UINT8_MAX) {
1112 /* Legacy Verbs api only support u8 port number. */
1113 err = mlx5_glue->query_port(sh->cdev->ctx, spawn->phys_port,
1116 DRV_LOG(ERR, "port query failed: %s", strerror(err));
1119 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
1120 DRV_LOG(ERR, "port is not configured in Ethernet mode");
1124 } else if (nl_rdma >= 0) {
1125 /* IB doesn't allow more than 255 ports, must be Ethernet. */
1126 err = mlx5_nl_port_state(nl_rdma,
1127 spawn->phys_dev_name,
1130 DRV_LOG(INFO, "Failed to get netlink port state: %s",
1131 strerror(rte_errno));
1135 port_attr.state = (enum ibv_port_state)err;
1137 if (port_attr.state != IBV_PORT_ACTIVE)
1138 DRV_LOG(INFO, "port is not active: \"%s\" (%d)",
1139 mlx5_glue->port_state_str(port_attr.state),
1141 /* Allocate private eth device data. */
1142 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1144 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1146 DRV_LOG(ERR, "priv allocation failure");
1151 priv->dev_port = spawn->phys_port;
1152 priv->pci_dev = spawn->pci_dev;
1153 priv->mtu = RTE_ETHER_MTU;
1154 /* Some internal functions rely on Netlink sockets, open them now. */
1155 priv->nl_socket_rdma = nl_rdma;
1156 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
1157 priv->representor = !!switch_info->representor;
1158 priv->master = !!switch_info->master;
1159 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1160 priv->vport_meta_tag = 0;
1161 priv->vport_meta_mask = 0;
1162 priv->pf_bond = spawn->pf_bond;
1165 "dev_port=%u bus=%s pci=%s master=%d representor=%d pf_bond=%d\n",
1166 priv->dev_port, dpdk_dev->bus->name,
1167 priv->pci_dev ? priv->pci_dev->name : "NONE",
1168 priv->master, priv->representor, priv->pf_bond);
1171 * If we have E-Switch we should determine the vport attributes.
1172 * E-Switch may use either source vport field or reg_c[0] metadata
1173 * register to match on vport index. The engaged part of metadata
1174 * register is defined by mask.
1176 if (switch_info->representor || switch_info->master) {
1177 err = mlx5_glue->devx_port_query(sh->cdev->ctx,
1182 "Cannot query devx port %d on device %s",
1183 spawn->phys_port, spawn->phys_dev_name);
1184 vport_info.query_flags = 0;
1187 if (vport_info.query_flags & MLX5_PORT_QUERY_REG_C0) {
1188 priv->vport_meta_tag = vport_info.vport_meta_tag;
1189 priv->vport_meta_mask = vport_info.vport_meta_mask;
1190 if (!priv->vport_meta_mask) {
1192 "vport zero mask for port %d on bonding device %s",
1193 spawn->phys_port, spawn->phys_dev_name);
1197 if (priv->vport_meta_tag & ~priv->vport_meta_mask) {
1199 "Invalid vport tag for port %d on bonding device %s",
1200 spawn->phys_port, spawn->phys_dev_name);
1205 if (vport_info.query_flags & MLX5_PORT_QUERY_VPORT) {
1206 priv->vport_id = vport_info.vport_id;
1207 } else if (spawn->pf_bond >= 0 &&
1208 (switch_info->representor || switch_info->master)) {
1210 "Cannot deduce vport index for port %d on bonding device %s",
1211 spawn->phys_port, spawn->phys_dev_name);
1216 * Suppose vport index in compatible way. Kernel/rdma_core
1217 * support single E-Switch per PF configurations only and
1218 * vport_id field contains the vport index for associated VF,
1219 * which is deduced from representor port name.
1220 * For example, let's have the IB device port 10, it has
1221 * attached network device eth0, which has port name attribute
1222 * pf0vf2, we can deduce the VF number as 2, and set vport index
1223 * as 3 (2+1). This assigning schema should be changed if the
1224 * multiple E-Switch instances per PF configurations or/and PCI
1225 * subfunctions are added.
1227 priv->vport_id = switch_info->representor ?
1228 switch_info->port_name + 1 : -1;
1230 priv->representor_id = mlx5_representor_id_encode(switch_info,
1233 * Look for sibling devices in order to reuse their switch domain
1234 * if any, otherwise allocate one.
1236 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
1237 const struct mlx5_priv *opriv =
1238 rte_eth_devices[port_id].data->dev_private;
1241 opriv->sh != priv->sh ||
1243 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
1245 priv->domain_id = opriv->domain_id;
1246 DRV_LOG(DEBUG, "dev_port-%u inherit domain_id=%u\n",
1247 priv->dev_port, priv->domain_id);
1250 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1251 err = rte_eth_switch_domain_alloc(&priv->domain_id);
1254 DRV_LOG(ERR, "unable to allocate switch domain: %s",
1255 strerror(rte_errno));
1259 DRV_LOG(DEBUG, "dev_port-%u new domain_id=%u\n",
1260 priv->dev_port, priv->domain_id);
1262 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex &
1263 IBV_DEVICE_RAW_IP_CSUM);
1264 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
1265 (config->hw_csum ? "" : "not "));
1266 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
1267 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
1268 DRV_LOG(DEBUG, "counters are not supported");
1270 config->ind_table_max_size =
1271 sh->device_attr.max_rwq_indirection_table_size;
1273 * Remove this check once DPDK supports larger/variable
1274 * indirection tables.
1276 if (config->ind_table_max_size > (unsigned int)RTE_ETH_RSS_RETA_SIZE_512)
1277 config->ind_table_max_size = RTE_ETH_RSS_RETA_SIZE_512;
1278 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
1279 config->ind_table_max_size);
1280 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
1281 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
1282 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
1283 (config->hw_vlan_strip ? "" : "not "));
1284 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
1285 IBV_RAW_PACKET_CAP_SCATTER_FCS);
1286 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
1287 hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
1288 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
1289 hw_padding = !!(sh->device_attr.device_cap_flags_ex &
1290 IBV_DEVICE_PCI_WRITE_END_PADDING);
1292 if (config->hw_padding && !hw_padding) {
1293 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
1294 config->hw_padding = 0;
1295 } else if (config->hw_padding) {
1296 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
1298 config->tso = (sh->device_attr.max_tso > 0 &&
1299 (sh->device_attr.tso_supported_qpts &
1300 (1 << IBV_QPT_RAW_PACKET)));
1302 config->tso_max_payload_sz = sh->device_attr.max_tso;
1304 * MPW is disabled by default, while the Enhanced MPW is enabled
1307 if (config->mps == MLX5_ARG_UNSET)
1308 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
1311 config->mps = config->mps ? mps : MLX5_MPW_DISABLED;
1312 DRV_LOG(INFO, "%sMPS is %s",
1313 config->mps == MLX5_MPW_ENHANCED ? "enhanced " :
1314 config->mps == MLX5_MPW ? "legacy " : "",
1315 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
1316 if (sh->cdev->config.devx) {
1317 sh->steering_format_version = hca_attr->steering_format_version;
1318 /* Check for LRO support. */
1319 if (config->dest_tir && hca_attr->lro_cap &&
1320 config->dv_flow_en) {
1321 /* TBD check tunnel lro caps. */
1322 config->lro.supported = hca_attr->lro_cap;
1323 DRV_LOG(DEBUG, "Device supports LRO");
1325 * If LRO timeout is not configured by application,
1326 * use the minimal supported value.
1328 if (!config->lro.timeout)
1329 config->lro.timeout =
1330 hca_attr->lro_timer_supported_periods[0];
1331 DRV_LOG(DEBUG, "LRO session timeout set to %d usec",
1332 config->lro.timeout);
1333 DRV_LOG(DEBUG, "LRO minimal size of TCP segment "
1334 "required for coalescing is %d bytes",
1335 hca_attr->lro_min_mss_size);
1337 #if defined(HAVE_MLX5DV_DR) && \
1338 (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \
1339 defined(HAVE_MLX5_DR_CREATE_ACTION_ASO))
1340 if (hca_attr->qos.sup && hca_attr->qos.flow_meter_old &&
1341 config->dv_flow_en) {
1342 uint8_t reg_c_mask = hca_attr->qos.flow_meter_reg_c_ids;
1344 * Meter needs two REG_C's for color match and pre-sfx
1345 * flow match. Here get the REG_C for color match.
1346 * REG_C_0 and REG_C_1 is reserved for metadata feature.
1349 if (__builtin_popcount(reg_c_mask) < 1) {
1351 DRV_LOG(WARNING, "No available register for"
1355 * The meter color register is used by the
1356 * flow-hit feature as well.
1357 * The flow-hit feature must use REG_C_3
1358 * Prefer REG_C_3 if it is available.
1360 if (reg_c_mask & (1 << (REG_C_3 - REG_C_0)))
1361 priv->mtr_color_reg = REG_C_3;
1363 priv->mtr_color_reg = ffs(reg_c_mask)
1366 priv->mtr_reg_share = hca_attr->qos.flow_meter;
1367 DRV_LOG(DEBUG, "The REG_C meter uses is %d",
1368 priv->mtr_color_reg);
1371 if (hca_attr->qos.sup && hca_attr->qos.flow_meter_aso_sup) {
1372 uint32_t log_obj_size =
1373 rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
1375 hca_attr->qos.log_meter_aso_granularity &&
1377 hca_attr->qos.log_meter_aso_max_alloc)
1378 sh->meter_aso_en = 1;
1381 err = mlx5_aso_flow_mtrs_mng_init(priv->sh);
1387 if (hca_attr->flow.tunnel_header_0_1)
1388 sh->tunnel_header_0_1 = 1;
1390 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
1391 if (hca_attr->flow_hit_aso && priv->mtr_color_reg == REG_C_3) {
1392 sh->flow_hit_aso_en = 1;
1393 err = mlx5_flow_aso_age_mng_init(sh);
1398 DRV_LOG(DEBUG, "Flow Hit ASO is supported.");
1400 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
1401 #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO) && \
1402 defined(HAVE_MLX5_DR_ACTION_ASO_CT)
1403 if (hca_attr->ct_offload && priv->mtr_color_reg == REG_C_3) {
1404 err = mlx5_flow_aso_ct_mng_init(sh);
1409 DRV_LOG(DEBUG, "CT ASO is supported.");
1412 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */
1413 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE)
1414 if (hca_attr->log_max_ft_sampler_num > 0 &&
1415 config->dv_flow_en) {
1416 priv->sampler_en = 1;
1417 DRV_LOG(DEBUG, "Sampler enabled!");
1419 priv->sampler_en = 0;
1420 if (!hca_attr->log_max_ft_sampler_num)
1422 "No available register for sampler.");
1424 DRV_LOG(DEBUG, "DV flow is not supported!");
1428 if (config->cqe_comp && RTE_CACHE_LINE_SIZE == 128 &&
1429 !(sh->device_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) {
1430 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported");
1431 config->cqe_comp = 0;
1433 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX &&
1434 (!sh->cdev->config.devx || !hca_attr->mini_cqe_resp_flow_tag)) {
1435 DRV_LOG(WARNING, "Flow Tag CQE compression"
1436 " format isn't supported.");
1437 config->cqe_comp = 0;
1439 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX &&
1440 (!sh->cdev->config.devx || !hca_attr->mini_cqe_resp_l3_l4_tag)) {
1441 DRV_LOG(WARNING, "L3/L4 Header CQE compression"
1442 " format isn't supported.");
1443 config->cqe_comp = 0;
1445 DRV_LOG(DEBUG, "Rx CQE compression is %ssupported",
1446 config->cqe_comp ? "" : "not ");
1447 if (config->tx_pp) {
1448 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz",
1449 hca_attr->dev_freq_khz);
1450 DRV_LOG(DEBUG, "Packet pacing is %ssupported",
1451 hca_attr->qos.packet_pacing ? "" : "not ");
1452 DRV_LOG(DEBUG, "Cross channel ops are %ssupported",
1453 hca_attr->cross_channel ? "" : "not ");
1454 DRV_LOG(DEBUG, "WQE index ignore is %ssupported",
1455 hca_attr->wqe_index_ignore ? "" : "not ");
1456 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported",
1457 hca_attr->non_wire_sq ? "" : "not ");
1458 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)",
1459 hca_attr->log_max_static_sq_wq ? "" : "not ",
1460 hca_attr->log_max_static_sq_wq);
1461 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported",
1462 hca_attr->qos.wqe_rate_pp ? "" : "not ");
1463 if (!sh->cdev->config.devx) {
1464 DRV_LOG(ERR, "DevX is required for packet pacing");
1468 if (!hca_attr->qos.packet_pacing) {
1469 DRV_LOG(ERR, "Packet pacing is not supported");
1473 if (!hca_attr->cross_channel) {
1474 DRV_LOG(ERR, "Cross channel operations are"
1475 " required for packet pacing");
1479 if (!hca_attr->wqe_index_ignore) {
1480 DRV_LOG(ERR, "WQE index ignore feature is"
1481 " required for packet pacing");
1485 if (!hca_attr->non_wire_sq) {
1486 DRV_LOG(ERR, "Non-wire SQ feature is"
1487 " required for packet pacing");
1491 if (!hca_attr->log_max_static_sq_wq) {
1492 DRV_LOG(ERR, "Static WQE SQ feature is"
1493 " required for packet pacing");
1497 if (!hca_attr->qos.wqe_rate_pp) {
1498 DRV_LOG(ERR, "WQE rate mode is required"
1499 " for packet pacing");
1503 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET
1504 DRV_LOG(ERR, "DevX does not provide UAR offset,"
1505 " can't create queues for packet pacing");
1510 if (config->std_delay_drop || config->hp_delay_drop) {
1511 if (!hca_attr->rq_delay_drop) {
1512 config->std_delay_drop = 0;
1513 config->hp_delay_drop = 0;
1515 "dev_port-%u: Rxq delay drop is not supported",
1519 if (sh->cdev->config.devx)
1520 mlx5_rt_timestamp_config(sh, config, hca_attr);
1522 * If HW has bug working with tunnel packet decapsulation and
1523 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip
1524 * bit. Then RTE_ETH_RX_OFFLOAD_KEEP_CRC bit will not be set anymore.
1526 if (hca_attr->scatter_fcs_w_decap_disable && config->decap_en)
1527 config->hw_fcs_strip = 0;
1528 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
1529 (config->hw_fcs_strip ? "" : "not "));
1530 if (config->mprq.enabled && !mprq) {
1531 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
1532 config->mprq.enabled = 0;
1534 if (config->max_dump_files_num == 0)
1535 config->max_dump_files_num = 128;
1536 eth_dev = rte_eth_dev_allocate(name);
1537 if (eth_dev == NULL) {
1538 DRV_LOG(ERR, "can not allocate rte ethdev");
1542 if (priv->representor) {
1543 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
1544 eth_dev->data->representor_id = priv->representor_id;
1545 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
1546 struct mlx5_priv *opriv =
1547 rte_eth_devices[port_id].data->dev_private;
1550 opriv->domain_id == priv->domain_id &&
1551 opriv->sh == priv->sh) {
1552 eth_dev->data->backer_port_id = port_id;
1556 if (port_id >= RTE_MAX_ETHPORTS)
1557 eth_dev->data->backer_port_id = eth_dev->data->port_id;
1559 priv->mp_id.port_id = eth_dev->data->port_id;
1560 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
1562 * Store associated network device interface index. This index
1563 * is permanent throughout the lifetime of device. So, we may store
1564 * the ifindex here and use the cached value further.
1566 MLX5_ASSERT(spawn->ifindex);
1567 priv->if_index = spawn->ifindex;
1568 priv->lag_affinity_idx = sh->refcnt - 1;
1569 eth_dev->data->dev_private = priv;
1570 priv->dev_data = eth_dev->data;
1571 eth_dev->data->mac_addrs = priv->mac;
1572 eth_dev->device = dpdk_dev;
1573 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1574 /* Configure the first MAC address by default. */
1575 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
1577 "port %u cannot get MAC address, is mlx5_en"
1578 " loaded? (errno: %s)",
1579 eth_dev->data->port_id, strerror(rte_errno));
1584 "port %u MAC address is " RTE_ETHER_ADDR_PRT_FMT,
1585 eth_dev->data->port_id, RTE_ETHER_ADDR_BYTES(&mac));
1586 #ifdef RTE_LIBRTE_MLX5_DEBUG
1588 char ifname[MLX5_NAMESIZE];
1590 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
1591 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
1592 eth_dev->data->port_id, ifname);
1594 DRV_LOG(DEBUG, "port %u ifname is unknown",
1595 eth_dev->data->port_id);
1598 /* Get actual MTU if possible. */
1599 err = mlx5_get_mtu(eth_dev, &priv->mtu);
1604 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1606 /* Initialize burst functions to prevent crashes before link-up. */
1607 eth_dev->rx_pkt_burst = rte_eth_pkt_burst_dummy;
1608 eth_dev->tx_pkt_burst = rte_eth_pkt_burst_dummy;
1609 eth_dev->dev_ops = &mlx5_dev_ops;
1610 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status;
1611 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status;
1612 eth_dev->rx_queue_count = mlx5_rx_queue_count;
1613 /* Register MAC address. */
1614 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1615 if (config->vf && config->vf_nl_en)
1616 mlx5_nl_mac_addr_sync(priv->nl_socket_route,
1617 mlx5_ifindex(eth_dev),
1618 eth_dev->data->mac_addrs,
1619 MLX5_MAX_MAC_ADDRESSES);
1620 priv->ctrl_flows = 0;
1621 rte_spinlock_init(&priv->flow_list_lock);
1622 TAILQ_INIT(&priv->flow_meters);
1623 priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR);
1624 if (!priv->mtr_profile_tbl)
1626 /* Bring Ethernet device up. */
1627 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1628 eth_dev->data->port_id);
1629 mlx5_set_link_up(eth_dev);
1631 * Even though the interrupt handler is not installed yet,
1632 * interrupts will still trigger on the async_fd from
1633 * Verbs context returned by ibv_open_device().
1635 mlx5_link_update(eth_dev, 0);
1636 /* Detect minimal data bytes to inline. */
1637 mlx5_set_min_inline(spawn, config);
1638 /* Store device configuration on private structure. */
1639 priv->config = *config;
1640 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) {
1641 icfg[i].release_mem_en = !!config->reclaim_mode;
1642 if (config->reclaim_mode)
1643 icfg[i].per_core_cache = 0;
1644 priv->flows[i] = mlx5_ipool_create(&icfg[i]);
1645 if (!priv->flows[i])
1648 /* Create context for virtual machine VLAN workaround. */
1649 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex);
1650 if (config->dv_flow_en) {
1651 err = mlx5_alloc_shared_dr(priv);
1654 if (mlx5_flex_item_port_init(eth_dev) < 0)
1657 if (sh->cdev->config.devx && config->dv_flow_en && config->dest_tir) {
1658 priv->obj_ops = devx_obj_ops;
1659 mlx5_queue_counter_id_prepare(eth_dev);
1660 priv->obj_ops.lb_dummy_queue_create =
1661 mlx5_rxq_ibv_obj_dummy_lb_create;
1662 priv->obj_ops.lb_dummy_queue_release =
1663 mlx5_rxq_ibv_obj_dummy_lb_release;
1664 } else if (spawn->max_port > UINT8_MAX) {
1665 /* Verbs can't support ports larger than 255 by design. */
1666 DRV_LOG(ERR, "must enable DV and ESW when RDMA link ports > 255");
1670 priv->obj_ops = ibv_obj_ops;
1672 if (config->tx_pp &&
1673 priv->obj_ops.txq_obj_new != mlx5_txq_devx_obj_new) {
1675 * HAVE_MLX5DV_DEVX_UAR_OFFSET is required to support
1676 * packet pacing and already checked above.
1677 * Hence, we should only make sure the SQs will be created
1678 * with DevX, not with Verbs.
1679 * Verbs allocates the SQ UAR on its own and it can't be shared
1680 * with Clock Queue UAR as required for Tx scheduling.
1682 DRV_LOG(ERR, "Verbs SQs, UAR can't be shared as required for packet pacing");
1686 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev);
1687 if (!priv->drop_queue.hrxq)
1689 /* Port representor shares the same max priority with pf port. */
1690 if (!priv->sh->flow_priority_check_flag) {
1691 /* Supported Verbs flow priority number detection. */
1692 err = mlx5_flow_discover_priorities(eth_dev);
1693 priv->sh->flow_max_priority = err;
1694 priv->sh->flow_priority_check_flag = 1;
1696 err = priv->sh->flow_max_priority;
1702 mlx5_set_metadata_mask(eth_dev);
1703 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
1704 !priv->sh->dv_regc0_mask) {
1705 DRV_LOG(ERR, "metadata mode %u is not supported "
1706 "(no metadata reg_c[0] is available)",
1707 priv->config.dv_xmeta_en);
1711 priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true,
1712 mlx5_hrxq_create_cb,
1714 mlx5_hrxq_remove_cb,
1716 mlx5_hrxq_clone_free_cb);
1719 rte_rwlock_init(&priv->ind_tbls_lock);
1720 /* Query availability of metadata reg_c's. */
1721 if (!priv->sh->metadata_regc_check_flag) {
1722 err = mlx5_flow_discover_mreg_c(eth_dev);
1728 if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
1730 "port %u extensive metadata register is not supported",
1731 eth_dev->data->port_id);
1732 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1733 DRV_LOG(ERR, "metadata mode %u is not supported "
1734 "(no metadata registers available)",
1735 priv->config.dv_xmeta_en);
1740 if (priv->config.dv_flow_en &&
1741 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
1742 mlx5_flow_ext_mreg_supported(eth_dev) &&
1743 priv->sh->dv_regc0_mask) {
1744 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME,
1745 MLX5_FLOW_MREG_HTABLE_SZ,
1746 false, true, eth_dev,
1747 flow_dv_mreg_create_cb,
1748 flow_dv_mreg_match_cb,
1749 flow_dv_mreg_remove_cb,
1750 flow_dv_mreg_clone_cb,
1751 flow_dv_mreg_clone_free_cb);
1752 if (!priv->mreg_cp_tbl) {
1757 rte_spinlock_init(&priv->shared_act_sl);
1758 mlx5_flow_counter_mode_config(eth_dev);
1759 mlx5_flow_drop_action_config(eth_dev);
1760 if (priv->config.dv_flow_en)
1761 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
1765 if (priv->mreg_cp_tbl)
1766 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1768 mlx5_os_free_shared_dr(priv);
1769 if (priv->nl_socket_route >= 0)
1770 close(priv->nl_socket_route);
1771 if (priv->vmwa_context)
1772 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1773 if (eth_dev && priv->drop_queue.hrxq)
1774 mlx5_drop_action_destroy(eth_dev);
1775 if (priv->mtr_profile_tbl)
1776 mlx5_l3t_destroy(priv->mtr_profile_tbl);
1778 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1780 mlx5_list_destroy(priv->hrxqs);
1781 if (eth_dev && priv->flex_item_map)
1782 mlx5_flex_item_port_cleanup(eth_dev);
1784 if (eth_dev != NULL)
1785 eth_dev->data->dev_private = NULL;
1787 if (eth_dev != NULL) {
1788 /* mac_addrs must not be freed alone because part of
1791 eth_dev->data->mac_addrs = NULL;
1792 rte_eth_dev_release_port(eth_dev);
1795 mlx5_free_shared_dev_ctx(sh);
1798 MLX5_ASSERT(err > 0);
1804 * Comparison callback to sort device data.
1806 * This is meant to be used with qsort().
1809 * Pointer to pointer to first data object.
1811 * Pointer to pointer to second data object.
1814 * 0 if both objects are equal, less than 0 if the first argument is less
1815 * than the second, greater than 0 otherwise.
1818 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
1820 const struct mlx5_switch_info *si_a =
1821 &((const struct mlx5_dev_spawn_data *)a)->info;
1822 const struct mlx5_switch_info *si_b =
1823 &((const struct mlx5_dev_spawn_data *)b)->info;
1826 /* Master device first. */
1827 ret = si_b->master - si_a->master;
1830 /* Then representor devices. */
1831 ret = si_b->representor - si_a->representor;
1834 /* Unidentified devices come last in no specific order. */
1835 if (!si_a->representor)
1837 /* Order representors by name. */
1838 return si_a->port_name - si_b->port_name;
1842 * Match PCI information for possible slaves of bonding device.
1844 * @param[in] ibdev_name
1845 * Name of Infiniband device.
1846 * @param[in] pci_dev
1847 * Pointer to primary PCI address structure to match.
1848 * @param[in] nl_rdma
1849 * Netlink RDMA group socket handle.
1851 * Representor owner PF index.
1852 * @param[out] bond_info
1853 * Pointer to bonding information.
1856 * negative value if no bonding device found, otherwise
1857 * positive index of slave PF in bonding.
1860 mlx5_device_bond_pci_match(const char *ibdev_name,
1861 const struct rte_pci_addr *pci_dev,
1862 int nl_rdma, uint16_t owner,
1863 struct mlx5_bond_info *bond_info)
1865 char ifname[IF_NAMESIZE + 1];
1866 unsigned int ifindex;
1868 FILE *bond_file = NULL, *file;
1871 uint8_t cur_guid[32] = {0};
1872 uint8_t guid[32] = {0};
1875 * Try to get master device name. If something goes wrong suppose
1876 * the lack of kernel support and no bonding devices.
1878 memset(bond_info, 0, sizeof(*bond_info));
1881 if (!strstr(ibdev_name, "bond"))
1883 np = mlx5_nl_portnum(nl_rdma, ibdev_name);
1886 if (mlx5_get_device_guid(pci_dev, cur_guid, sizeof(cur_guid)) < 0)
1889 * The master device might not be on the predefined port(not on port
1890 * index 1, it is not guaranteed), we have to scan all Infiniband
1891 * device ports and find master.
1893 for (i = 1; i <= np; ++i) {
1894 /* Check whether Infiniband port is populated. */
1895 ifindex = mlx5_nl_ifindex(nl_rdma, ibdev_name, i);
1898 if (!if_indextoname(ifindex, ifname))
1900 /* Try to read bonding slave names from sysfs. */
1902 "/sys/class/net/%s/master/bonding/slaves", ifname);
1903 bond_file = fopen(slaves, "r");
1909 /* Use safe format to check maximal buffer length. */
1910 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE);
1911 while (fscanf(bond_file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) {
1912 char tmp_str[IF_NAMESIZE + 32];
1913 struct rte_pci_addr pci_addr;
1914 struct mlx5_switch_info info;
1917 /* Process slave interface names in the loop. */
1918 snprintf(tmp_str, sizeof(tmp_str),
1919 "/sys/class/net/%s", ifname);
1920 if (mlx5_get_pci_addr(tmp_str, &pci_addr)) {
1922 "Cannot get PCI address for netdev \"%s\".",
1926 /* Slave interface PCI address match found. */
1927 snprintf(tmp_str, sizeof(tmp_str),
1928 "/sys/class/net/%s/phys_port_name", ifname);
1929 file = fopen(tmp_str, "rb");
1932 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET;
1933 if (fscanf(file, "%32s", tmp_str) == 1)
1934 mlx5_translate_port_name(tmp_str, &info);
1936 /* Only process PF ports. */
1937 if (info.name_type != MLX5_PHYS_PORT_NAME_TYPE_LEGACY &&
1938 info.name_type != MLX5_PHYS_PORT_NAME_TYPE_UPLINK)
1940 /* Check max bonding member. */
1941 if (info.port_name >= MLX5_BOND_MAX_PORTS) {
1942 DRV_LOG(WARNING, "bonding index out of range, "
1943 "please increase MLX5_BOND_MAX_PORTS: %s",
1948 snprintf(tmp_str, sizeof(tmp_str),
1949 "/sys/class/net/%s/ifindex", ifname);
1950 file = fopen(tmp_str, "rb");
1953 ret = fscanf(file, "%u", &ifindex);
1957 /* Save bonding info. */
1958 strncpy(bond_info->ports[info.port_name].ifname, ifname,
1959 sizeof(bond_info->ports[0].ifname));
1960 bond_info->ports[info.port_name].pci_addr = pci_addr;
1961 bond_info->ports[info.port_name].ifindex = ifindex;
1962 bond_info->n_port++;
1964 * Under socket direct mode, bonding will use
1965 * system_image_guid as identification.
1966 * After OFED 5.4, guid is readable (ret >= 0) under sysfs.
1967 * All bonding members should have the same guid even if driver
1968 * is using PCIe BDF.
1970 ret = mlx5_get_device_guid(&pci_addr, guid, sizeof(guid));
1974 if (!memcmp(guid, cur_guid, sizeof(guid)) &&
1975 owner == info.port_name &&
1976 (owner != 0 || (owner == 0 &&
1977 !rte_pci_addr_cmp(pci_dev, &pci_addr))))
1978 pf = info.port_name;
1979 } else if (pci_dev->domain == pci_addr.domain &&
1980 pci_dev->bus == pci_addr.bus &&
1981 pci_dev->devid == pci_addr.devid &&
1982 ((pci_dev->function == 0 &&
1983 pci_dev->function + owner == pci_addr.function) ||
1984 (pci_dev->function == owner &&
1985 pci_addr.function == owner)))
1986 pf = info.port_name;
1989 /* Get bond interface info */
1990 ret = mlx5_sysfs_bond_info(ifindex, &bond_info->ifindex,
1993 DRV_LOG(ERR, "unable to get bond info: %s",
1994 strerror(rte_errno));
1996 DRV_LOG(INFO, "PF device %u, bond device %u(%s)",
1997 ifindex, bond_info->ifindex, bond_info->ifname);
1999 if (owner == 0 && pf != 0) {
2000 DRV_LOG(INFO, "PCIe instance %04x:%02x:%02x.%x isn't bonding owner",
2001 pci_dev->domain, pci_dev->bus, pci_dev->devid,
2008 mlx5_os_config_default(struct mlx5_dev_config *config,
2009 struct mlx5_common_dev_config *cconf)
2011 memset(config, 0, sizeof(*config));
2012 config->mps = MLX5_ARG_UNSET;
2013 config->cqe_comp = 1;
2014 config->rx_vec_en = 1;
2015 config->txq_inline_max = MLX5_ARG_UNSET;
2016 config->txq_inline_min = MLX5_ARG_UNSET;
2017 config->txq_inline_mpw = MLX5_ARG_UNSET;
2018 config->txqs_inline = MLX5_ARG_UNSET;
2019 config->vf_nl_en = 1;
2020 config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN;
2021 config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS;
2022 config->mprq.log_min_stride_wqe_size = cconf->devx ?
2023 cconf->hca_attr.log_min_stride_wqe_sz :
2024 MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE;
2025 config->mprq.log_stride_num = MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM;
2026 config->dv_esw_en = 1;
2027 config->dv_flow_en = 1;
2028 config->decap_en = 1;
2029 config->log_hp_size = MLX5_ARG_UNSET;
2030 config->allow_duplicate_pattern = 1;
2031 config->std_delay_drop = 0;
2032 config->hp_delay_drop = 0;
2036 * Register a PCI device within bonding.
2038 * This function spawns Ethernet devices out of a given PCI device and
2039 * bonding owner PF index.
2042 * Pointer to common mlx5 device structure.
2043 * @param[in] req_eth_da
2044 * Requested ethdev device argument.
2045 * @param[in] owner_id
2046 * Requested owner PF port ID within bonding device, default to 0.
2049 * 0 on success, a negative errno value otherwise and rte_errno is set.
2052 mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev,
2053 struct rte_eth_devargs *req_eth_da,
2056 struct ibv_device **ibv_list;
2058 * Number of found IB Devices matching with requested PCI BDF.
2059 * nd != 1 means there are multiple IB devices over the same
2060 * PCI device and we have representors and master.
2062 unsigned int nd = 0;
2064 * Number of found IB device Ports. nd = 1 and np = 1..n means
2065 * we have the single multiport IB device, and there may be
2066 * representors attached to some of found ports.
2068 unsigned int np = 0;
2070 * Number of DPDK ethernet devices to Spawn - either over
2071 * multiple IB devices or multiple ports of single IB device.
2072 * Actually this is the number of iterations to spawn.
2074 unsigned int ns = 0;
2077 * < 0 - no bonding device (single one)
2078 * >= 0 - bonding device (value is slave PF index)
2081 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev);
2082 struct mlx5_dev_spawn_data *list = NULL;
2083 struct mlx5_dev_config dev_config;
2084 struct rte_eth_devargs eth_da = *req_eth_da;
2085 struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */
2086 struct mlx5_bond_info bond_info;
2090 ibv_list = mlx5_glue->get_device_list(&ret);
2092 rte_errno = errno ? errno : ENOSYS;
2093 DRV_LOG(ERR, "Cannot list devices, is ib_uverbs loaded?");
2097 * First scan the list of all Infiniband devices to find
2098 * matching ones, gathering into the list.
2100 struct ibv_device *ibv_match[ret + 1];
2101 int nl_route = mlx5_nl_init(NETLINK_ROUTE);
2102 int nl_rdma = mlx5_nl_init(NETLINK_RDMA);
2106 struct rte_pci_addr pci_addr;
2108 DRV_LOG(DEBUG, "Checking device \"%s\"", ibv_list[ret]->name);
2109 bd = mlx5_device_bond_pci_match(ibv_list[ret]->name, &owner_pci,
2110 nl_rdma, owner_id, &bond_info);
2113 * Bonding device detected. Only one match is allowed,
2114 * the bonding is supported over multi-port IB device,
2115 * there should be no matches on representor PCI
2116 * functions or non VF LAG bonding devices with
2117 * specified address.
2121 "multiple PCI match on bonding device"
2122 "\"%s\" found", ibv_list[ret]->name);
2127 /* Amend owner pci address if owner PF ID specified. */
2128 if (eth_da.nb_representor_ports)
2129 owner_pci.function += owner_id;
2131 "PCI information matches for slave %d bonding device \"%s\"",
2132 bd, ibv_list[ret]->name);
2133 ibv_match[nd++] = ibv_list[ret];
2136 /* Bonding device not found. */
2137 if (mlx5_get_pci_addr(ibv_list[ret]->ibdev_path,
2140 if (owner_pci.domain != pci_addr.domain ||
2141 owner_pci.bus != pci_addr.bus ||
2142 owner_pci.devid != pci_addr.devid ||
2143 owner_pci.function != pci_addr.function)
2145 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
2146 ibv_list[ret]->name);
2147 ibv_match[nd++] = ibv_list[ret];
2150 ibv_match[nd] = NULL;
2152 /* No device matches, just complain and bail out. */
2154 "No Verbs device matches PCI device " PCI_PRI_FMT ","
2155 " are kernel drivers loaded?",
2156 owner_pci.domain, owner_pci.bus,
2157 owner_pci.devid, owner_pci.function);
2164 * Found single matching device may have multiple ports.
2165 * Each port may be representor, we have to check the port
2166 * number and check the representors existence.
2169 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
2172 "Cannot get IB device \"%s\" ports number.",
2173 ibv_match[0]->name);
2174 if (bd >= 0 && !np) {
2175 DRV_LOG(ERR, "Cannot get ports for bonding device.");
2181 /* Now we can determine the maximal amount of devices to be spawned. */
2182 list = mlx5_malloc(MLX5_MEM_ZERO,
2183 sizeof(struct mlx5_dev_spawn_data) * (np ? np : nd),
2184 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
2186 DRV_LOG(ERR, "Spawn data array allocation failure.");
2191 if (bd >= 0 || np > 1) {
2193 * Single IB device with multiple ports found,
2194 * it may be E-Switch master device and representors.
2195 * We have to perform identification through the ports.
2197 MLX5_ASSERT(nl_rdma >= 0);
2198 MLX5_ASSERT(ns == 0);
2199 MLX5_ASSERT(nd == 1);
2201 for (i = 1; i <= np; ++i) {
2202 list[ns].bond_info = &bond_info;
2203 list[ns].max_port = np;
2204 list[ns].phys_port = i;
2205 list[ns].phys_dev_name = ibv_match[0]->name;
2206 list[ns].eth_dev = NULL;
2207 list[ns].pci_dev = pci_dev;
2208 list[ns].cdev = cdev;
2209 list[ns].pf_bond = bd;
2210 list[ns].ifindex = mlx5_nl_ifindex(nl_rdma,
2213 if (!list[ns].ifindex) {
2215 * No network interface index found for the
2216 * specified port, it means there is no
2217 * representor on this port. It's OK,
2218 * there can be disabled ports, for example
2219 * if sriov_numvfs < sriov_totalvfs.
2225 ret = mlx5_nl_switch_info(nl_route,
2228 if (ret || (!list[ns].info.representor &&
2229 !list[ns].info.master)) {
2231 * We failed to recognize representors with
2232 * Netlink, let's try to perform the task
2235 ret = mlx5_sysfs_switch_info(list[ns].ifindex,
2238 if (!ret && bd >= 0) {
2239 switch (list[ns].info.name_type) {
2240 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK:
2243 * Force standalone bonding
2244 * device for ROCE LAG
2247 list[ns].info.master = 0;
2248 list[ns].info.representor = 0;
2250 if (list[ns].info.port_name == bd)
2253 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF:
2255 case MLX5_PHYS_PORT_NAME_TYPE_PFVF:
2257 case MLX5_PHYS_PORT_NAME_TYPE_PFSF:
2258 if (list[ns].info.pf_num == bd)
2266 if (!ret && (list[ns].info.representor ^
2267 list[ns].info.master))
2272 "Unable to recognize master/representors on the IB device with multiple ports.");
2279 * The existence of several matching entries (nd > 1) means
2280 * port representors have been instantiated. No existing Verbs
2281 * call nor sysfs entries can tell them apart, this can only
2282 * be done through Netlink calls assuming kernel drivers are
2283 * recent enough to support them.
2285 * In the event of identification failure through Netlink,
2286 * try again through sysfs, then:
2288 * 1. A single IB device matches (nd == 1) with single
2289 * port (np=0/1) and is not a representor, assume
2290 * no switch support.
2292 * 2. Otherwise no safe assumptions can be made;
2293 * complain louder and bail out.
2295 for (i = 0; i != nd; ++i) {
2296 memset(&list[ns].info, 0, sizeof(list[ns].info));
2297 list[ns].bond_info = NULL;
2298 list[ns].max_port = 1;
2299 list[ns].phys_port = 1;
2300 list[ns].phys_dev_name = ibv_match[i]->name;
2301 list[ns].eth_dev = NULL;
2302 list[ns].pci_dev = pci_dev;
2303 list[ns].cdev = cdev;
2304 list[ns].pf_bond = -1;
2305 list[ns].ifindex = 0;
2307 list[ns].ifindex = mlx5_nl_ifindex
2311 if (!list[ns].ifindex) {
2312 char ifname[IF_NAMESIZE];
2315 * Netlink failed, it may happen with old
2316 * ib_core kernel driver (before 4.16).
2317 * We can assume there is old driver because
2318 * here we are processing single ports IB
2319 * devices. Let's try sysfs to retrieve
2320 * the ifindex. The method works for
2321 * master device only.
2325 * Multiple devices found, assume
2326 * representors, can not distinguish
2327 * master/representor and retrieve
2328 * ifindex via sysfs.
2332 ret = mlx5_get_ifname_sysfs
2333 (ibv_match[i]->ibdev_path, ifname);
2336 if_nametoindex(ifname);
2337 if (!list[ns].ifindex) {
2339 * No network interface index found
2340 * for the specified device, it means
2341 * there it is neither representor
2349 ret = mlx5_nl_switch_info(nl_route,
2352 if (ret || (!list[ns].info.representor &&
2353 !list[ns].info.master)) {
2355 * We failed to recognize representors with
2356 * Netlink, let's try to perform the task
2359 ret = mlx5_sysfs_switch_info(list[ns].ifindex,
2362 if (!ret && (list[ns].info.representor ^
2363 list[ns].info.master)) {
2365 } else if ((nd == 1) &&
2366 !list[ns].info.representor &&
2367 !list[ns].info.master) {
2369 * Single IB device with one physical port and
2370 * attached network device.
2371 * May be SRIOV is not enabled or there is no
2374 DRV_LOG(INFO, "No E-Switch support detected.");
2381 "Unable to recognize master/representors on the multiple IB devices.");
2387 * New kernels may add the switch_id attribute for the case
2388 * there is no E-Switch and we wrongly recognized the only
2389 * device as master. Override this if there is the single
2390 * device with single port and new device name format present.
2393 list[0].info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) {
2394 list[0].info.master = 0;
2395 list[0].info.representor = 0;
2400 * Sort list to probe devices in natural order for users convenience
2401 * (i.e. master first, then representors from lowest to highest ID).
2403 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
2404 if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) {
2405 /* Set devargs default values. */
2406 if (eth_da.nb_mh_controllers == 0) {
2407 eth_da.nb_mh_controllers = 1;
2408 eth_da.mh_controllers[0] = 0;
2410 if (eth_da.nb_ports == 0 && ns > 0) {
2411 if (list[0].pf_bond >= 0 && list[0].info.representor)
2412 DRV_LOG(WARNING, "Representor on Bonding device should use pf#vf# syntax: %s",
2413 pci_dev->device.devargs->args);
2414 eth_da.nb_ports = 1;
2415 eth_da.ports[0] = list[0].info.pf_num;
2417 if (eth_da.nb_representor_ports == 0) {
2418 eth_da.nb_representor_ports = 1;
2419 eth_da.representor_ports[0] = 0;
2422 for (i = 0; i != ns; ++i) {
2425 /* Default configuration. */
2426 mlx5_os_config_default(&dev_config, &cdev->config);
2427 dev_config.vf = mlx5_dev_is_vf_pci(pci_dev);
2428 list[i].eth_dev = mlx5_dev_spawn(cdev->dev, &list[i],
2429 &dev_config, ð_da);
2430 if (!list[i].eth_dev) {
2431 if (rte_errno != EBUSY && rte_errno != EEXIST)
2433 /* Device is disabled or already spawned. Ignore it. */
2436 restore = list[i].eth_dev->data->dev_flags;
2437 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
2439 * Each representor has a dedicated interrupts vector.
2440 * rte_eth_copy_pci_info() assigns PF interrupts handle to
2441 * representor eth_dev object because representor and PF
2442 * share the same PCI address.
2443 * Override representor device with a dedicated
2444 * interrupts handle here.
2445 * Representor interrupts handle is released in mlx5_dev_stop().
2447 if (list[i].info.representor) {
2448 struct rte_intr_handle *intr_handle =
2449 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);
2450 if (intr_handle == NULL) {
2452 "port %u failed to allocate memory for interrupt handler "
2453 "Rx interrupts will not be supported",
2459 list[i].eth_dev->intr_handle = intr_handle;
2461 /* Restore non-PCI flags cleared by the above call. */
2462 list[i].eth_dev->data->dev_flags |= restore;
2463 rte_eth_dev_probing_finish(list[i].eth_dev);
2467 "probe of PCI device " PCI_PRI_FMT " aborted after"
2468 " encountering an error: %s",
2469 owner_pci.domain, owner_pci.bus,
2470 owner_pci.devid, owner_pci.function,
2471 strerror(rte_errno));
2475 if (!list[i].eth_dev)
2477 mlx5_dev_close(list[i].eth_dev);
2478 /* mac_addrs must not be freed because in dev_private */
2479 list[i].eth_dev->data->mac_addrs = NULL;
2480 claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
2482 /* Restore original error. */
2489 * Do the routine cleanup:
2490 * - close opened Netlink sockets
2491 * - free allocated spawn data array
2492 * - free the Infiniband device list
2500 MLX5_ASSERT(ibv_list);
2501 mlx5_glue->free_device_list(ibv_list);
2506 mlx5_os_parse_eth_devargs(struct rte_device *dev,
2507 struct rte_eth_devargs *eth_da)
2511 if (dev->devargs == NULL)
2513 memset(eth_da, 0, sizeof(*eth_da));
2514 /* Parse representor information first from class argument. */
2515 if (dev->devargs->cls_str)
2516 ret = rte_eth_devargs_parse(dev->devargs->cls_str, eth_da);
2518 DRV_LOG(ERR, "failed to parse device arguments: %s",
2519 dev->devargs->cls_str);
2522 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) {
2523 /* Parse legacy device argument */
2524 ret = rte_eth_devargs_parse(dev->devargs->args, eth_da);
2526 DRV_LOG(ERR, "failed to parse device arguments: %s",
2527 dev->devargs->args);
2535 * Callback to register a PCI device.
2537 * This function spawns Ethernet devices out of a given PCI device.
2540 * Pointer to common mlx5 device structure.
2543 * 0 on success, a negative errno value otherwise and rte_errno is set.
2546 mlx5_os_pci_probe(struct mlx5_common_device *cdev)
2548 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev);
2549 struct rte_eth_devargs eth_da = { .nb_ports = 0 };
2553 ret = mlx5_os_parse_eth_devargs(cdev->dev, ð_da);
2557 if (eth_da.nb_ports > 0) {
2558 /* Iterate all port if devargs pf is range: "pf[0-1]vf[...]". */
2559 for (p = 0; p < eth_da.nb_ports; p++) {
2560 ret = mlx5_os_pci_probe_pf(cdev, ð_da,
2566 DRV_LOG(ERR, "Probe of PCI device " PCI_PRI_FMT " "
2567 "aborted due to prodding failure of PF %u",
2568 pci_dev->addr.domain, pci_dev->addr.bus,
2569 pci_dev->addr.devid, pci_dev->addr.function,
2571 mlx5_net_remove(cdev);
2574 ret = mlx5_os_pci_probe_pf(cdev, ð_da, 0);
2579 /* Probe a single SF device on auxiliary bus, no representor support. */
2581 mlx5_os_auxiliary_probe(struct mlx5_common_device *cdev)
2583 struct rte_eth_devargs eth_da = { .nb_ports = 0 };
2584 struct mlx5_dev_config config;
2585 struct mlx5_dev_spawn_data spawn = { .pf_bond = -1 };
2586 struct rte_device *dev = cdev->dev;
2587 struct rte_auxiliary_device *adev = RTE_DEV_TO_AUXILIARY(dev);
2588 struct rte_eth_dev *eth_dev;
2591 /* Parse ethdev devargs. */
2592 ret = mlx5_os_parse_eth_devargs(dev, ð_da);
2595 /* Set default config data. */
2596 mlx5_os_config_default(&config, &cdev->config);
2598 /* Init spawn data. */
2600 spawn.phys_port = 1;
2601 spawn.phys_dev_name = mlx5_os_get_ctx_device_name(cdev->ctx);
2602 ret = mlx5_auxiliary_get_ifindex(dev->name);
2604 DRV_LOG(ERR, "failed to get ethdev ifindex: %s", dev->name);
2607 spawn.ifindex = ret;
2610 eth_dev = mlx5_dev_spawn(dev, &spawn, &config, ð_da);
2611 if (eth_dev == NULL)
2614 eth_dev->intr_handle = adev->intr_handle;
2615 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2616 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2617 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_RMV;
2618 eth_dev->data->numa_node = dev->numa_node;
2620 rte_eth_dev_probing_finish(eth_dev);
2625 * Net class driver callback to probe a device.
2627 * This function probe PCI bus device(s) or a single SF on auxiliary bus.
2630 * Pointer to the common mlx5 device.
2633 * 0 on success, a negative errno value otherwise and rte_errno is set.
2636 mlx5_os_net_probe(struct mlx5_common_device *cdev)
2640 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
2641 mlx5_pmd_socket_init();
2642 ret = mlx5_init_once();
2644 DRV_LOG(ERR, "Unable to init PMD global data: %s",
2645 strerror(rte_errno));
2648 if (mlx5_dev_is_pci(cdev->dev))
2649 return mlx5_os_pci_probe(cdev);
2651 return mlx5_os_auxiliary_probe(cdev);
2655 * Cleanup resources when the last device is closed.
2658 mlx5_os_net_cleanup(void)
2660 mlx5_pmd_socket_uninit();
2664 * Install shared asynchronous device events handler.
2665 * This function is implemented to support event sharing
2666 * between multiple ports of single IB device.
2669 * Pointer to mlx5_dev_ctx_shared object.
2672 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh)
2676 struct ibv_context *ctx = sh->cdev->ctx;
2678 sh->intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);
2679 if (sh->intr_handle == NULL) {
2680 DRV_LOG(ERR, "Fail to allocate intr_handle");
2684 rte_intr_fd_set(sh->intr_handle, -1);
2686 flags = fcntl(ctx->async_fd, F_GETFL);
2687 ret = fcntl(ctx->async_fd, F_SETFL, flags | O_NONBLOCK);
2689 DRV_LOG(INFO, "failed to change file descriptor async event"
2692 rte_intr_fd_set(sh->intr_handle, ctx->async_fd);
2693 rte_intr_type_set(sh->intr_handle, RTE_INTR_HANDLE_EXT);
2694 if (rte_intr_callback_register(sh->intr_handle,
2695 mlx5_dev_interrupt_handler, sh)) {
2696 DRV_LOG(INFO, "Fail to install the shared interrupt.");
2697 rte_intr_fd_set(sh->intr_handle, -1);
2700 if (sh->cdev->config.devx) {
2701 #ifdef HAVE_IBV_DEVX_ASYNC
2702 sh->intr_handle_devx =
2703 rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_SHARED);
2704 if (!sh->intr_handle_devx) {
2705 DRV_LOG(ERR, "Fail to allocate intr_handle");
2709 rte_intr_fd_set(sh->intr_handle_devx, -1);
2710 sh->devx_comp = (void *)mlx5_glue->devx_create_cmd_comp(ctx);
2711 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp;
2713 DRV_LOG(INFO, "failed to allocate devx_comp.");
2716 flags = fcntl(devx_comp->fd, F_GETFL);
2717 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK);
2719 DRV_LOG(INFO, "failed to change file descriptor"
2723 rte_intr_fd_set(sh->intr_handle_devx, devx_comp->fd);
2724 rte_intr_type_set(sh->intr_handle_devx,
2725 RTE_INTR_HANDLE_EXT);
2726 if (rte_intr_callback_register(sh->intr_handle_devx,
2727 mlx5_dev_interrupt_handler_devx, sh)) {
2728 DRV_LOG(INFO, "Fail to install the devx shared"
2730 rte_intr_fd_set(sh->intr_handle_devx, -1);
2732 #endif /* HAVE_IBV_DEVX_ASYNC */
2737 * Uninstall shared asynchronous device events handler.
2738 * This function is implemented to support event sharing
2739 * between multiple ports of single IB device.
2742 * Pointer to mlx5_dev_ctx_shared object.
2745 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh)
2747 if (rte_intr_fd_get(sh->intr_handle) >= 0)
2748 mlx5_intr_callback_unregister(sh->intr_handle,
2749 mlx5_dev_interrupt_handler, sh);
2750 rte_intr_instance_free(sh->intr_handle);
2751 #ifdef HAVE_IBV_DEVX_ASYNC
2752 if (rte_intr_fd_get(sh->intr_handle_devx) >= 0)
2753 rte_intr_callback_unregister(sh->intr_handle_devx,
2754 mlx5_dev_interrupt_handler_devx, sh);
2755 rte_intr_instance_free(sh->intr_handle_devx);
2757 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp);
2762 * Read statistics by a named counter.
2765 * Pointer to the private device data structure.
2766 * @param[in] ctr_name
2767 * Pointer to the name of the statistic counter to read
2769 * Pointer to read statistic value.
2771 * 0 on success and stat is valud, 1 if failed to read the value
2776 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name,
2782 if (priv->q_counters != NULL &&
2783 strcmp(ctr_name, "out_of_buffer") == 0)
2784 return mlx5_devx_cmd_queue_counter_query
2785 (priv->q_counters, 0, (uint32_t *)stat);
2786 MKSTR(path, "%s/ports/%d/hw_counters/%s",
2787 priv->sh->ibdev_path,
2790 fd = open(path, O_RDONLY);
2792 * in switchdev the file location is not per port
2793 * but rather in <ibdev_path>/hw_counters/<file_name>.
2796 MKSTR(path1, "%s/hw_counters/%s",
2797 priv->sh->ibdev_path,
2799 fd = open(path1, O_RDONLY);
2802 char buf[21] = {'\0'};
2803 ssize_t n = read(fd, buf, sizeof(buf));
2807 *stat = strtoull(buf, NULL, 10);
2817 * Remove a MAC address from device
2820 * Pointer to Ethernet device structure.
2822 * MAC address index.
2825 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
2827 struct mlx5_priv *priv = dev->data->dev_private;
2828 const int vf = priv->config.vf;
2831 mlx5_nl_mac_addr_remove(priv->nl_socket_route,
2832 mlx5_ifindex(dev), priv->mac_own,
2833 &dev->data->mac_addrs[index], index);
2837 * Adds a MAC address to the device
2840 * Pointer to Ethernet device structure.
2842 * MAC address to register.
2844 * MAC address index.
2847 * 0 on success, a negative errno value otherwise
2850 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
2853 struct mlx5_priv *priv = dev->data->dev_private;
2854 const int vf = priv->config.vf;
2858 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route,
2859 mlx5_ifindex(dev), priv->mac_own,
2865 * Modify a VF MAC address
2868 * Pointer to device private data.
2870 * MAC address to modify into.
2872 * Net device interface index
2877 * 0 on success, a negative errno value otherwise
2880 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv,
2881 unsigned int iface_idx,
2882 struct rte_ether_addr *mac_addr,
2885 return mlx5_nl_vf_mac_addr_modify
2886 (priv->nl_socket_route, iface_idx, mac_addr, vf_index);
2890 * Set device promiscuous mode
2893 * Pointer to Ethernet device structure.
2895 * 0 - promiscuous is disabled, otherwise - enabled
2898 * 0 on success, a negative error value otherwise
2901 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable)
2903 struct mlx5_priv *priv = dev->data->dev_private;
2905 return mlx5_nl_promisc(priv->nl_socket_route,
2906 mlx5_ifindex(dev), !!enable);
2910 * Set device promiscuous mode
2913 * Pointer to Ethernet device structure.
2915 * 0 - all multicase is disabled, otherwise - enabled
2918 * 0 on success, a negative error value otherwise
2921 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable)
2923 struct mlx5_priv *priv = dev->data->dev_private;
2925 return mlx5_nl_allmulti(priv->nl_socket_route,
2926 mlx5_ifindex(dev), !!enable);
2930 * Flush device MAC addresses
2933 * Pointer to Ethernet device structure.
2937 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev)
2939 struct mlx5_priv *priv = dev->data->dev_private;
2941 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
2942 dev->data->mac_addrs,
2943 MLX5_MAX_MAC_ADDRESSES, priv->mac_own);