1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
11 #include <sys/queue.h>
13 #include "mlx5_autoconf.h"
16 #include <rte_malloc.h>
17 #include <ethdev_driver.h>
18 #include <rte_common.h>
20 #include <mlx5_glue.h>
21 #include <mlx5_common.h>
22 #include <mlx5_common_mr.h>
23 #include <mlx5_verbs.h>
26 #include <mlx5_utils.h>
27 #include <mlx5_malloc.h>
30 * Register mr. Given protection domain pointer, pointer to addr and length
31 * register the memory region.
34 * Pointer to protection domain context.
36 * Pointer to memory start address.
38 * Length of the memory to register.
40 * pmd_mr struct set with lkey, address, length and pointer to mr object
43 * 0 on successful registration, -1 otherwise
46 mlx5_reg_mr(void *pd, void *addr, size_t length,
47 struct mlx5_pmd_mr *pmd_mr)
49 return mlx5_common_verbs_reg_mr(pd, addr, length, pmd_mr);
53 * Deregister mr. Given the mlx5 pmd MR - deregister the MR
56 * pmd_mr struct set with lkey, address, length and pointer to mr object
60 mlx5_dereg_mr(struct mlx5_pmd_mr *pmd_mr)
62 mlx5_common_verbs_dereg_mr(pmd_mr);
65 /* verbs operations. */
66 const struct mlx5_mr_ops mlx5_mr_verbs_ops = {
67 .reg_mr = mlx5_reg_mr,
68 .dereg_mr = mlx5_dereg_mr,
72 * Modify Rx WQ vlan stripping offload
77 * @return 0 on success, non-0 otherwise
80 mlx5_rxq_obj_modify_wq_vlan_strip(struct mlx5_rxq_obj *rxq_obj, int on)
82 uint16_t vlan_offloads =
83 (on ? IBV_WQ_FLAGS_CVLAN_STRIPPING : 0) |
85 struct ibv_wq_attr mod;
86 mod = (struct ibv_wq_attr){
87 .attr_mask = IBV_WQ_ATTR_FLAGS,
88 .flags_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING,
89 .flags = vlan_offloads,
92 return mlx5_glue->modify_wq(rxq_obj->wq, &mod);
96 * Modifies the attributes for the specified WQ.
99 * Verbs Rx queue object.
101 * Type of change queue state.
104 * 0 on success, a negative errno value otherwise and rte_errno is set.
107 mlx5_ibv_modify_wq(struct mlx5_rxq_obj *rxq_obj, uint8_t type)
109 struct ibv_wq_attr mod = {
110 .attr_mask = IBV_WQ_ATTR_STATE,
111 .wq_state = (enum ibv_wq_state)type,
114 return mlx5_glue->modify_wq(rxq_obj->wq, &mod);
118 * Modify QP using Verbs API.
121 * Verbs Tx queue object.
123 * Type of change queue state.
125 * IB device port number.
128 * 0 on success, a negative errno value otherwise and rte_errno is set.
131 mlx5_ibv_modify_qp(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type,
134 struct ibv_qp_attr mod = {
135 .qp_state = IBV_QPS_RESET,
136 .port_num = dev_port,
138 int attr_mask = (IBV_QP_STATE | IBV_QP_PORT);
141 if (type != MLX5_TXQ_MOD_RST2RDY) {
142 ret = mlx5_glue->modify_qp(obj->qp, &mod, IBV_QP_STATE);
144 DRV_LOG(ERR, "Cannot change Tx QP state to RESET %s",
149 if (type == MLX5_TXQ_MOD_RDY2RST)
152 if (type == MLX5_TXQ_MOD_ERR2RDY)
153 attr_mask = IBV_QP_STATE;
154 mod.qp_state = IBV_QPS_INIT;
155 ret = mlx5_glue->modify_qp(obj->qp, &mod, attr_mask);
157 DRV_LOG(ERR, "Cannot change Tx QP state to INIT %s",
162 mod.qp_state = IBV_QPS_RTR;
163 ret = mlx5_glue->modify_qp(obj->qp, &mod, IBV_QP_STATE);
165 DRV_LOG(ERR, "Cannot change Tx QP state to RTR %s",
170 mod.qp_state = IBV_QPS_RTS;
171 ret = mlx5_glue->modify_qp(obj->qp, &mod, IBV_QP_STATE);
173 DRV_LOG(ERR, "Cannot change Tx QP state to RTS %s",
182 * Create a CQ Verbs object.
185 * Pointer to Ethernet device.
187 * Queue index in DPDK Rx queue array.
190 * The Verbs CQ object initialized, NULL otherwise and rte_errno is set.
192 static struct ibv_cq *
193 mlx5_rxq_ibv_cq_create(struct rte_eth_dev *dev, uint16_t idx)
195 struct mlx5_priv *priv = dev->data->dev_private;
196 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
197 struct mlx5_rxq_ctrl *rxq_ctrl =
198 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
199 struct mlx5_rxq_obj *rxq_obj = rxq_ctrl->obj;
200 unsigned int cqe_n = mlx5_rxq_cqe_num(rxq_data);
202 struct ibv_cq_init_attr_ex ibv;
203 struct mlx5dv_cq_init_attr mlx5;
206 cq_attr.ibv = (struct ibv_cq_init_attr_ex){
208 .channel = rxq_obj->ibv_channel,
211 cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){
214 if (priv->config.cqe_comp && !rxq_data->hw_timestamp) {
215 cq_attr.mlx5.comp_mask |=
216 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
217 rxq_data->byte_mask = UINT32_MAX;
218 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
219 if (mlx5_rxq_mprq_enabled(rxq_data)) {
220 cq_attr.mlx5.cqe_comp_res_format =
221 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX;
222 rxq_data->mcqe_format =
223 MLX5_CQE_RESP_FORMAT_CSUM_STRIDX;
225 cq_attr.mlx5.cqe_comp_res_format =
226 MLX5DV_CQE_RES_FORMAT_HASH;
227 rxq_data->mcqe_format =
228 MLX5_CQE_RESP_FORMAT_HASH;
231 cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
232 rxq_data->mcqe_format = MLX5_CQE_RESP_FORMAT_HASH;
235 * For vectorized Rx, it must not be doubled in order to
236 * make cq_ci and rq_ci aligned.
238 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
239 cq_attr.ibv.cqe *= 2;
240 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
242 "Port %u Rx CQE compression is disabled for HW"
246 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
247 if (RTE_CACHE_LINE_SIZE == 128) {
248 cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
249 cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
252 return mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,
258 * Create a WQ Verbs object.
261 * Pointer to Ethernet device.
263 * Queue index in DPDK Rx queue array.
266 * The Verbs WQ object initialized, NULL otherwise and rte_errno is set.
268 static struct ibv_wq *
269 mlx5_rxq_ibv_wq_create(struct rte_eth_dev *dev, uint16_t idx)
271 struct mlx5_priv *priv = dev->data->dev_private;
272 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
273 struct mlx5_rxq_ctrl *rxq_ctrl =
274 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
275 struct mlx5_rxq_obj *rxq_obj = rxq_ctrl->obj;
276 unsigned int wqe_n = 1 << rxq_data->elts_n;
278 struct ibv_wq_init_attr ibv;
279 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
280 struct mlx5dv_wq_init_attr mlx5;
284 wq_attr.ibv = (struct ibv_wq_init_attr){
285 .wq_context = NULL, /* Could be useful in the future. */
286 .wq_type = IBV_WQT_RQ,
287 /* Max number of outstanding WRs. */
288 .max_wr = wqe_n >> rxq_data->sges_n,
289 /* Max number of scatter/gather elements in a WR. */
290 .max_sge = 1 << rxq_data->sges_n,
292 .cq = rxq_obj->ibv_cq,
293 .comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0,
294 .create_flags = (rxq_data->vlan_strip ?
295 IBV_WQ_FLAGS_CVLAN_STRIPPING : 0),
297 /* By default, FCS (CRC) is stripped by hardware. */
298 if (rxq_data->crc_present) {
299 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
300 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
302 if (priv->config.hw_padding) {
303 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
304 wq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
305 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
306 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
307 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
308 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
311 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
312 wq_attr.mlx5 = (struct mlx5dv_wq_init_attr){
315 if (mlx5_rxq_mprq_enabled(rxq_data)) {
316 struct mlx5dv_striding_rq_init_attr *mprq_attr =
317 &wq_attr.mlx5.striding_rq_attrs;
319 wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
320 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
321 .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
322 .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
323 .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
326 rxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,
329 rxq_obj->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);
333 * Make sure number of WRs*SGEs match expectations since a queue
334 * cannot allocate more than "desc" buffers.
336 if (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
337 wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {
339 "Port %u Rx queue %u requested %u*%u but got"
341 dev->data->port_id, idx,
342 wqe_n >> rxq_data->sges_n,
343 (1 << rxq_data->sges_n),
344 wq_attr.ibv.max_wr, wq_attr.ibv.max_sge);
345 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
354 * Create the Rx queue Verbs object.
357 * Pointer to Ethernet device.
359 * Queue index in DPDK Rx queue array.
362 * 0 on success, a negative errno value otherwise and rte_errno is set.
365 mlx5_rxq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx)
367 struct mlx5_priv *priv = dev->data->dev_private;
368 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
369 struct mlx5_rxq_ctrl *rxq_ctrl =
370 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
371 struct mlx5_rxq_obj *tmpl = rxq_ctrl->obj;
372 struct mlx5dv_cq cq_info;
373 struct mlx5dv_rwq rwq;
375 struct mlx5dv_obj obj;
377 MLX5_ASSERT(rxq_data);
379 tmpl->rxq_ctrl = rxq_ctrl;
382 mlx5_glue->create_comp_channel(priv->sh->ctx);
383 if (!tmpl->ibv_channel) {
384 DRV_LOG(ERR, "Port %u: comp channel creation failure.",
389 tmpl->fd = ((struct ibv_comp_channel *)(tmpl->ibv_channel))->fd;
391 /* Create CQ using Verbs API. */
392 tmpl->ibv_cq = mlx5_rxq_ibv_cq_create(dev, idx);
394 DRV_LOG(ERR, "Port %u Rx queue %u CQ creation failure.",
395 dev->data->port_id, idx);
399 obj.cq.in = tmpl->ibv_cq;
400 obj.cq.out = &cq_info;
401 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ);
406 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
408 "Port %u wrong MLX5_CQE_SIZE environment "
409 "variable value: it should be set to %u.",
410 dev->data->port_id, RTE_CACHE_LINE_SIZE);
414 /* Fill the rings. */
415 rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
416 rxq_data->cq_db = cq_info.dbrec;
417 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
418 rxq_data->cq_uar = cq_info.cq_uar;
419 rxq_data->cqn = cq_info.cqn;
420 /* Create WQ (RQ) using Verbs API. */
421 tmpl->wq = mlx5_rxq_ibv_wq_create(dev, idx);
423 DRV_LOG(ERR, "Port %u Rx queue %u WQ creation failure.",
424 dev->data->port_id, idx);
428 /* Change queue state to ready. */
429 ret = mlx5_ibv_modify_wq(tmpl, IBV_WQS_RDY);
432 "Port %u Rx queue %u WQ state to IBV_WQS_RDY failed.",
433 dev->data->port_id, idx);
437 obj.rwq.in = tmpl->wq;
439 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_RWQ);
444 rxq_data->wqes = rwq.buf;
445 rxq_data->rq_db = rwq.dbrec;
446 rxq_data->cq_arm_sn = 0;
447 mlx5_rxq_initialize(rxq_data);
449 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
450 rxq_ctrl->wqn = ((struct ibv_wq *)(tmpl->wq))->wq_num;
453 ret = rte_errno; /* Save rte_errno before cleanup. */
455 claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
457 claim_zero(mlx5_glue->destroy_cq(tmpl->ibv_cq));
458 if (tmpl->ibv_channel)
459 claim_zero(mlx5_glue->destroy_comp_channel(tmpl->ibv_channel));
460 rte_errno = ret; /* Restore rte_errno. */
465 * Release an Rx verbs queue object.
468 * Verbs Rx queue object.
471 mlx5_rxq_ibv_obj_release(struct mlx5_rxq_obj *rxq_obj)
473 MLX5_ASSERT(rxq_obj);
474 MLX5_ASSERT(rxq_obj->wq);
475 MLX5_ASSERT(rxq_obj->ibv_cq);
476 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
477 claim_zero(mlx5_glue->destroy_cq(rxq_obj->ibv_cq));
478 if (rxq_obj->ibv_channel)
479 claim_zero(mlx5_glue->destroy_comp_channel
480 (rxq_obj->ibv_channel));
484 * Get event for an Rx verbs queue object.
487 * Verbs Rx queue object.
490 * 0 on success, a negative errno value otherwise and rte_errno is set.
493 mlx5_rx_ibv_get_event(struct mlx5_rxq_obj *rxq_obj)
495 struct ibv_cq *ev_cq;
497 int ret = mlx5_glue->get_cq_event(rxq_obj->ibv_channel,
500 if (ret < 0 || ev_cq != rxq_obj->ibv_cq)
502 mlx5_glue->ack_cq_events(rxq_obj->ibv_cq, 1);
513 * Creates a receive work queue as a filed of indirection table.
516 * Pointer to Ethernet device.
518 * Log of number of queues in the array.
520 * Verbs indirection table object.
523 * 0 on success, a negative errno value otherwise and rte_errno is set.
526 mlx5_ibv_ind_table_new(struct rte_eth_dev *dev, const unsigned int log_n,
527 struct mlx5_ind_table_obj *ind_tbl)
529 struct mlx5_priv *priv = dev->data->dev_private;
530 struct ibv_wq *wq[1 << log_n];
533 MLX5_ASSERT(ind_tbl);
534 for (i = 0; i != ind_tbl->queues_n; ++i) {
535 struct mlx5_rxq_data *rxq = (*priv->rxqs)[ind_tbl->queues[i]];
536 struct mlx5_rxq_ctrl *rxq_ctrl =
537 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
539 wq[i] = rxq_ctrl->obj->wq;
542 /* Finalise indirection table. */
543 for (j = 0; i != (unsigned int)(1 << log_n); ++j, ++i)
545 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table(priv->sh->ctx,
546 &(struct ibv_rwq_ind_table_init_attr){
547 .log_ind_tbl_size = log_n,
551 if (!ind_tbl->ind_table) {
559 * Destroys the specified Indirection Table.
562 * Indirection table to release.
565 mlx5_ibv_ind_table_destroy(struct mlx5_ind_table_obj *ind_tbl)
567 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
571 * Create an Rx Hash queue.
574 * Pointer to Ethernet device.
576 * Pointer to Rx Hash queue.
581 * 0 on success, a negative errno value otherwise and rte_errno is set.
584 mlx5_ibv_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
585 int tunnel __rte_unused)
587 struct mlx5_priv *priv = dev->data->dev_private;
588 struct ibv_qp *qp = NULL;
589 struct mlx5_ind_table_obj *ind_tbl = hrxq->ind_table;
590 const uint8_t *rss_key = hrxq->rss_key;
591 uint64_t hash_fields = hrxq->hash_fields;
593 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
594 struct mlx5dv_qp_init_attr qp_init_attr;
596 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
598 qp_init_attr.comp_mask =
599 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
600 qp_init_attr.create_flags = MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
602 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
603 if (dev->data->dev_conf.lpbk_mode) {
604 /* Allow packet sent from NIC loop back w/o source MAC check. */
605 qp_init_attr.comp_mask |=
606 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
607 qp_init_attr.create_flags |=
608 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
611 qp = mlx5_glue->dv_create_qp
613 &(struct ibv_qp_init_attr_ex){
614 .qp_type = IBV_QPT_RAW_PACKET,
616 IBV_QP_INIT_ATTR_PD |
617 IBV_QP_INIT_ATTR_IND_TABLE |
618 IBV_QP_INIT_ATTR_RX_HASH,
619 .rx_hash_conf = (struct ibv_rx_hash_conf){
621 IBV_RX_HASH_FUNC_TOEPLITZ,
622 .rx_hash_key_len = hrxq->rss_key_len,
624 (void *)(uintptr_t)rss_key,
625 .rx_hash_fields_mask = hash_fields,
627 .rwq_ind_tbl = ind_tbl->ind_table,
632 qp = mlx5_glue->create_qp_ex
634 &(struct ibv_qp_init_attr_ex){
635 .qp_type = IBV_QPT_RAW_PACKET,
637 IBV_QP_INIT_ATTR_PD |
638 IBV_QP_INIT_ATTR_IND_TABLE |
639 IBV_QP_INIT_ATTR_RX_HASH,
640 .rx_hash_conf = (struct ibv_rx_hash_conf){
642 IBV_RX_HASH_FUNC_TOEPLITZ,
643 .rx_hash_key_len = hrxq->rss_key_len,
645 (void *)(uintptr_t)rss_key,
646 .rx_hash_fields_mask = hash_fields,
648 .rwq_ind_tbl = ind_tbl->ind_table,
657 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
658 hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
666 err = rte_errno; /* Save rte_errno before cleanup. */
668 claim_zero(mlx5_glue->destroy_qp(qp));
669 rte_errno = err; /* Restore rte_errno. */
674 * Destroy a Verbs queue pair.
677 * Hash Rx queue to release its qp.
680 mlx5_ibv_qp_destroy(struct mlx5_hrxq *hrxq)
682 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
686 * Release a drop Rx queue Verbs object.
689 * Pointer to Ethernet device.
692 mlx5_rxq_ibv_obj_drop_release(struct rte_eth_dev *dev)
694 struct mlx5_priv *priv = dev->data->dev_private;
695 struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
698 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
700 claim_zero(mlx5_glue->destroy_cq(rxq->ibv_cq));
702 priv->drop_queue.rxq = NULL;
706 * Create a drop Rx queue Verbs object.
709 * Pointer to Ethernet device.
712 * 0 on success, a negative errno value otherwise and rte_errno is set.
715 mlx5_rxq_ibv_obj_drop_create(struct rte_eth_dev *dev)
717 struct mlx5_priv *priv = dev->data->dev_private;
718 struct ibv_context *ctx = priv->sh->ctx;
719 struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
723 rxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rxq), 0, SOCKET_ID_ANY);
725 DRV_LOG(DEBUG, "Port %u cannot allocate drop Rx queue memory.",
730 priv->drop_queue.rxq = rxq;
731 rxq->ibv_cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
733 DRV_LOG(DEBUG, "Port %u cannot allocate CQ for drop queue.",
738 rxq->wq = mlx5_glue->create_wq(ctx, &(struct ibv_wq_init_attr){
739 .wq_type = IBV_WQT_RQ,
746 DRV_LOG(DEBUG, "Port %u cannot allocate WQ for drop queue.",
751 priv->drop_queue.rxq = rxq;
754 mlx5_rxq_ibv_obj_drop_release(dev);
759 * Create a Verbs drop action for Rx Hash queue.
762 * Pointer to Ethernet device.
765 * 0 on success, a negative errno value otherwise and rte_errno is set.
768 mlx5_ibv_drop_action_create(struct rte_eth_dev *dev)
770 struct mlx5_priv *priv = dev->data->dev_private;
771 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
772 struct ibv_rwq_ind_table *ind_tbl = NULL;
773 struct mlx5_rxq_obj *rxq;
776 MLX5_ASSERT(hrxq && hrxq->ind_table);
777 ret = mlx5_rxq_ibv_obj_drop_create(dev);
780 rxq = priv->drop_queue.rxq;
781 ind_tbl = mlx5_glue->create_rwq_ind_table
783 &(struct ibv_rwq_ind_table_init_attr){
784 .log_ind_tbl_size = 0,
785 .ind_tbl = (struct ibv_wq **)&rxq->wq,
789 DRV_LOG(DEBUG, "Port %u"
790 " cannot allocate indirection table for drop queue.",
795 hrxq->qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
796 &(struct ibv_qp_init_attr_ex){
797 .qp_type = IBV_QPT_RAW_PACKET,
798 .comp_mask = IBV_QP_INIT_ATTR_PD |
799 IBV_QP_INIT_ATTR_IND_TABLE |
800 IBV_QP_INIT_ATTR_RX_HASH,
801 .rx_hash_conf = (struct ibv_rx_hash_conf){
802 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,
803 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
804 .rx_hash_key = rss_hash_default_key,
805 .rx_hash_fields_mask = 0,
807 .rwq_ind_tbl = ind_tbl,
811 DRV_LOG(DEBUG, "Port %u cannot allocate QP for drop queue.",
816 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
817 hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
823 hrxq->ind_table->ind_table = ind_tbl;
827 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
829 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl));
830 if (priv->drop_queue.rxq)
831 mlx5_rxq_ibv_obj_drop_release(dev);
836 * Release a drop hash Rx queue.
839 * Pointer to Ethernet device.
842 mlx5_ibv_drop_action_destroy(struct rte_eth_dev *dev)
844 struct mlx5_priv *priv = dev->data->dev_private;
845 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
846 struct ibv_rwq_ind_table *ind_tbl = hrxq->ind_table->ind_table;
848 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
849 claim_zero(mlx5_glue->destroy_flow_action(hrxq->action));
851 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
852 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl));
853 mlx5_rxq_ibv_obj_drop_release(dev);
857 * Create a QP Verbs object.
860 * Pointer to Ethernet device.
862 * Queue index in DPDK Tx queue array.
865 * The QP Verbs object, NULL otherwise and rte_errno is set.
867 static struct ibv_qp *
868 mlx5_txq_ibv_qp_create(struct rte_eth_dev *dev, uint16_t idx)
870 struct mlx5_priv *priv = dev->data->dev_private;
871 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
872 struct mlx5_txq_ctrl *txq_ctrl =
873 container_of(txq_data, struct mlx5_txq_ctrl, txq);
874 struct ibv_qp *qp_obj = NULL;
875 struct ibv_qp_init_attr_ex qp_attr = { 0 };
876 const int desc = 1 << txq_data->elts_n;
878 MLX5_ASSERT(txq_ctrl->obj->cq);
879 /* CQ to be associated with the send queue. */
880 qp_attr.send_cq = txq_ctrl->obj->cq;
881 /* CQ to be associated with the receive queue. */
882 qp_attr.recv_cq = txq_ctrl->obj->cq;
883 /* Max number of outstanding WRs. */
884 qp_attr.cap.max_send_wr = ((priv->sh->device_attr.max_qp_wr < desc) ?
885 priv->sh->device_attr.max_qp_wr : desc);
887 * Max number of scatter/gather elements in a WR, must be 1 to prevent
888 * libmlx5 from trying to affect must be 1 to prevent libmlx5 from
889 * trying to affect too much memory. TX gather is not impacted by the
890 * device_attr.max_sge limit and will still work properly.
892 qp_attr.cap.max_send_sge = 1;
893 qp_attr.qp_type = IBV_QPT_RAW_PACKET,
894 /* Do *NOT* enable this, completions events are managed per Tx burst. */
895 qp_attr.sq_sig_all = 0;
896 qp_attr.pd = priv->sh->pd;
897 qp_attr.comp_mask = IBV_QP_INIT_ATTR_PD;
898 if (txq_data->inlen_send)
899 qp_attr.cap.max_inline_data = txq_ctrl->max_inline_data;
900 if (txq_data->tso_en) {
901 qp_attr.max_tso_header = txq_ctrl->max_tso_header;
902 qp_attr.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;
904 qp_obj = mlx5_glue->create_qp_ex(priv->sh->ctx, &qp_attr);
905 if (qp_obj == NULL) {
906 DRV_LOG(ERR, "Port %u Tx queue %u QP creation failure.",
907 dev->data->port_id, idx);
914 * Create the Tx queue Verbs object.
917 * Pointer to Ethernet device.
919 * Queue index in DPDK Tx queue array.
922 * 0 on success, a negative errno value otherwise and rte_errno is set.
925 mlx5_txq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx)
927 struct mlx5_priv *priv = dev->data->dev_private;
928 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
929 struct mlx5_txq_ctrl *txq_ctrl =
930 container_of(txq_data, struct mlx5_txq_ctrl, txq);
931 struct mlx5_txq_obj *txq_obj = txq_ctrl->obj;
934 struct mlx5dv_cq cq_info;
935 struct mlx5dv_obj obj;
936 const int desc = 1 << txq_data->elts_n;
939 MLX5_ASSERT(txq_data);
940 MLX5_ASSERT(txq_obj);
941 txq_obj->txq_ctrl = txq_ctrl;
942 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
943 DRV_LOG(ERR, "Port %u MLX5_ENABLE_CQE_COMPRESSION "
944 "must never be set.", dev->data->port_id);
948 cqe_n = desc / MLX5_TX_COMP_THRESH +
949 1 + MLX5_TX_COMP_THRESH_INLINE_DIV;
950 txq_obj->cq = mlx5_glue->create_cq(priv->sh->ctx, cqe_n, NULL, NULL, 0);
951 if (txq_obj->cq == NULL) {
952 DRV_LOG(ERR, "Port %u Tx queue %u CQ creation failure.",
953 dev->data->port_id, idx);
957 txq_obj->qp = mlx5_txq_ibv_qp_create(dev, idx);
958 if (txq_obj->qp == NULL) {
962 ret = mlx5_ibv_modify_qp(txq_obj, MLX5_TXQ_MOD_RST2RDY,
963 (uint8_t)priv->dev_port);
965 DRV_LOG(ERR, "Port %u Tx queue %u QP state modifying failed.",
966 dev->data->port_id, idx);
970 qp.comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET;
971 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
972 /* If using DevX, need additional mask to read tisn value. */
973 if (priv->sh->devx && !priv->sh->tdn)
974 qp.comp_mask |= MLX5DV_QP_MASK_RAW_QP_HANDLES;
976 obj.cq.in = txq_obj->cq;
977 obj.cq.out = &cq_info;
978 obj.qp.in = txq_obj->qp;
980 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);
985 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
987 "Port %u wrong MLX5_CQE_SIZE environment variable"
988 " value: it should be set to %u.",
989 dev->data->port_id, RTE_CACHE_LINE_SIZE);
993 txq_data->cqe_n = log2above(cq_info.cqe_cnt);
994 txq_data->cqe_s = 1 << txq_data->cqe_n;
995 txq_data->cqe_m = txq_data->cqe_s - 1;
996 txq_data->qp_num_8s = ((struct ibv_qp *)txq_obj->qp)->qp_num << 8;
997 txq_data->wqes = qp.sq.buf;
998 txq_data->wqe_n = log2above(qp.sq.wqe_cnt);
999 txq_data->wqe_s = 1 << txq_data->wqe_n;
1000 txq_data->wqe_m = txq_data->wqe_s - 1;
1001 txq_data->wqes_end = txq_data->wqes + txq_data->wqe_s;
1002 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR];
1003 txq_data->cq_db = cq_info.dbrec;
1004 txq_data->cqes = (volatile struct mlx5_cqe *)cq_info.buf;
1005 txq_data->cq_ci = 0;
1006 txq_data->cq_pi = 0;
1007 txq_data->wqe_ci = 0;
1008 txq_data->wqe_pi = 0;
1009 txq_data->wqe_comp = 0;
1010 txq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV;
1011 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1013 * If using DevX need to query and store TIS transport domain value.
1014 * This is done once per port.
1015 * Will use this value on Rx, when creating matching TIR.
1017 if (priv->sh->devx && !priv->sh->tdn) {
1018 ret = mlx5_devx_cmd_qp_query_tis_td(txq_obj->qp, qp.tisn,
1021 DRV_LOG(ERR, "Fail to query port %u Tx queue %u QP TIS "
1022 "transport domain.", dev->data->port_id, idx);
1026 DRV_LOG(DEBUG, "Port %u Tx queue %u TIS number %d "
1027 "transport domain %d.", dev->data->port_id,
1028 idx, qp.tisn, priv->sh->tdn);
1032 txq_ctrl->bf_reg = qp.bf.reg;
1033 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
1034 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
1035 DRV_LOG(DEBUG, "Port %u: uar_mmap_offset 0x%" PRIx64 ".",
1036 dev->data->port_id, txq_ctrl->uar_mmap_offset);
1039 "Port %u failed to retrieve UAR info, invalid"
1041 dev->data->port_id);
1045 txq_uar_init(txq_ctrl);
1046 dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
1049 ret = rte_errno; /* Save rte_errno before cleanup. */
1051 claim_zero(mlx5_glue->destroy_cq(txq_obj->cq));
1053 claim_zero(mlx5_glue->destroy_qp(txq_obj->qp));
1054 rte_errno = ret; /* Restore rte_errno. */
1059 * Release an Tx verbs queue object.
1062 * Verbs Tx queue object..
1065 mlx5_txq_ibv_obj_release(struct mlx5_txq_obj *txq_obj)
1067 MLX5_ASSERT(txq_obj);
1068 claim_zero(mlx5_glue->destroy_qp(txq_obj->qp));
1069 claim_zero(mlx5_glue->destroy_cq(txq_obj->cq));
1072 struct mlx5_obj_ops ibv_obj_ops = {
1073 .rxq_obj_modify_vlan_strip = mlx5_rxq_obj_modify_wq_vlan_strip,
1074 .rxq_obj_new = mlx5_rxq_ibv_obj_new,
1075 .rxq_event_get = mlx5_rx_ibv_get_event,
1076 .rxq_obj_modify = mlx5_ibv_modify_wq,
1077 .rxq_obj_release = mlx5_rxq_ibv_obj_release,
1078 .ind_table_new = mlx5_ibv_ind_table_new,
1079 .ind_table_destroy = mlx5_ibv_ind_table_destroy,
1080 .hrxq_new = mlx5_ibv_hrxq_new,
1081 .hrxq_destroy = mlx5_ibv_qp_destroy,
1082 .drop_action_create = mlx5_ibv_drop_action_create,
1083 .drop_action_destroy = mlx5_ibv_drop_action_destroy,
1084 .txq_obj_new = mlx5_txq_ibv_obj_new,
1085 .txq_obj_modify = mlx5_ibv_modify_qp,
1086 .txq_obj_release = mlx5_txq_ibv_obj_release,