1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
11 #include <sys/queue.h>
13 #include "mlx5_autoconf.h"
16 #include <rte_malloc.h>
17 #include <ethdev_driver.h>
18 #include <rte_common.h>
20 #include <mlx5_glue.h>
21 #include <mlx5_common.h>
22 #include <mlx5_common_mr.h>
23 #include <mlx5_rxtx.h>
24 #include <mlx5_verbs.h>
25 #include <mlx5_utils.h>
26 #include <mlx5_malloc.h>
29 * Register mr. Given protection domain pointer, pointer to addr and length
30 * register the memory region.
33 * Pointer to protection domain context.
35 * Pointer to memory start address.
37 * Length of the memory to register.
39 * pmd_mr struct set with lkey, address, length and pointer to mr object
42 * 0 on successful registration, -1 otherwise
45 mlx5_reg_mr(void *pd, void *addr, size_t length,
46 struct mlx5_pmd_mr *pmd_mr)
48 return mlx5_common_verbs_reg_mr(pd, addr, length, pmd_mr);
52 * Deregister mr. Given the mlx5 pmd MR - deregister the MR
55 * pmd_mr struct set with lkey, address, length and pointer to mr object
59 mlx5_dereg_mr(struct mlx5_pmd_mr *pmd_mr)
61 mlx5_common_verbs_dereg_mr(pmd_mr);
64 /* verbs operations. */
65 const struct mlx5_mr_ops mlx5_mr_verbs_ops = {
66 .reg_mr = mlx5_reg_mr,
67 .dereg_mr = mlx5_dereg_mr,
71 * Modify Rx WQ vlan stripping offload
76 * @return 0 on success, non-0 otherwise
79 mlx5_rxq_obj_modify_wq_vlan_strip(struct mlx5_rxq_obj *rxq_obj, int on)
81 uint16_t vlan_offloads =
82 (on ? IBV_WQ_FLAGS_CVLAN_STRIPPING : 0) |
84 struct ibv_wq_attr mod;
85 mod = (struct ibv_wq_attr){
86 .attr_mask = IBV_WQ_ATTR_FLAGS,
87 .flags_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING,
88 .flags = vlan_offloads,
91 return mlx5_glue->modify_wq(rxq_obj->wq, &mod);
95 * Modifies the attributes for the specified WQ.
98 * Verbs Rx queue object.
100 * Type of change queue state.
103 * 0 on success, a negative errno value otherwise and rte_errno is set.
106 mlx5_ibv_modify_wq(struct mlx5_rxq_obj *rxq_obj, uint8_t type)
108 struct ibv_wq_attr mod = {
109 .attr_mask = IBV_WQ_ATTR_STATE,
110 .wq_state = (enum ibv_wq_state)type,
113 return mlx5_glue->modify_wq(rxq_obj->wq, &mod);
117 * Modify QP using Verbs API.
120 * Verbs Tx queue object.
122 * Type of change queue state.
124 * IB device port number.
127 * 0 on success, a negative errno value otherwise and rte_errno is set.
130 mlx5_ibv_modify_qp(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type,
133 struct ibv_qp_attr mod = {
134 .qp_state = IBV_QPS_RESET,
135 .port_num = dev_port,
137 int attr_mask = (IBV_QP_STATE | IBV_QP_PORT);
140 if (type != MLX5_TXQ_MOD_RST2RDY) {
141 ret = mlx5_glue->modify_qp(obj->qp, &mod, IBV_QP_STATE);
143 DRV_LOG(ERR, "Cannot change Tx QP state to RESET %s",
148 if (type == MLX5_TXQ_MOD_RDY2RST)
151 if (type == MLX5_TXQ_MOD_ERR2RDY)
152 attr_mask = IBV_QP_STATE;
153 mod.qp_state = IBV_QPS_INIT;
154 ret = mlx5_glue->modify_qp(obj->qp, &mod, attr_mask);
156 DRV_LOG(ERR, "Cannot change Tx QP state to INIT %s",
161 mod.qp_state = IBV_QPS_RTR;
162 ret = mlx5_glue->modify_qp(obj->qp, &mod, IBV_QP_STATE);
164 DRV_LOG(ERR, "Cannot change Tx QP state to RTR %s",
169 mod.qp_state = IBV_QPS_RTS;
170 ret = mlx5_glue->modify_qp(obj->qp, &mod, IBV_QP_STATE);
172 DRV_LOG(ERR, "Cannot change Tx QP state to RTS %s",
181 * Create a CQ Verbs object.
184 * Pointer to Ethernet device.
186 * Queue index in DPDK Rx queue array.
189 * The Verbs CQ object initialized, NULL otherwise and rte_errno is set.
191 static struct ibv_cq *
192 mlx5_rxq_ibv_cq_create(struct rte_eth_dev *dev, uint16_t idx)
194 struct mlx5_priv *priv = dev->data->dev_private;
195 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
196 struct mlx5_rxq_ctrl *rxq_ctrl =
197 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
198 struct mlx5_rxq_obj *rxq_obj = rxq_ctrl->obj;
199 unsigned int cqe_n = mlx5_rxq_cqe_num(rxq_data);
201 struct ibv_cq_init_attr_ex ibv;
202 struct mlx5dv_cq_init_attr mlx5;
205 cq_attr.ibv = (struct ibv_cq_init_attr_ex){
207 .channel = rxq_obj->ibv_channel,
210 cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){
213 if (priv->config.cqe_comp && !rxq_data->hw_timestamp) {
214 cq_attr.mlx5.comp_mask |=
215 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
216 rxq_data->byte_mask = UINT32_MAX;
217 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
218 if (mlx5_rxq_mprq_enabled(rxq_data)) {
219 cq_attr.mlx5.cqe_comp_res_format =
220 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX;
221 rxq_data->mcqe_format =
222 MLX5_CQE_RESP_FORMAT_CSUM_STRIDX;
224 cq_attr.mlx5.cqe_comp_res_format =
225 MLX5DV_CQE_RES_FORMAT_HASH;
226 rxq_data->mcqe_format =
227 MLX5_CQE_RESP_FORMAT_HASH;
230 cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
231 rxq_data->mcqe_format = MLX5_CQE_RESP_FORMAT_HASH;
234 * For vectorized Rx, it must not be doubled in order to
235 * make cq_ci and rq_ci aligned.
237 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
238 cq_attr.ibv.cqe *= 2;
239 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
241 "Port %u Rx CQE compression is disabled for HW"
245 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
246 if (RTE_CACHE_LINE_SIZE == 128) {
247 cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
248 cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
251 return mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,
257 * Create a WQ Verbs object.
260 * Pointer to Ethernet device.
262 * Queue index in DPDK Rx queue array.
265 * The Verbs WQ object initialized, NULL otherwise and rte_errno is set.
267 static struct ibv_wq *
268 mlx5_rxq_ibv_wq_create(struct rte_eth_dev *dev, uint16_t idx)
270 struct mlx5_priv *priv = dev->data->dev_private;
271 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
272 struct mlx5_rxq_ctrl *rxq_ctrl =
273 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
274 struct mlx5_rxq_obj *rxq_obj = rxq_ctrl->obj;
275 unsigned int wqe_n = 1 << rxq_data->elts_n;
277 struct ibv_wq_init_attr ibv;
278 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
279 struct mlx5dv_wq_init_attr mlx5;
283 wq_attr.ibv = (struct ibv_wq_init_attr){
284 .wq_context = NULL, /* Could be useful in the future. */
285 .wq_type = IBV_WQT_RQ,
286 /* Max number of outstanding WRs. */
287 .max_wr = wqe_n >> rxq_data->sges_n,
288 /* Max number of scatter/gather elements in a WR. */
289 .max_sge = 1 << rxq_data->sges_n,
291 .cq = rxq_obj->ibv_cq,
292 .comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0,
293 .create_flags = (rxq_data->vlan_strip ?
294 IBV_WQ_FLAGS_CVLAN_STRIPPING : 0),
296 /* By default, FCS (CRC) is stripped by hardware. */
297 if (rxq_data->crc_present) {
298 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
299 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
301 if (priv->config.hw_padding) {
302 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
303 wq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
304 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
305 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
306 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
307 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
310 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
311 wq_attr.mlx5 = (struct mlx5dv_wq_init_attr){
314 if (mlx5_rxq_mprq_enabled(rxq_data)) {
315 struct mlx5dv_striding_rq_init_attr *mprq_attr =
316 &wq_attr.mlx5.striding_rq_attrs;
318 wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
319 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
320 .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
321 .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
322 .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
325 rxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,
328 rxq_obj->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);
332 * Make sure number of WRs*SGEs match expectations since a queue
333 * cannot allocate more than "desc" buffers.
335 if (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
336 wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {
338 "Port %u Rx queue %u requested %u*%u but got"
340 dev->data->port_id, idx,
341 wqe_n >> rxq_data->sges_n,
342 (1 << rxq_data->sges_n),
343 wq_attr.ibv.max_wr, wq_attr.ibv.max_sge);
344 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
353 * Create the Rx queue Verbs object.
356 * Pointer to Ethernet device.
358 * Queue index in DPDK Rx queue array.
361 * 0 on success, a negative errno value otherwise and rte_errno is set.
364 mlx5_rxq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx)
366 struct mlx5_priv *priv = dev->data->dev_private;
367 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
368 struct mlx5_rxq_ctrl *rxq_ctrl =
369 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
370 struct mlx5_rxq_obj *tmpl = rxq_ctrl->obj;
371 struct mlx5dv_cq cq_info;
372 struct mlx5dv_rwq rwq;
374 struct mlx5dv_obj obj;
376 MLX5_ASSERT(rxq_data);
378 tmpl->rxq_ctrl = rxq_ctrl;
381 mlx5_glue->create_comp_channel(priv->sh->ctx);
382 if (!tmpl->ibv_channel) {
383 DRV_LOG(ERR, "Port %u: comp channel creation failure.",
388 tmpl->fd = ((struct ibv_comp_channel *)(tmpl->ibv_channel))->fd;
390 /* Create CQ using Verbs API. */
391 tmpl->ibv_cq = mlx5_rxq_ibv_cq_create(dev, idx);
393 DRV_LOG(ERR, "Port %u Rx queue %u CQ creation failure.",
394 dev->data->port_id, idx);
398 obj.cq.in = tmpl->ibv_cq;
399 obj.cq.out = &cq_info;
400 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ);
405 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
407 "Port %u wrong MLX5_CQE_SIZE environment "
408 "variable value: it should be set to %u.",
409 dev->data->port_id, RTE_CACHE_LINE_SIZE);
413 /* Fill the rings. */
414 rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
415 rxq_data->cq_db = cq_info.dbrec;
416 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
417 rxq_data->cq_uar = cq_info.cq_uar;
418 rxq_data->cqn = cq_info.cqn;
419 /* Create WQ (RQ) using Verbs API. */
420 tmpl->wq = mlx5_rxq_ibv_wq_create(dev, idx);
422 DRV_LOG(ERR, "Port %u Rx queue %u WQ creation failure.",
423 dev->data->port_id, idx);
427 /* Change queue state to ready. */
428 ret = mlx5_ibv_modify_wq(tmpl, IBV_WQS_RDY);
431 "Port %u Rx queue %u WQ state to IBV_WQS_RDY failed.",
432 dev->data->port_id, idx);
436 obj.rwq.in = tmpl->wq;
438 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_RWQ);
443 rxq_data->wqes = rwq.buf;
444 rxq_data->rq_db = rwq.dbrec;
445 rxq_data->cq_arm_sn = 0;
446 mlx5_rxq_initialize(rxq_data);
448 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
449 rxq_ctrl->wqn = ((struct ibv_wq *)(tmpl->wq))->wq_num;
452 ret = rte_errno; /* Save rte_errno before cleanup. */
454 claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
456 claim_zero(mlx5_glue->destroy_cq(tmpl->ibv_cq));
457 if (tmpl->ibv_channel)
458 claim_zero(mlx5_glue->destroy_comp_channel(tmpl->ibv_channel));
459 rte_errno = ret; /* Restore rte_errno. */
464 * Release an Rx verbs queue object.
467 * Verbs Rx queue object.
470 mlx5_rxq_ibv_obj_release(struct mlx5_rxq_obj *rxq_obj)
472 MLX5_ASSERT(rxq_obj);
473 MLX5_ASSERT(rxq_obj->wq);
474 MLX5_ASSERT(rxq_obj->ibv_cq);
475 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
476 claim_zero(mlx5_glue->destroy_cq(rxq_obj->ibv_cq));
477 if (rxq_obj->ibv_channel)
478 claim_zero(mlx5_glue->destroy_comp_channel
479 (rxq_obj->ibv_channel));
483 * Get event for an Rx verbs queue object.
486 * Verbs Rx queue object.
489 * 0 on success, a negative errno value otherwise and rte_errno is set.
492 mlx5_rx_ibv_get_event(struct mlx5_rxq_obj *rxq_obj)
494 struct ibv_cq *ev_cq;
496 int ret = mlx5_glue->get_cq_event(rxq_obj->ibv_channel,
499 if (ret < 0 || ev_cq != rxq_obj->ibv_cq)
501 mlx5_glue->ack_cq_events(rxq_obj->ibv_cq, 1);
512 * Creates a receive work queue as a filed of indirection table.
515 * Pointer to Ethernet device.
517 * Log of number of queues in the array.
519 * Verbs indirection table object.
522 * 0 on success, a negative errno value otherwise and rte_errno is set.
525 mlx5_ibv_ind_table_new(struct rte_eth_dev *dev, const unsigned int log_n,
526 struct mlx5_ind_table_obj *ind_tbl)
528 struct mlx5_priv *priv = dev->data->dev_private;
529 struct ibv_wq *wq[1 << log_n];
532 MLX5_ASSERT(ind_tbl);
533 for (i = 0; i != ind_tbl->queues_n; ++i) {
534 struct mlx5_rxq_data *rxq = (*priv->rxqs)[ind_tbl->queues[i]];
535 struct mlx5_rxq_ctrl *rxq_ctrl =
536 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
538 wq[i] = rxq_ctrl->obj->wq;
541 /* Finalise indirection table. */
542 for (j = 0; i != (unsigned int)(1 << log_n); ++j, ++i)
544 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table(priv->sh->ctx,
545 &(struct ibv_rwq_ind_table_init_attr){
546 .log_ind_tbl_size = log_n,
550 if (!ind_tbl->ind_table) {
558 * Destroys the specified Indirection Table.
561 * Indirection table to release.
564 mlx5_ibv_ind_table_destroy(struct mlx5_ind_table_obj *ind_tbl)
566 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
570 * Create an Rx Hash queue.
573 * Pointer to Ethernet device.
575 * Pointer to Rx Hash queue.
580 * 0 on success, a negative errno value otherwise and rte_errno is set.
583 mlx5_ibv_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
584 int tunnel __rte_unused)
586 struct mlx5_priv *priv = dev->data->dev_private;
587 struct ibv_qp *qp = NULL;
588 struct mlx5_ind_table_obj *ind_tbl = hrxq->ind_table;
589 const uint8_t *rss_key = hrxq->rss_key;
590 uint64_t hash_fields = hrxq->hash_fields;
592 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
593 struct mlx5dv_qp_init_attr qp_init_attr;
595 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
597 qp_init_attr.comp_mask =
598 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
599 qp_init_attr.create_flags = MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
601 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
602 if (dev->data->dev_conf.lpbk_mode) {
603 /* Allow packet sent from NIC loop back w/o source MAC check. */
604 qp_init_attr.comp_mask |=
605 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
606 qp_init_attr.create_flags |=
607 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
610 qp = mlx5_glue->dv_create_qp
612 &(struct ibv_qp_init_attr_ex){
613 .qp_type = IBV_QPT_RAW_PACKET,
615 IBV_QP_INIT_ATTR_PD |
616 IBV_QP_INIT_ATTR_IND_TABLE |
617 IBV_QP_INIT_ATTR_RX_HASH,
618 .rx_hash_conf = (struct ibv_rx_hash_conf){
620 IBV_RX_HASH_FUNC_TOEPLITZ,
621 .rx_hash_key_len = hrxq->rss_key_len,
623 (void *)(uintptr_t)rss_key,
624 .rx_hash_fields_mask = hash_fields,
626 .rwq_ind_tbl = ind_tbl->ind_table,
631 qp = mlx5_glue->create_qp_ex
633 &(struct ibv_qp_init_attr_ex){
634 .qp_type = IBV_QPT_RAW_PACKET,
636 IBV_QP_INIT_ATTR_PD |
637 IBV_QP_INIT_ATTR_IND_TABLE |
638 IBV_QP_INIT_ATTR_RX_HASH,
639 .rx_hash_conf = (struct ibv_rx_hash_conf){
641 IBV_RX_HASH_FUNC_TOEPLITZ,
642 .rx_hash_key_len = hrxq->rss_key_len,
644 (void *)(uintptr_t)rss_key,
645 .rx_hash_fields_mask = hash_fields,
647 .rwq_ind_tbl = ind_tbl->ind_table,
656 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
657 hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
665 err = rte_errno; /* Save rte_errno before cleanup. */
667 claim_zero(mlx5_glue->destroy_qp(qp));
668 rte_errno = err; /* Restore rte_errno. */
673 * Destroy a Verbs queue pair.
676 * Hash Rx queue to release its qp.
679 mlx5_ibv_qp_destroy(struct mlx5_hrxq *hrxq)
681 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
685 * Release a drop Rx queue Verbs object.
688 * Pointer to Ethernet device.
691 mlx5_rxq_ibv_obj_drop_release(struct rte_eth_dev *dev)
693 struct mlx5_priv *priv = dev->data->dev_private;
694 struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
697 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
699 claim_zero(mlx5_glue->destroy_cq(rxq->ibv_cq));
701 priv->drop_queue.rxq = NULL;
705 * Create a drop Rx queue Verbs object.
708 * Pointer to Ethernet device.
711 * 0 on success, a negative errno value otherwise and rte_errno is set.
714 mlx5_rxq_ibv_obj_drop_create(struct rte_eth_dev *dev)
716 struct mlx5_priv *priv = dev->data->dev_private;
717 struct ibv_context *ctx = priv->sh->ctx;
718 struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
722 rxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rxq), 0, SOCKET_ID_ANY);
724 DEBUG("Port %u cannot allocate drop Rx queue memory.",
729 priv->drop_queue.rxq = rxq;
730 rxq->ibv_cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
732 DEBUG("Port %u cannot allocate CQ for drop queue.",
737 rxq->wq = mlx5_glue->create_wq(ctx, &(struct ibv_wq_init_attr){
738 .wq_type = IBV_WQT_RQ,
745 DEBUG("Port %u cannot allocate WQ for drop queue.",
750 priv->drop_queue.rxq = rxq;
753 mlx5_rxq_ibv_obj_drop_release(dev);
758 * Create a Verbs drop action for Rx Hash queue.
761 * Pointer to Ethernet device.
764 * 0 on success, a negative errno value otherwise and rte_errno is set.
767 mlx5_ibv_drop_action_create(struct rte_eth_dev *dev)
769 struct mlx5_priv *priv = dev->data->dev_private;
770 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
771 struct ibv_rwq_ind_table *ind_tbl = NULL;
772 struct mlx5_rxq_obj *rxq;
775 MLX5_ASSERT(hrxq && hrxq->ind_table);
776 ret = mlx5_rxq_ibv_obj_drop_create(dev);
779 rxq = priv->drop_queue.rxq;
780 ind_tbl = mlx5_glue->create_rwq_ind_table
782 &(struct ibv_rwq_ind_table_init_attr){
783 .log_ind_tbl_size = 0,
784 .ind_tbl = (struct ibv_wq **)&rxq->wq,
788 DEBUG("Port %u cannot allocate indirection table for drop"
789 " queue.", dev->data->port_id);
793 hrxq->qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
794 &(struct ibv_qp_init_attr_ex){
795 .qp_type = IBV_QPT_RAW_PACKET,
796 .comp_mask = IBV_QP_INIT_ATTR_PD |
797 IBV_QP_INIT_ATTR_IND_TABLE |
798 IBV_QP_INIT_ATTR_RX_HASH,
799 .rx_hash_conf = (struct ibv_rx_hash_conf){
800 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,
801 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
802 .rx_hash_key = rss_hash_default_key,
803 .rx_hash_fields_mask = 0,
805 .rwq_ind_tbl = ind_tbl,
809 DEBUG("Port %u cannot allocate QP for drop queue.",
814 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
815 hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
821 hrxq->ind_table->ind_table = ind_tbl;
825 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
827 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl));
828 if (priv->drop_queue.rxq)
829 mlx5_rxq_ibv_obj_drop_release(dev);
834 * Release a drop hash Rx queue.
837 * Pointer to Ethernet device.
840 mlx5_ibv_drop_action_destroy(struct rte_eth_dev *dev)
842 struct mlx5_priv *priv = dev->data->dev_private;
843 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
844 struct ibv_rwq_ind_table *ind_tbl = hrxq->ind_table->ind_table;
846 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
847 claim_zero(mlx5_glue->destroy_flow_action(hrxq->action));
849 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
850 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl));
851 mlx5_rxq_ibv_obj_drop_release(dev);
855 * Create a QP Verbs object.
858 * Pointer to Ethernet device.
860 * Queue index in DPDK Tx queue array.
863 * The QP Verbs object, NULL otherwise and rte_errno is set.
865 static struct ibv_qp *
866 mlx5_txq_ibv_qp_create(struct rte_eth_dev *dev, uint16_t idx)
868 struct mlx5_priv *priv = dev->data->dev_private;
869 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
870 struct mlx5_txq_ctrl *txq_ctrl =
871 container_of(txq_data, struct mlx5_txq_ctrl, txq);
872 struct ibv_qp *qp_obj = NULL;
873 struct ibv_qp_init_attr_ex qp_attr = { 0 };
874 const int desc = 1 << txq_data->elts_n;
876 MLX5_ASSERT(txq_ctrl->obj->cq);
877 /* CQ to be associated with the send queue. */
878 qp_attr.send_cq = txq_ctrl->obj->cq;
879 /* CQ to be associated with the receive queue. */
880 qp_attr.recv_cq = txq_ctrl->obj->cq;
881 /* Max number of outstanding WRs. */
882 qp_attr.cap.max_send_wr = ((priv->sh->device_attr.max_qp_wr < desc) ?
883 priv->sh->device_attr.max_qp_wr : desc);
885 * Max number of scatter/gather elements in a WR, must be 1 to prevent
886 * libmlx5 from trying to affect must be 1 to prevent libmlx5 from
887 * trying to affect too much memory. TX gather is not impacted by the
888 * device_attr.max_sge limit and will still work properly.
890 qp_attr.cap.max_send_sge = 1;
891 qp_attr.qp_type = IBV_QPT_RAW_PACKET,
892 /* Do *NOT* enable this, completions events are managed per Tx burst. */
893 qp_attr.sq_sig_all = 0;
894 qp_attr.pd = priv->sh->pd;
895 qp_attr.comp_mask = IBV_QP_INIT_ATTR_PD;
896 if (txq_data->inlen_send)
897 qp_attr.cap.max_inline_data = txq_ctrl->max_inline_data;
898 if (txq_data->tso_en) {
899 qp_attr.max_tso_header = txq_ctrl->max_tso_header;
900 qp_attr.comp_mask |= IBV_QP_INIT_ATTR_MAX_TSO_HEADER;
902 qp_obj = mlx5_glue->create_qp_ex(priv->sh->ctx, &qp_attr);
903 if (qp_obj == NULL) {
904 DRV_LOG(ERR, "Port %u Tx queue %u QP creation failure.",
905 dev->data->port_id, idx);
912 * Create the Tx queue Verbs object.
915 * Pointer to Ethernet device.
917 * Queue index in DPDK Tx queue array.
920 * 0 on success, a negative errno value otherwise and rte_errno is set.
923 mlx5_txq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx)
925 struct mlx5_priv *priv = dev->data->dev_private;
926 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
927 struct mlx5_txq_ctrl *txq_ctrl =
928 container_of(txq_data, struct mlx5_txq_ctrl, txq);
929 struct mlx5_txq_obj *txq_obj = txq_ctrl->obj;
932 struct mlx5dv_cq cq_info;
933 struct mlx5dv_obj obj;
934 const int desc = 1 << txq_data->elts_n;
937 MLX5_ASSERT(txq_data);
938 MLX5_ASSERT(txq_obj);
939 txq_obj->txq_ctrl = txq_ctrl;
940 if (mlx5_getenv_int("MLX5_ENABLE_CQE_COMPRESSION")) {
941 DRV_LOG(ERR, "Port %u MLX5_ENABLE_CQE_COMPRESSION "
942 "must never be set.", dev->data->port_id);
946 cqe_n = desc / MLX5_TX_COMP_THRESH +
947 1 + MLX5_TX_COMP_THRESH_INLINE_DIV;
948 txq_obj->cq = mlx5_glue->create_cq(priv->sh->ctx, cqe_n, NULL, NULL, 0);
949 if (txq_obj->cq == NULL) {
950 DRV_LOG(ERR, "Port %u Tx queue %u CQ creation failure.",
951 dev->data->port_id, idx);
955 txq_obj->qp = mlx5_txq_ibv_qp_create(dev, idx);
956 if (txq_obj->qp == NULL) {
960 ret = mlx5_ibv_modify_qp(txq_obj, MLX5_TXQ_MOD_RST2RDY,
961 (uint8_t)priv->dev_port);
963 DRV_LOG(ERR, "Port %u Tx queue %u QP state modifying failed.",
964 dev->data->port_id, idx);
968 qp.comp_mask = MLX5DV_QP_MASK_UAR_MMAP_OFFSET;
969 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
970 /* If using DevX, need additional mask to read tisn value. */
971 if (priv->sh->devx && !priv->sh->tdn)
972 qp.comp_mask |= MLX5DV_QP_MASK_RAW_QP_HANDLES;
974 obj.cq.in = txq_obj->cq;
975 obj.cq.out = &cq_info;
976 obj.qp.in = txq_obj->qp;
978 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_QP);
983 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
985 "Port %u wrong MLX5_CQE_SIZE environment variable"
986 " value: it should be set to %u.",
987 dev->data->port_id, RTE_CACHE_LINE_SIZE);
991 txq_data->cqe_n = log2above(cq_info.cqe_cnt);
992 txq_data->cqe_s = 1 << txq_data->cqe_n;
993 txq_data->cqe_m = txq_data->cqe_s - 1;
994 txq_data->qp_num_8s = ((struct ibv_qp *)txq_obj->qp)->qp_num << 8;
995 txq_data->wqes = qp.sq.buf;
996 txq_data->wqe_n = log2above(qp.sq.wqe_cnt);
997 txq_data->wqe_s = 1 << txq_data->wqe_n;
998 txq_data->wqe_m = txq_data->wqe_s - 1;
999 txq_data->wqes_end = txq_data->wqes + txq_data->wqe_s;
1000 txq_data->qp_db = &qp.dbrec[MLX5_SND_DBR];
1001 txq_data->cq_db = cq_info.dbrec;
1002 txq_data->cqes = (volatile struct mlx5_cqe *)cq_info.buf;
1003 txq_data->cq_ci = 0;
1004 txq_data->cq_pi = 0;
1005 txq_data->wqe_ci = 0;
1006 txq_data->wqe_pi = 0;
1007 txq_data->wqe_comp = 0;
1008 txq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV;
1009 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1011 * If using DevX need to query and store TIS transport domain value.
1012 * This is done once per port.
1013 * Will use this value on Rx, when creating matching TIR.
1015 if (priv->sh->devx && !priv->sh->tdn) {
1016 ret = mlx5_devx_cmd_qp_query_tis_td(txq_obj->qp, qp.tisn,
1019 DRV_LOG(ERR, "Fail to query port %u Tx queue %u QP TIS "
1020 "transport domain.", dev->data->port_id, idx);
1024 DRV_LOG(DEBUG, "Port %u Tx queue %u TIS number %d "
1025 "transport domain %d.", dev->data->port_id,
1026 idx, qp.tisn, priv->sh->tdn);
1030 txq_ctrl->bf_reg = qp.bf.reg;
1031 if (qp.comp_mask & MLX5DV_QP_MASK_UAR_MMAP_OFFSET) {
1032 txq_ctrl->uar_mmap_offset = qp.uar_mmap_offset;
1033 DRV_LOG(DEBUG, "Port %u: uar_mmap_offset 0x%" PRIx64 ".",
1034 dev->data->port_id, txq_ctrl->uar_mmap_offset);
1037 "Port %u failed to retrieve UAR info, invalid"
1039 dev->data->port_id);
1043 txq_uar_init(txq_ctrl);
1044 dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
1047 ret = rte_errno; /* Save rte_errno before cleanup. */
1049 claim_zero(mlx5_glue->destroy_cq(txq_obj->cq));
1051 claim_zero(mlx5_glue->destroy_qp(txq_obj->qp));
1052 rte_errno = ret; /* Restore rte_errno. */
1057 * Release an Tx verbs queue object.
1060 * Verbs Tx queue object..
1063 mlx5_txq_ibv_obj_release(struct mlx5_txq_obj *txq_obj)
1065 MLX5_ASSERT(txq_obj);
1066 claim_zero(mlx5_glue->destroy_qp(txq_obj->qp));
1067 claim_zero(mlx5_glue->destroy_cq(txq_obj->cq));
1070 struct mlx5_obj_ops ibv_obj_ops = {
1071 .rxq_obj_modify_vlan_strip = mlx5_rxq_obj_modify_wq_vlan_strip,
1072 .rxq_obj_new = mlx5_rxq_ibv_obj_new,
1073 .rxq_event_get = mlx5_rx_ibv_get_event,
1074 .rxq_obj_modify = mlx5_ibv_modify_wq,
1075 .rxq_obj_release = mlx5_rxq_ibv_obj_release,
1076 .ind_table_new = mlx5_ibv_ind_table_new,
1077 .ind_table_destroy = mlx5_ibv_ind_table_destroy,
1078 .hrxq_new = mlx5_ibv_hrxq_new,
1079 .hrxq_destroy = mlx5_ibv_qp_destroy,
1080 .drop_action_create = mlx5_ibv_drop_action_create,
1081 .drop_action_destroy = mlx5_ibv_drop_action_destroy,
1082 .txq_obj_new = mlx5_txq_ibv_obj_new,
1083 .txq_obj_modify = mlx5_ibv_modify_qp,
1084 .txq_obj_release = mlx5_txq_ibv_obj_release,